Semiconductor structure and preparation method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate; the base comprises a substrate and a gate structure; a well region, a source-drain region and a lightly doped region are formed on the substrate; wherein the well region comprises a channel region; the gate structure is arranged on the surface of the channel region; the lightly doped region is located between the source drain region and the channel region; a contact structure; the contact structure is arranged on the surface of the source-drain region; wherein an air gap located on the lightly doped region is formed between the contact structure and the gate structure. Therefore, ions can be injected into the lightly doped region through the air gap so as to make up the loss of the ions in the lightly doped region in the preparation process.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] In order to achieve the target threshold voltage Vt and off-current Ioff of existing MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices, the gate material size and gate sidewall thickness are usually increased, resulting in insufficient contact structure (CT) size in the source and drain regions.

[0003] In the related art, in order to increase the size of the contact structure of the source and drain regions, it is usually necessary to perform a gate sidewall removal process before fabricating the contact structure of the source and drain regions.

[0004] However, during the process of removing the gate sidewalls and subsequently forming the source and drain contact structures, overetching, misalignment, and other factors can cause a certain degree of damage to the ions already implanted in the lightly doped drain (LDD) region. This can lead to high resistance in the channel direction of the MOSFET device, affecting device performance. For example, in a pull-up transistor (PU), the high resistance in the channel direction of the MOSFET device can easily cause the pull-up transistor to fail under high-voltage operation. Summary of the Invention

[0005] In view of this, multiple embodiments of this specification are dedicated to providing a semiconductor structure and a method for manufacturing the same, which can reduce the impact of ion loss in the lightly doped region during the manufacturing process on device performance.

[0006] One embodiment of the present specification provides a semiconductor structure, comprising: a substrate; the substrate comprising a substrate and a gate structure; the substrate is formed with a well region, a source / drain region, and a lightly doped region; wherein the well region comprises a channel region; the gate structure is arranged on the surface of the channel region; the lightly doped region is located between the source / drain region and the channel region; a contact structure; the contact structure is arranged on the surface of the source / drain region; wherein an air gap is formed between the contact structure and the gate structure and is located on the lightly doped region.

[0007] Optionally, the width of the air gap is consistent with the width of the lightly doped region.

[0008] Optionally, the contact structure includes a metal contact portion and a contact connection portion; the contact connection portion includes a bottom connection layer formed on the surface of the source and drain region, and a connection side wall located at the edges of both sides of the bottom connection layer; wherein the bottom connection layer and the connection side wall form a contact window; the metal contact portion is filled and formed in the contact window.

[0009] Optionally, the contact portion is made of metal silicide.

[0010] One embodiment of the present specification provides a method for preparing a semiconductor structure, the method comprising: providing a substrate; the substrate comprising a substrate and a gate structure; the substrate being formed with a well region, a source-drain doped region and a lightly doped region; wherein the well region comprises a channel region; the gate structure is arranged on the surface of the channel region; the lightly doped region is located between the source-drain doped region and the channel region; forming isolation sidewalls on both sides of the gate structure; the isolation sidewalls are located on the lightly doped region; forming a contact structure on the side of the isolation sidewall that contacts the source-drain doped region; and removing the isolation sidewalls to form an air gap between the gate structure and the contact structure on the lightly doped region.

[0011] Optionally, the step of removing the isolation spacer includes: removing the isolation spacer based on an etching process; wherein the isolation spacer has a high etching selectivity with respect to both the gate structure and the contact structure.

[0012] Optionally, the step of forming a contact structure on the side of the isolation side wall that contacts the source and drain doped regions includes: forming a polysilicon side wall on the side of the isolation side wall; the polysilicon side wall is located on the edge of the source and drain doped region close to the lightly doped region; making metal silicide on the surface of the polysilicon side wall and the source and drain doped region to form a contact connection portion; wherein the contact connection portion includes a connection side wall formed by the polysilicon side wall, and a bottom connection layer formed by the substrate located in the source and drain region; the bottom connection layer and the connection side wall form a contact window; and a metal contact portion is filled in the contact window to form the contact structure.

[0013] Optionally, the method for preparing the semiconductor structure further includes: supplementally injecting ions into the lightly doped region through the air gap.

[0014] Optionally, the step of providing a substrate includes: providing an intermediate structure; the intermediate structure includes the substrate, a gate intermediate structure formed on the surface of the channel region, and at least one layer of gate sidewall formed on the surface of the lightly doped region; wherein the gate intermediate structure includes a gate material and a gate oxide layer; removing the at least one layer of gate sidewall; forming a dielectric layer on the gate intermediate structure; and etching the dielectric layer to form the substrate.

[0015] Optionally, the step of etching the dielectric layer to form the gate structure includes: stacking a hard mask layer, at least one anti-reflective layer, and a photoresist layer on the dielectric layer; exposing and developing the photoresist layer corresponding to the position of the source and drain doping regions; forming an opening aligned with the etching position after development in the photoresist layer; wherein the width of the opening is greater than the width of the source and drain doping regions; etching the dielectric layer using the opening as a position reference; and removing the at least one anti-reflective layer and the hard mask layer to obtain the substrate.

[0016] The unexpected effect of the multiple implementations provided in this specification is that after an air gap is set between the contact structure and the gate structure on the lightly doped region, ions can be injected into the lightly doped region through the air gap to compensate for the loss of ions in the lightly doped region during the preparation process, thereby avoiding to a certain extent the high resistance in the channel direction caused by the loss of ions in the lightly doped region and reducing the impact on device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a semiconductor structure provided for one embodiment of this specification.

[0018] Figure 2 A schematic diagram of a method for preparing a semiconductor structure provided in another embodiment of this specification.

[0019] Figure 3 This is a schematic diagram of an intermediate structure in the method for preparing a semiconductor structure provided in this specification.

[0020] Figure 4 This is a schematic diagram of removing the gate sidewall in the method for preparing the semiconductor structure provided in this specification.

[0021] Figure 5 This is a schematic diagram of forming a dielectric layer in the method for preparing a semiconductor structure provided in this specification.

[0022] Figure 6 This is a schematic diagram of etching a dielectric layer in the method for preparing a semiconductor structure provided in this specification.

[0023] Figure 7This is a schematic diagram of a substrate formed in the method for preparing a semiconductor structure provided in this specification.

[0024] Figure 8 This is a schematic diagram of forming isolation sidewalls and polysilicon sidewalls in the method for preparing a semiconductor structure provided in this specification.

[0025] Figure 9 This is a schematic diagram of forming a contact portion in the method for preparing a semiconductor structure provided in this specification.

[0026] Figure 10 This is a schematic diagram of providing a metal contact portion in the method for preparing a semiconductor structure provided in this specification.

[0027] Figure 11 This is a schematic diagram of removing the isolation sidewall in the method for preparing the semiconductor structure provided in this specification.

[0028] Figure 12 This is a schematic diagram of sealing the air gap in the method for preparing the semiconductor structure provided in this specification.

[0029] Description of reference numerals: 10. Semiconductor structure; 11. Base; 12. Substrate; 13. Gate structure; 121. Well region; 122. Source and drain regions; 123. Lightly doped region; 124. Channel region; 14. Contact structure; 15. Air gap; 16. Metal contact; 161. Transition layer; 162. Metal material; 17. Contact connection; 171. Bottom connection layer; 172. Connection sidewall; 18. Contact window; 20. Intermediate structure; 21. Gate intermediate structure; 211. Gate material; 212. Gate oxide layer; 22. Gate sidewall; 23. Dielectric layer; 24. Hard mask layer; 25. Anti-reflective coating; 251. Silicon oxynitride; 252. Silicon dioxide; 253. Bottom anti-reflective coating; 26. Photoresist layer; 27. Opening; 28. Source and drain doped regions; 29. ​​Isolation sidewall; 31. Polysilicon sidewall. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of this specification will be described clearly and completely below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments.

[0031] In this specification, the drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show details of the local features.

[0032] Unless otherwise indicated, all technical and scientific terms used in this specification have the same meaning as those commonly understood by those skilled in the art in the technical field of this specification. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the scope of this specification. The term "and / or" used in this specification includes any and all combinations of one or more related listed items. The singular forms "a", "above", and "the" used in the embodiments of this specification and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0033] In the description of this specification, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this specification, the meaning of "plurality" is two or more, unless otherwise explicitly and specifically defined.

[0034] In the description of this specification, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "height", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of a simplified description of this application, and do not indicate that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and should not be understood as a limitation to this application.

[0035] Throughout this specification, unless otherwise expressly defined, the terms "installed," "connected," "connect," "fixed," and "disposed" should be interpreted broadly. For example, "connection" can refer to fixed or removable connections, or integration; mechanical or electrical connections; direct or indirect connections through an intermediary; or internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0036] In the description of this specification, unless otherwise explicitly defined, when a first feature is “on,” “above,” “above,” “above,” “below,” “below,” or “below” a second feature, the first feature and the second feature may be in direct contact, or the first feature and the second feature may be in indirect contact via an intermediate medium. Moreover, when a first feature is “on,” “above,” or “above” a second feature, it may mean that the first feature is directly above or obliquely above the second feature, or simply means that the horizontal height of the first feature is higher than the horizontal height of the second feature. When a first feature is “below,” “below,” or “below” a second feature, it may mean that the first feature is directly below or obliquely below the second feature, or simply means that the horizontal height of the first feature is lower than the horizontal height of the second feature.

[0037] During the preparation process of MOS devices, based on the front-end process, a well region, gate oxide layer, gate polysilicon, gate sidewall, lightly doped region, pocket region, source and drain region and metal silicide can be formed.

[0038] To increase the size of the source / drain contact structures, gate spacer removal is typically required before contact formation. However, during the gate spacer removal and subsequent source / drain contact formation processes, ions implanted in the lightly doped drain (LDD) region can be damaged to a certain extent. Specifically, the gate spacer removal process, as well as alignment errors and overetching during the etching process, can damage the doped ions in the LDD region. Furthermore, when metal silicides, such as nickel silicide (NiSi), are formed in the source / drain regions, they can interact with doped ions, such as boron ions, in the LDD region, causing ion loss. This, in turn, reduces the doping concentration in the LDD region, resulting in high resistance in the channel direction of the MOS device, impacting its performance. For example, this high resistance in the channel direction can lead to poor reliability of the MOS device under high-voltage operating conditions.

[0039] Therefore, it is necessary to provide a semiconductor structure that can reduce the impact of ion loss in the lightly doped region during the preparation process on device performance.

[0040] See also Figure 1One embodiment of the present specification provides a semiconductor structure 10, which may be a MOS structure. The semiconductor structure 10 includes a base 11 and a contact structure 14. The base 11 includes a substrate 12 and a gate structure 13; the substrate 12 is formed with a well region 121, a source / drain region 122, and a lightly doped region 123; wherein the well region 121 includes a channel region 124; the gate structure 13 is disposed on the surface of the channel region 124; and the lightly doped region 123 is located between the source / drain region 122 and the channel region 124.

[0041] The substrate 12 serves as the foundation of the semiconductor structure 10, providing mechanical support and, through ion doping, affecting the device's electrical properties, such as threshold voltage and carrier mobility. Specifically, the substrate 12 may be made of silicon (Si) or, as required, other semiconductor materials, such as silicon carbide (SiC) or gallium nitride (GaN).

[0042] The gate structure 13 can be used to control the switching behavior of the MOS structure. Specifically, the gate structure 13 can be composed of a gate material and a gate oxide layer. As the gate electrode, the gate material can be polysilicon or a metal (such as aluminum). The gate material can be isolated from the substrate by the gate oxide layer. The gate oxide layer can specifically be silicon dioxide (SiO2). In some possible embodiments, the gate structure 13 can also include a work function adjustment layer. When a voltage is applied to the gate structure 13, carriers in the channel region 124 can be attracted or repelled, thereby controlling the flow of carriers between the source and drain electrodes.

[0043] Well region 121 is a doped region formed in substrate 12 that isolates different types of MOS structures within semiconductor structure 10 and provides a suitable electrical environment to ensure proper operation of semiconductor structure 10. Specifically, well region 121 can be P-type or N-type, depending on the type of MOS to be constructed (e.g., NMOS or PMOS). The doping concentration of well region 121 is typically higher than that of substrate 12 but lower than that of source and drain regions 122.

[0044] The source and drain (S / D) regions 122 are highly doped regions in the substrate 12, forming the source and drain, respectively. The doping concentration of the source and drain regions 122 is typically higher than that of the substrate 12 and the well region 121 to ensure low contact resistance and good current transfer. Under operating conditions, a conductive path is formed between the source and drain, allowing carriers to flow from the source to the drain, generating current. The high doping concentration of the source and drain regions 122 ensures a low-resistance connection between the source and drain.

[0045] The channel region 124 is located between the source and drain regions 122 on both sides of the gate structure 13. When a proper voltage is applied to the gate, the channel region 124 forms a conductive channel, thereby forming a current between the source and the drain.

[0046] The lightly doped drain (LDD) region 123 is a low-doped region located between the source / drain region 122 and the channel region 124. It reduces the electric field strength between the source / drain region 122 and the channel, thereby reducing the rate of electron and hole injection, thereby reducing the hot carrier effect and improving the reliability of the MOS structure. The doping concentration of the lightly doped region 123 is lower than that of the source / drain region 122, but higher than that of the well region 121.

[0047] The contact structure 14 is used to establish an electrical connection between the source and drain regions 122 and an external circuit. The contact structure 14 is provided on the surface of the source and drain regions 122. The contact structure 14 can be formed by depositing one or more layers of metal. Specifically, the metal used to form the contact structure 14 may include aluminum (Al), copper (Cu), tungsten (W), or other alloys. In some embodiments, the contact structure 14 may also include a metal silicide located between the metal layer and the substrate 12. The metal silicide can be used as a contact connection between the metal layer and the substrate 12 to reduce contact resistance. Specifically, the metal silicide can be nickel silicide NiSi, or can be titanium silicide TiSi2, cobalt silicide CoSi2, etc.

[0048] In this embodiment, an air gap 15 is formed between the contact structure 14 and the gate structure 13 and is located on the surface of the lightly doped region 123. Specifically, perpendicular to the surface of the substrate 12, the air gap 15 corresponding to the region on the substrate 12 may overlap with the lightly doped region 123. In some possible embodiments, the air gap 15 corresponding to the region on the substrate 12 may also partially overlap with the lightly doped region 123.

[0049] An unexpected effect of this embodiment is that after the contact structure 14 is formed, the consumed dopant ions can be replenished into the lightly doped region 123 through the air gap 15 to maintain the original ion concentration of the lightly doped region 123. This prevents high resistance in the channel direction caused by ion loss in the lightly doped region 123, which in turn affects the performance of the semiconductor structure 10. Furthermore, the air gap 15 has a relatively low dielectric constant K, which can reduce RC delay.

[0050] Furthermore, in related art, the removal of the gate sidewall spacers can cause the enlarged contact structure to directly contact portions of the lightly doped regions. Furthermore, alignment errors during contact structure fabrication can also cause the contact structure to directly contact portions of the lightly doped regions, which can also increase resistance in the channel direction. Providing an air gap 15 above the lightly doped regions 123 can also reduce or prevent direct contact between the contact structure 14 and the lightly doped regions 123.

[0051] To illustrate the technical effects of this embodiment, this specification also provides the simulation data in Table 1 as follows: Table 1 In Table 1, the parameters in the "LDD Ion Implantation" and "S / D Ion Implantation" columns indicate the ion type, energy, and dose implanted in the LDD and S / D regions, respectively. The data in the "Z Depth" and "Y Channel" columns indicate the etch depths in the Z and Y directions, respectively. Vt, Idsat, and Ioff represent the PMOS threshold voltage, saturation current, and off-state current, respectively.

[0052] The data in Table 1 shows that, in the case of a Schottky contact, Idsat decreases as etching damage to the ion-doped region increases. However, increasing the ion implantation dose in the LDD and S / D regions (data highlighted in black in Table 1) can increase Idsat.

[0053] Optionally, the width of the air gap 15 is consistent with the width of the lightly doped region 123. Specifically, taking the 40nm process node as an example, the width of the air gap 15 ranges from 10nm to 20nm. For example, the width of the air gap 15 can be 10nm or 20nm, or 15nm. It should be noted that in some possible embodiments, the width of the air gap 15 can also be different from the width of the lightly doped region 123, for example, greater than or less than the width of the lightly doped region 123.

[0054] In this embodiment, the contact structure 14 includes a metal contact portion 16 and a contact connection portion 17; the contact connection portion 17 includes a bottom connection layer 171 formed on the surface of the source and drain region 122, and a connection side wall 172 located on both side edges of the bottom connection layer 171; wherein the bottom connection layer 171 and the connection side wall 172 form a contact window 18; the metal contact portion 16 is formed in the contact window 18.

[0055] The contact portion 17 may be made of metal silicide. Optionally, the contact portion 17 is made of nickel silicide.

[0056] The contact window 18 formed by the bottom connecting layer 171 and the connecting sidewall 172 wraps the metal contact portion 16 , which can further reduce the contact resistance compared to only providing the bottom connecting layer 171 on the surface of the drain and source regions.

[0057] The metal contact portion 16 is composed of a metal material 162, such as tungsten (W), and a transition layer 161 disposed on the surface of the contact interface portion 17 facing the metal material 162. The transition layer 161 can be made of titanium (Ti) or titanium nitride (TiN) and serves as a barrier and buffer between the metal material 162 and the contact interface portion 17, thereby improving contact performance.

[0058] It should be noted that, in some possible implementations, the contact structure 14 may not include the contact connection portion 17 .

[0059] Optionally, the thickness of the connecting sidewall spacer 172 ranges from 5 nm to 15 nm. Specifically, taking the 40 nm process node as an example, the thickness of the connecting sidewall spacer 172 can be 5 nm, 15 nm, or even 10 nm.

[0060] See also Figure 2-Figure 12 One embodiment of the present specification provides a method for preparing a semiconductor structure, which may include the following steps.

[0061] S110: Provide a substrate 11; the substrate 11 includes a substrate 12 and a gate structure 13; the substrate 12 is formed with a well region 121, a source-drain doped region 28 and a lightly doped region 123; wherein the well region 121 includes a channel region 124; the gate structure 13 is arranged on the surface of the channel region 124; the lightly doped region 123 is located between the source-drain doped region 28 and the channel region 124.

[0062] Please refer to Figure 7 In this embodiment, the source / drain doped region 28 may include a source / drain region 122. Compared to the source / drain region 122 in the previous embodiment, a bottom connection layer 171 is not formed near the surface. The other specific structures of the substrate 11 can be explained with reference to the previous embodiment and will not be repeated here.

[0063] In some embodiments, the step of providing the substrate 11 includes: providing an intermediate structure 20; the intermediate structure 20 includes the substrate 12, a gate intermediate structure 21 formed on the surface of the channel region 124, and at least one gate spacer 22 formed on the surface of the substrate 12; wherein the gate intermediate structure 21 includes a gate material 211 and a gate oxide layer 212; removing the at least one gate spacer 22; forming a dielectric layer 23 on the intermediate structure 20; and etching the dielectric layer 23 to form the substrate 11. The remaining portion of the dielectric layer 23 after etching and the gate intermediate structure 21 form the gate structure 13 in the substrate 11.

[0064] refer to Figure 3 In some embodiments, the intermediate structure 20 can be obtained through a MOS front-end process. As an example, the front-end process may specifically include AA (Active Area), STI (Shallow Trench Isolation), NW (N-well), PW (P-well), GOX (Gate Oxide), Poly (Polysilicon), Spacer (gate sidewall), LDD, Pocket (pocket area), S / D (Source and Drain), etc.

[0065] Optionally, the width of the gate material 211 may be 55 nm.

[0066] In some embodiments, the at least one gate spacer 22 may comprise two layers. Specifically, each gate spacer 22 may be composed of a layer of silicon dioxide and a layer of silicon nitride. The at least one gate spacer 22 is spaced away from the outer edge of the gate material 211 and may be aligned with the boundary between the lightly doped region 123 and the source / drain doped region 28. Optionally, the total thickness of the at least one gate spacer 22 is 30 nm.

[0067] In some embodiments, Figure 3 The structure shown in FIG. 1 can be obtained by removing the gate sidewall 22 entirely based on an etching process. Figure 4 The structure shown.

[0068] refer to Figure 5 In some embodiments, Figure 4 The structure shown may be subjected to oxide deposition and planarization based on a CMP process, followed by 600Å TEOS deposition to form a dielectric layer 23 on the intermediate structure 20. Optionally, the thickness of the dielectric layer 23 remains at 2100Å.

[0069] In some embodiments, the step of etching the dielectric layer 23 to form the substrate 11 may include: stacking a hard mask layer 24, at least one anti-reflective coating layer 25, and a photoresist layer 26 on the dielectric layer 23; exposing and developing the photoresist layer 26 corresponding to the position of the source and drain doping regions 28; forming an opening 27 aligned with the etching position in the photoresist layer 26 after development; wherein the width of the opening 27 is greater than the width of the source and drain doping regions 28; etching the dielectric layer 23 using the opening 27 as a position reference; and removing the at least one anti-reflective coating layer 25 and the hard mask layer 24 to obtain the substrate 11.

[0070] Specifically, refer to Figure 6 As an example, we can Figure 5 The structure shown in the figure sequentially deposits: a 1900Å thick amorphous carbon (Amorphous Carbon) as a hard mask layer 24, a 320Å thick silicon oxynitride 251 (SiON), a 50Å thick silicon dioxide 252 (OX), and a 200Å thick bottom anti-reflective coating 253 (BARC) as an anti-reflective coating 25, and then a 1000Å thick photoresist layer 26 is applied on top. This reduces light reflections and standing wave effects during the photolithography process, minimizing photolithography errors, improving photolithography accuracy, and enhancing the accuracy of pattern transfer during etching.

[0071] Then, the photoresist layer 26 is exposed and developed to form a Figure 6 In the structure shown, after developing the photoresist layer 26, an opening 27 is formed corresponding to the location of the source and drain doped regions 28. The opening 27 can be used to define the size of the contact structure 14. To increase the size of the contact structure 14, the width of the opening 27 needs to be larger than the width of the source and drain doped regions 28. Specifically, for example, the width of the opening 27 can be 90 nm, but can also be 80 nm, 100 nm, etc., and can be flexibly set according to actual needs.

[0072] Finally, after multiple etching processes, we can get Figure 7 The substrate 11 is shown. After at least one anti-reflective coating layer 25 and the hard mask layer 24 are removed, the remaining portion of the dielectric layer 23 after etching and the gate intermediate structure 21 together form the gate structure 13 in the substrate 11.

[0073] It should be noted that, in some possible implementations, the substrate 11 may be obtained by other etching processes or by directly etching the dielectric layer 23 formed on the intermediate structure 20. This specification does not impose any specific limitation on this.

[0074] S120 : forming isolation spacers 29 on both sides of the gate structure 13 ; the isolation spacers 29 are located on the lightly doped region 123 .

[0075] refer to Figure 8 In this embodiment, it is possible to Figure 7 In the structure shown, a certain thickness of SiN, which may be 15 nm, is deposited on the side of the dielectric layer 23 corresponding to the surface of the lightly doped region to form the isolation sidewall 29. The isolation sidewall 29 can be used as an isolation layer when forming the contact structure 14. It should be noted that the material used to form the isolation sidewall 29 is not limited to SiN, and can also be other materials used for interlayer isolation. For example, in some possible embodiments, materials such as silicon oxynitride or silicon carbide can also be used to form the isolation sidewall 29. This specification does not specifically limit this.

[0076] S130 : forming a contact structure 14 on a side surface of the isolation spacer 29 , the contact structure 14 being in contact with the source / drain doped region 28 .

[0077] refer to Figures 8-10 In some embodiments, the step of forming a contact structure 14 on the side of the isolation spacer 29 that contacts the source / drain doped region 28 may include: forming a polysilicon sidewall on the side of the isolation spacer 29; the polysilicon sidewall is located on the edge of the source / drain doped region 28 close to the lightly doped region 123; forming a metal silicide on the surface of the polysilicon sidewall and the source / drain doped region 28 to form a contact connection portion 17; wherein the contact connection portion 17 includes a connection sidewall 172 formed by the polysilicon sidewall and a bottom connection layer 171 formed by the substrate 12 located in the source / drain region 122; the bottom connection layer 171 and the connection sidewall 172 form a contact window 18; and filling the contact window 18 with a metal contact portion 16 to form the contact structure 14.

[0078] Specifically, after forming the isolation sidewall 29, a certain thickness of polysilicon can be deposited on the side of the isolation sidewall 29 away from the gate material 211 to form a polysilicon sidewall 31. The thickness can be 10nm. Then, the excess SiN and polysilicon in the active area are removed by self-alignment technology to obtain the following: Figure 8 It should be noted that the polysilicon sidewalls provided here are used to make the connecting sidewalls 172 in the contact structure 14, so in some possible implementations, the polysilicon sidewalls 31 may not be provided.

[0079] Next, the source and drain doping regions 28 are used for alignment, and metal silicide is formed on the surface of the polysilicon sidewalls 31 and the source and drain doping regions 28. Specifically, as an example, a pre-cleaning can be performed to remove the natural oxide layer on the surface, and 120Å NiPt alloy and 50Å TiN are deposited in sequence. Then, a first RTP (Rapid Thermal Processing) is performed to form a high-resistance metal silicide Ni2PtSi (temperature is 290 degrees, duration is 30 seconds), and then a second RTP is performed to form a low-resistance NiPtSi2. Finally, the unreacted Ni in the area where NiPtSi2 is not formed is removed to obtain the following. Figure 9 It should be noted that, in Figure 9 In the structure shown, since metal silicide is formed in a portion of the source / drain doping region 28 close to the surface, the remaining region of the source / drain doping region 28 forms the source / drain region 122 .

[0080] Then, a metal contact portion 16 is formed in the contact window 18 formed by the metal silicide. Specifically, as an example, a layer of titanium (Ti) with a thickness of 100Å and a layer of titanium nitride (TiN) with a thickness of 50Å are deposited by physical vapor deposition (PVD), and then a layer of tungsten (W) is deposited by chemical vapor deposition (CVD) and planarized by chemical mechanical polishing (CMP), to obtain the following: Figure 10 In this way, the metal contact portion 16 is entirely wrapped by the metal silicide, thereby reducing the RC delay.

[0081] S140 : removing the isolation spacer 29 to form an air gap 15 between the gate structure 13 and the contact structure 14 and located on the lightly doped region 123 .

[0082] Specifically, the isolation sidewall 29 can be removed based on an etching process, such as dry etching, wet etching, etc., to obtain Figure 11 The structure shown.

[0083] In some embodiments, the step of removing the isolation spacer 29 includes: removing the isolation spacer 29 based on an etching process; wherein the isolation spacer 29 has a high etching selectivity with respect to both the gate structure 13 and the contact structure 14 .

[0084] Specifically, to avoid damaging the gate structure 13 and contact structure 14 on either side of the isolation spacer 29 during etching, such as etching away a portion of the connecting sidewall 172 adjacent to the isolation spacer 29 and thereby damaging the contact structure 14, the material of the isolation spacer 29 and the specific etching process can be selected to ensure that the isolation spacer 29 has a high etching selectivity relative to both the gate structure 13 and the contact structure 14, so that only the isolation spacer 29 is etched during the etching process. For example, the isolation spacer 29 can be made of silicon nitride, and accordingly, wet etching can be used using phosphoric acid as the etchant to remove the isolation spacer 29. For another example, the isolation spacer 29 can be made of amorphous carbon, and accordingly, based on the Asher process, the isolation spacer 29 can be oxidized into gas using oxygen or ozone under certain temperature conditions (170°C to 330°C) and then removed. Of course, the material of the isolation sidewall 29 and the specific etching process can also be flexibly selected according to the material of the gate structure 13 and the contact structure 14. This specification does not make specific restrictions on this. It is sufficient to enable the isolation sidewall 29 to achieve a high etching selectivity relative to the gate structure 13 and the contact structure 14.

[0085] In some embodiments, the etching ratio of the isolation spacer 29 to the gate structure 13 and the contact structure 14 can be greater than 10:1. For example, the etching ratio can be 100:1. Of course, in some embodiments, the etching ratio can also be 1:0 to prevent the gate structure 13 and the contact structure 14 from being damaged by etching.

[0086] In this embodiment, since the gate sidewall spacers are removed at the beginning of the provided process flow, the subsequent process difficulty of fabricating the contact structure can be reduced, for example, by reducing the difficulty of the patterning and etching processes. Furthermore, the process flow provided in this embodiment can avoid the problem of short circuits between the contact structure and the gate caused by self-alignment errors, thereby reducing the difficulty of the self-alignment process.

[0087] In some embodiments, the method for preparing the semiconductor structure may further include: supplementally injecting ions into the lightly doped region 123 through the air gap 15 .

[0088] An unexpected effect is that after an air gap 15 is set between the contact structure 14 and the gate structure 13 and located on the lightly doped region 123, ions can be replenished into the lightly doped region 123 through the air gap 15 to compensate for the loss of ions in the lightly doped region 123 during the preparation process, thereby avoiding to a certain extent the high resistance in the channel direction caused by the loss of ions in the lightly doped region 123 and reducing the impact on device performance.

[0089] In some embodiments, the method for preparing the semiconductor structure may further include: performing a sealing process on the air gap 15 on the surfaces of the gate structure 13 and the contact structure 14 facing away from the substrate 12 .

[0090] Specifically, as an example, after the lightly doped region 123 is supplementally implanted with ions, SiCN may be deposited on the surface of the gate structure 13 and the contact structure 14 facing away from the substrate 12 to seal the air gap 15. Since the width of the air gap 15 is small, as shown in FIG. Figure 11 The thickness of the SiCN is only 15nm, so the rapid sealing technology of PVD can be used to generate SiCN to form Figure 12 The structure shown.

[0091] One embodiment of the present disclosure provides a pull-up transistor, comprising the semiconductor structure described in any one of the aforementioned embodiments.

[0092] In this embodiment, the pull-up transistor is used to provide the current required to pull the output node to a high level, ensuring that the output node can drive subsequent circuits or loads. Specifically, for example, the pull-up transistor can be composed of a PMOS transistor. In a CMOS logic circuit, the pull-up transistor can form a pull-up network and work in a complementary manner with the pull-down network (composed of an NMOS transistor).

[0093] It should be understood that the specific examples herein are only intended to help those skilled in the art better understand the embodiments of this specification, rather than to limit the scope of the present invention.

[0094] It can be understood that in the various implementations of this specification, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the implementation methods of this specification.

[0095] It can be understood that the various embodiments described in this specification can be implemented individually or in combination, and the embodiments in this specification are not limited to this.

[0096] Unless otherwise indicated, all technical and scientific terms used in the embodiments of this specification have the same meaning as those commonly understood by those skilled in the art in the technical field of this specification. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the scope of this specification. The term "and / or" used in this specification includes any and all combinations of one or more related listed items. The singular forms "a", "above", and "the" used in the embodiments of this specification and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0097] The above description is merely a specific embodiment of this specification, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this specification should be included in the scope of protection of this specification. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; The base comprises a substrate and a gate structure; the substrate is formed with a well region, a source-drain region and a lightly doped region; wherein the well region comprises a channel region; the gate structure is arranged on the surface of the channel region; the lightly doped region is located between the source-drain region and the channel region; A contact structure; the contact structure is arranged on the surface of the source and drain regions; Wherein, an air gap located on the lightly doped region is formed between the contact structure and the gate structure.

2. The semiconductor structure according to claim 1, characterized in that: The width of the air gap is consistent with the width of the lightly doped region.

3. The semiconductor structure according to claim 1, characterized in that The contact structure includes a metal contact portion and a contact connection portion; the contact connection portion includes a bottom connection layer formed on the surface of the source and drain region, and a connection side wall located at the two side edges of the bottom connection layer; wherein the bottom connection layer and the connection side wall form a contact window; the metal contact portion is formed in the contact window.

4. The semiconductor structure according to claim 3, characterized in that: The material of the contact connection portion is metal silicide.

5. A method for preparing a semiconductor structure, characterized in that: The method for preparing the semiconductor structure comprises: A substrate is provided; the substrate comprises a substrate and a gate structure; the substrate is formed with a well region, a source-drain doped region and a lightly doped region; wherein the well region comprises a channel region; the gate structure is arranged on a surface of the channel region; the lightly doped region is located between the source-drain doped region and the channel region; Isolation sidewalls are formed on both sides of the gate structure; the isolation sidewalls are located on the lightly doped region; forming a contact structure contacting the source-drain doped region on a side surface of the isolation sidewall; The isolation spacer is removed to form an air gap located on the lightly doped region between the gate structure and the contact structure.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: The step of removing the isolation sidewall includes: The isolation spacer is removed based on an etching process; wherein the isolation spacer has a high etching selectivity ratio relative to both the gate structure and the contact structure.

7. The method for preparing a semiconductor structure according to claim 5, characterized in that: The step of forming a contact structure on the side of the isolation spacer that contacts the source and drain doped regions includes: A polysilicon sidewall is formed on the side of the isolation sidewall; the polysilicon sidewall is located on the edge of the source and drain doping region close to the lightly doped region; Metal silicide is fabricated on the surface of the polysilicon sidewalls and the source-drain doped regions to form a contact connection portion; wherein the contact connection portion comprises a connection sidewall formed by the polysilicon sidewalls and a bottom connection layer formed by the substrate located in the source-drain region; the bottom connection layer and the connection sidewall form a contact window; A metal contact portion is filled in the contact window to form the contact structure.

8. The method for preparing a semiconductor structure according to claim 5, characterized in that: The method for preparing the semiconductor structure further comprises: Ions are additionally implanted into the lightly doped region through the air gap.

9. The method for preparing a semiconductor structure according to claim 5, characterized in that: The step of providing a substrate comprises: Providing an intermediate structure; the intermediate structure comprises the substrate, a gate intermediate structure formed on the surface of the channel region, and at least one layer of gate sidewall formed on the surface of the substrate; wherein the gate intermediate structure comprises a gate material and a gate oxide layer; Removing the at least one layer of gate sidewall; forming a dielectric layer on the intermediate structure; The dielectric layer is etched to form the substrate.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: The step of etching the dielectric layer to form the substrate comprises: A hard mask layer, at least one anti-reflective coating layer, and a photoresist layer are stacked on the dielectric layer; Corresponding to the position of the source and drain doped regions, the photoresist layer is exposed and developed; after the development, the photoresist layer forms an opening aligned with the etching position; wherein the width of the opening is greater than the width of the source and drain doped regions; Using the opening as a position reference, etching the dielectric layer; The at least one anti-reflective coating layer and the hard mask layer are removed to obtain the substrate.

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