Undervoltage protection circuit and gate drive circuit

Abstract

The invention relates to the field of gate driver design, in particular to an under-voltage protection circuit and a gate drive circuit. The under-voltage protection circuit comprises an inverter, a resistor, a capacitor, a diode and a field effect transistor, the under-voltage protection circuit is arranged at the output stage of the gate drive circuit, and when the power supply voltage is abnormal, the under-voltage protection circuit enables the output of the gate drive circuit to be low; when the output stage of the gate drive circuit is in an unbiased or under-voltage condition, the P-type field effect transistor MP1 is turned off through the high-resistance resistor R1, and the gate of the N-type field effect transistor MN1 is connected with the output through the clamping circuit.

Description

Technical Field

[0001] The present invention relates to the field of gate driver design, and in particular to an undervoltage protection circuit and a gate driver circuit. Background Art

[0002] Undervoltage of the gate driver refers to the situation where the power supply voltage is lower than the normal value when encountering external environmental interference. In this case, the voltage reduction causes power drop, affects the normal operation of the circuit, and shortens the life of the gate driver. Therefore, it is necessary to equip the gate driver with an undervoltage protection circuit to ensure the normal operation of the circuit during undervoltage.

[0003] Currently, an undervoltage lockout module is usually configured before the logic circuit module of the gate driver. When undervoltage occurs, the driver is turned off by the logic circuit module. However, this method cannot set the output low and turn off the gate driver in time, thereby causing damage to the gate driver. Summary of the invention

[0004] To solve the above problems, in the case of undervoltage of the gate driver, the present invention provides an undervoltage protection circuit and a gate drive circuit that can quickly respond to the undervoltage signal of the previous stage, timely lower the output and shut down the driver.

[0005] In a first aspect, an undervoltage protection circuit includes an inverter, a resistor, a capacitor, a diode and a field effect transistor, wherein:

[0006] The first input terminal voltage VINP is connected to the input terminal of the inverter INV1, and the second input terminal voltage VINN is connected to the gate of the N-type field effect transistor MN1; the output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2; the output terminal of the inverter INV2 is connected to the gate of the P-type field effect transistor MP1;

[0007] The gate of the P-type field effect transistor MP1 is also connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the power supply VDD; the drain of the P-type field effect transistor MP1 is connected to the output end; the source of the P-type field effect transistor MP1 is connected to the power supply VDD; the drain of the N-type field effect transistor MN1 is connected to the output end, and the source of the N-type field effect transistor MN1 is grounded;

[0008] The gate of the P-type field effect transistor MP2 and the gate of the P-type field effect transistor MP3 are both connected to the drain of the N-type field effect transistor MN2; the drain of the P-type field effect transistor MP2 is connected to the gate of the N-type field effect transistor MN1, and the drain of the P-type field effect transistor MP3 is connected to the output end; the source of the P-type field effect transistor MP2 and the source of the P-type field effect transistor MP3 are both connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the drain of the N-type field effect transistor MN2; the gate of the N-type field effect transistor MN2 is connected to the gate of the N-type field effect transistor MN3, the drain of the N-type field effect transistor MN3, and the drain of the N-type field effect transistor MN4; the source of the N-type field effect transistor MN2, the source of the N-type field effect transistor MN3, and the source of the N-type field effect transistor MN4 are all grounded; one end of the resistor R2 is connected to the power supply VDD, and the other end of the resistor R2 is connected to the drain of the N-type field effect transistor MN3;

[0009] The drain of the N-type field effect transistor MN5 and the gate of the N-type field effect transistor MN6 are both connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the output end; the source of the N-type field effect transistor MN5 and the source of the N-type field effect transistor MN6 are both grounded; the drain of the N-type field effect transistor MN6 is connected to the output end;

[0010] One end of the resistor R6 is connected to the drain of the N-type field effect transistor MN7, the gate of the N-type field effect transistor MN8, and the output end of the diode D1; the other end of the resistor R6 is connected to one end of the resistor R5 and one end of the capacitor C1; the other end of the capacitor C1 and the input end of the diode D1 are both grounded; the other end of the resistor R5 is connected to the power supply VDD; the source of the N-type field effect transistor MN7 is grounded; the drain of the N-type field effect transistor MN8 is connected to the power supply VDD; the source of the N-type field effect transistor MN8 is connected to the drain of the N-type field effect transistor MN9, the gate of the N-type field effect transistor MN10, the gate of the N-type field effect transistor MN11, and one end of the resistor R7; the other end of the resistor R7, the source of the N-type field effect transistor MN9, the source of the N-type field effect transistor MN10, and the source of the N-type field effect transistor MN11 are all grounded; the drain of the N-type field effect transistor MN10 is connected to the output end;

[0011] The first enable input terminal ENP is connected to the input terminal of the inverter INV3 and the input terminal of the inverter INV6, the output terminal of the inverter INV3 is connected to the input terminal of the inverter INV4, the output terminal of the inverter INV4 is connected to the input terminal of the inverter INV5, and the output terminal of the inverter INV5 is connected to the gate of the N-type field effect transistor MN5; the output terminal of the inverter INV6 is connected to the input terminal of the inverter INV7, the output terminal of the inverter INV7 is connected to the input terminal of the inverter INV8, and the output terminal of the inverter INV8 is connected to the gate of the N-type field effect transistor MN7 and the gate of the N-type field effect transistor MN9;

[0012] The second enable input terminal ENN is connected to the input terminal of the inverter INV9 , the output terminal of the inverter INV9 is connected to the input terminal of the inverter INV10 , and the output terminal of the inverter INV10 is connected to the gate of the N-type field effect transistor MN4 .

[0013] In a second aspect, the present invention provides a gate drive circuit, comprising an undervoltage protection circuit as described in the first aspect, and further comprising a voltage generator, a level shifter, an inverter INV11, a low-side control circuit, and an instantaneous pull-up enhancement circuit; wherein the output end of the inverter INV11 is connected to the input end of the inverter INV1 in the undervoltage protection circuit, and the inverter INV1, the inverter INV2 and the inverter INV11 together form a high-side inverter chain, and at the same time:

[0014] A level shifter for converting an input signal VIN into a high-side square wave signal;

[0015] A voltage generator, used for generating a signal VSSH, providing a floating ground for the high-side inverter chain;

[0016] The input end of the inverter INV11 is connected to the output of the level shifter, and is used to convert the high-side square wave signal into a high-side control signal (ie, the first input terminal voltage VINP);

[0017] A low-side control circuit, used for converting an input signal VIN into a low-side control signal (i.e., a second input terminal voltage VINN);

[0018] The instantaneous pull-up enhancement circuit and the undervoltage protection circuit are both used to protect the gate drive circuit; the instantaneous pull-up enhancement circuit and the undervoltage protection circuit are connected, indicating that the two cannot work at the same time.

[0019] Further, the first input terminal voltage VINP is connected to the instantaneous pull-up enhancement circuit, and the drain of the N-type field effect transistor MN6 and the drain of the N-type field effect transistor MN11 of the undervoltage protection circuit are also connected to the instantaneous pull-up enhancement circuit.

[0020] Further, the low-side control circuit includes a low-side inverter chain and a dead time adjustment circuit, wherein:

[0021] A low-side inverter chain for converting an input signal VIN into a low-side control signal;

[0022] The dead time adjustment circuit is used to make the rising edge of the low-side control signal arrive quickly, thereby reducing the dead time.

[0023] Furthermore, the low-side inverter chain includes: an input signal VIN is connected to the input end of the inverter INV12, the output end of the inverter INV12 is connected to the input end of the inverter INV13, the output end of the inverter INV13 is connected to the input end of the inverter INV14, and the output end of the inverter INV14 is connected to the dead time adjustment circuit; the output end of the inverter INV13 is also connected to the dead time adjustment circuit.

[0024] Furthermore, the dead time adjustment circuit includes:

[0025] The output end of the inverter INV14 is connected to an input end of the NAND gate G1; the output end of the inverter INV13 is connected to an input end of the NAND gate G2;

[0026] The output end of the NAND gate G1 is connected to the input end of the inverter INV15, the output end of the inverter INV15 is connected to the input end of the inverter INV16, and the output end of the inverter INV16 is connected to one input end of the NAND gate G3;

[0027] The input signal VIN is connected to the other input terminal of the NAND gate G3, the output terminal of the NAND gate G3 is connected to the input terminal of the inverter INV17, the output terminal of the inverter INV17 is connected to the input terminal of the inverter INV18, the output terminal of the inverter INV18 is connected to the input terminal of the inverter INV19, the output terminal of the inverter INV19 is connected to the other input terminal of the NAND gate G2, the output terminal of the NAND gate G2 is connected to the input terminal of the inverter INV20, and the output terminal of the inverter INV20 provides a second input terminal voltage VINN.

[0028] Beneficial effects of the present invention:

[0029] The present invention designs an undervoltage protection circuit, which is set at the output stage of the gate drive circuit. When the power supply voltage is abnormal, the undervoltage protection circuit sets the output of the gate drive circuit to a low level; when the output stage of the gate drive circuit is unbiased or undervoltage, the P-type field effect transistor MP1 is turned off through the high-resistance resistor R1, and the gate of the N-type field effect transistor MN1 is connected to the output through the clamping circuit. In this configuration, there is no available bias power supply, and the output is clamped to the threshold voltage of the N-type field effect transistor MN1. It plays the role of protecting the circuit and enhancing stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a structural diagram of the gate drive circuit of the present invention;

[0031] Figure 2 It is a schematic diagram of the structure of the undervoltage protection circuit of the present invention;

[0032] Figure 3 This is a simulation waveform diagram of the normal operation of the gate drive circuit according to the embodiment of the present invention;

[0033] Figure 4 This is a simulation waveform diagram of the power supply voltage undervoltage to 5V in an embodiment of the present invention;

[0034] Figure 5 This is a simulation waveform diagram of the power supply voltage being under-voltage to 3V according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] The present invention provides an undervoltage protection circuit such as Figure 2 As shown, it includes an inverter, a resistor, a capacitor, a diode and a field effect transistor, among which:

[0037] The first input terminal voltage VINP is connected to the input terminal of the inverter INV1, and the second input terminal voltage VINN is connected to the gate of the N-type field effect transistor MN1; the output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2; the output terminal of the inverter INV2 is connected to the gate of the P-type field effect transistor MP1;

[0038] The gate of the P-type field effect transistor MP1 is also connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the power supply VDD; the drain of the P-type field effect transistor MP1 is connected to the output end; the source of the P-type field effect transistor MP1 is connected to the power supply VDD; the drain of the N-type field effect transistor MN1 is connected to the output end, and the source of the N-type field effect transistor MN1 is grounded;

[0039] The gate of the P-type field effect transistor MP2 and the gate of the P-type field effect transistor MP3 are both connected to the drain of the N-type field effect transistor MN2; the drain of the P-type field effect transistor MP2 is connected to the gate of the N-type field effect transistor MN1, and the drain of the P-type field effect transistor MP3 is connected to the output end; the source of the P-type field effect transistor MP2 and the source of the P-type field effect transistor MP3 are both connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the drain of the N-type field effect transistor MN2; the gate of the N-type field effect transistor MN2 is connected to the gate of the N-type field effect transistor MN3, the drain of the N-type field effect transistor MN3, and the drain of the N-type field effect transistor MN4; the source of the N-type field effect transistor MN2, the source of the N-type field effect transistor MN3, and the source of the N-type field effect transistor MN4 are all grounded; one end of the resistor R2 is connected to the power supply VDD, and the other end of the resistor R2 is connected to the drain of the N-type field effect transistor MN3;

[0040] The drain of the N-type field effect transistor MN5 and the gate of the N-type field effect transistor MN6 are both connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the output end; the source of the N-type field effect transistor MN5 and the source of the N-type field effect transistor MN6 are both grounded; the drain of the N-type field effect transistor MN6 is connected to the output end;

[0041] One end of the resistor R6 is connected to the drain of the N-type field effect transistor MN7, the gate of the N-type field effect transistor MN8, and the output end of the diode D1; the other end of the resistor R6 is connected to one end of the resistor R5 and one end of the capacitor C1; the other end of the capacitor C1 and the input end of the diode D1 are both grounded; the other end of the resistor R5 is connected to the power supply VDD; the source of the N-type field effect transistor MN7 is grounded; the drain of the N-type field effect transistor MN8 is connected to the power supply VDD; the source of the N-type field effect transistor MN8 is connected to the drain of the N-type field effect transistor MN9, the gate of the N-type field effect transistor MN10, the gate of the N-type field effect transistor MN11, and one end of the resistor R7; the other end of the resistor R7, the source of the N-type field effect transistor MN9, the source of the N-type field effect transistor MN10, and the source of the N-type field effect transistor MN11 are all grounded; the drain of the N-type field effect transistor MN10 is connected to the output end;

[0042] The first enable input terminal is connected to the input terminal of the inverter INV3 and the input terminal of the inverter INV6, the output terminal of the inverter INV3 is connected to the input terminal of the inverter INV4, the output terminal of the inverter INV4 is connected to the input terminal of the inverter INV5, and the output terminal of the inverter INV5 is connected to the gate of the N-type field effect transistor MN5; the output terminal of the inverter INV6 is connected to the input terminal of the inverter INV7, the output terminal of the inverter INV7 is connected to the input terminal of the inverter INV8, and the output terminal of the inverter INV8 is connected to the gate of the N-type field effect transistor MN7 and the gate of the N-type field effect transistor MN9;

[0043] The second enable input terminal is connected to the input terminal of the inverter INV9, the output terminal of the inverter INV9 is connected to the input terminal of the inverter INV10, and the output terminal of the inverter INV10 is connected to the gate of the N-type field effect transistor MN4.

[0044] Specifically, the undervoltage protection circuit is further divided into two parts, wherein the inverter INV1, the inverter INV2, the resistor R1, the P-type field effect transistor MP1, and the N-type field effect transistor MN1 constitute a first undervoltage protection circuit, and the remaining devices constitute a second undervoltage protection circuit.

[0045] The present invention provides a gate drive circuit, which adopts an undervoltage protection circuit. The overall structure of the gate drive circuit is as follows: Figure 1As shown, it also includes a voltage generator, a level shifter, an inverter INV11, a low-side control circuit, and an instantaneous pull-up enhancement circuit; wherein the output end of the inverter INV11 is connected to the input end of the inverter INV1 in the undervoltage protection circuit, and the inverter INV1, the inverter INV2 and the inverter INV11 together form a high-side inverter chain.

[0046] Specifically, the first input terminal voltage VINP is connected to the instantaneous pull-up enhancement circuit, and the drain of the N-type field effect transistor MN6 and the drain of the N-type field effect transistor MN11 in the undervoltage protection circuit are also connected to the instantaneous pull-up enhancement circuit.

[0047] Specifically, the low-side control circuit includes a low-side inverter chain and a dead time adjustment circuit.

[0048] Specifically, the low-side inverter chain includes:

[0049] The input signal VIN is connected to the input end of the inverter INV12, the output end of the inverter INV12 is connected to the input end of the inverter INV13, the output end of the inverter INV13 is connected to the input end of the inverter INV14, the output end of the inverter INV14 is connected to the dead time adjustment circuit; the output end of the inverter INV13 is also connected to the dead time adjustment circuit.

[0050] Specifically, the dead time adjustment circuit includes:

[0051] The output end of the inverter INV14 is connected to an input end of the NAND gate G1; the output end of the inverter INV13 is connected to an input end of the NAND gate G2;

[0052] The output end of the NAND gate G1 is connected to the input end of the inverter INV15, the output end of the inverter INV15 is connected to the input end of the inverter INV16, and the output end of the inverter INV16 is connected to one input end of the NAND gate G3;

[0053] The input signal VIN is connected to the other input terminal of the NAND gate G3, the output terminal of the NAND gate G3 is connected to the input terminal of the inverter INV17, the output terminal of the inverter INV17 is connected to the input terminal of the inverter INV18, the output terminal of the inverter INV18 is connected to the input terminal of the inverter INV19, the output terminal of the inverter INV19 is connected to the other input terminal of the NAND gate G2, the output terminal of the NAND gate G2 is connected to the input terminal of the inverter INV20, and the output terminal of the inverter INV20 provides a second input terminal voltage VINN.

[0054] Specifically, Figure 1As shown, the M-type field effect transistor MP1 and the N-type field effect transistor MN1 in the undervoltage protection circuit form a push-pull structure. The input signal VIN flowing in from the input end is converted into a high-side square wave signal through a level shifter. At the same time, the input signal VIN generates a pulse signal through a NAND gate in the low-side control circuit, so that the rising edge of the low-side control signal (i.e., the second input terminal voltage VINN) arrives quickly, thereby reducing the dead time. The voltage generator generates a signal VSSH to provide a floating ground for the high-side inverter chain. The instantaneous pull-up enhancement circuit is connected to the undervoltage protection circuit, indicating that the two cannot work at the same time.

[0055] Preferably, when the output stage is undervoltage and unbiased, the output is pulled down, and the undervoltage protection circuit can protect the gate drive circuit from being burned; the enable signal ENP of the first enable input terminal and the enable signal ENN of the second enable input terminal provide gate signals X1_N, X2_N, and X3_N through the inverter chain, and the gate signal X3_N is input to the gate of the N-type field effect transistor MN4; the gate signal X1_N is input to the gate of the N-type field effect transistor MN5; the gate signal X2_N is input to the gate of the N-type field effect transistor MN7 and the gate signal X3_N is input to the gate of the N-type field effect transistor MN8. The gate of N-type field effect transistor MN9 is controlled by gate signal X1_N, gate of N-type field effect transistor MN4 is controlled by X2_N, gate of N-type field effect transistor MN7 is controlled by X3_N, and gates of N-type field effect transistors MN7 and MN9 are controlled by gate signal X1_N. In the case of undervoltage and no bias at the output stage, the output is set low through the active clamping circuit to limit the rise of the output. At this time, MP1 is turned off through a resistor, and the gate of MN1 is connected to the output through a clamping resistor. In this configuration, there is no bias power supply available, and the output is clamped to the threshold voltage of MN1.

[0056] Specifically, the undervoltage protection circuit is controlled by an undervoltage detection signal, wherein the enable signal ENP of the first enable input terminal and the enable signal ENN of the second enable input terminal are provided by an external undervoltage detection module and a power supply voltage divider, respectively. When the gate drive circuit is operating normally, the undervoltage detection module outputs a high level, the externally provided enable signal ENP is a low level, and the enable signal ENN is a high level. At this time, the enable signal of the undervoltage protection circuit is a high level, that is, the gate signals of MN4, MN5, MN7 and MN9 are all high levels, so the gate signals of MN2, MN6, MN8 and MN10 in the undervoltage protection circuit are pulled down, thereby controlling the overall undervoltage protection circuit to shut down, and the undervoltage protection circuit does not work. When one of the power supply voltage VDD and the voltage generated by LDO is undervoltage, the undervoltage detection module outputs a low level, and the undervoltage protection circuit starts to work.

[0057] The gate of the power tube MN1 is connected to the output through the clamp circuit, and the undervoltage protection circuit works when the gate signal of the N-type field effect tube MN4 is at a low level. The resistor R2 and the N-type field effect tube MN3 branch provide a DC voltage through the power supply voltage VDD, and the generated current is copied to the N-type field effect tube MN2 through the current mirror. The copied current flows through the resistor R3 to generate a voltage drop. One end of the resistor R3 is connected to the source of the P-type field effect transistor MP2 and the source of the P-type field effect transistor MP3 at the same time, and the other end of the resistor R3 is connected to the gate of the P-type field effect transistor MP2 and the gate of the P-type field effect transistor MP3 at the same time. The P-type field effect transistor MP2 and the P-type field effect transistor MP3 are two identical transistors, so the drain voltages of the P-type field effect transistor MP2 and the P-type field effect transistor MP3 are also equal, and the drains of the P-type field effect transistor MP2 and the P-type field effect transistor MP3 are respectively connected to the gate and output end of the N-type field effect transistor MN1, that is, the output end is clamped to be consistent with the gate signal of the N-type field effect transistor MN1 when the circuit is undervoltage, at this time, the low-side inverter chain source voltage is undervoltage, and the output end VOUT is pulled down to the MN1 threshold voltage. And the P-type field effect transistor MP1 is also turned off through the resistor R1.

[0058] Secondly, when power-on and power-off are abnormal, the low-side inverter chain source voltage is abnormal, and the gate of the N-type field effect transistor MN1 is in a suspended state. At this time, the gate signal of the N-type field effect transistor MN4 is 0, and the N-type field effect transistor MN1 is turned off. In addition, the gate voltage of the N-type field effect transistor MN10 is obtained by dividing the power supply voltage VDD. When the voltage is undervoltage, the gate signal of the N-type field effect transistor MN10 is low, but still higher than the threshold voltage of the N-type field effect transistor MN10. Therefore, as long as the N-type field effect transistor MN10 is turned on, the output will be pulled down, that is, the threshold voltage output to the N-type field effect transistor MN6 will be lowered when the voltage is undervoltage. At the same time, the gate signals of the N-type field effect transistor MN10 and the N-type field effect transistor MN11 are consistent. When the voltage is undervoltage, the N-type field effect transistor MN11 is also turned on, thereby pulling down the gate of the pull-up transistor in the instantaneous pull-up enhancement circuit to turn it off. That is, when the voltage is undervoltage, the instantaneous pull-up enhancement circuit will not work, and the two will not take effect at the same time.

[0059] In one embodiment, the gate drive circuit is simulated in a transient state with a frequency of 5 MHz and a load capacitance C load The simulation is carried out under the conditions of 1.8nF and 50% duty cycle, inputting a square wave of 0 to 5V and outputting a square wave of 0 to VDD. The simulation of the undervoltage protection circuit is as follows.

[0060] When there is no undervoltage, UVLO outputs a high level, that is, the enable signal ENP input to the gate drive circuit is a low level, and the enable signal ENN is a high level, with a typical value of 5V. The output is a 0-12V square wave. Figure 3 shown.

[0061] After undervoltage occurs, VDD is set to 5V, UVLO outputs low level, the enable signal ENN input to the gate drive circuit is high level, the enable signal ENP is high level, the typical value is 5V, and the output is low level. Figure 4 shown.

[0062] Continue to set VDD to 3V, UVLO outputs low level, the enable signal ENN input to the gate drive circuit is low level, the enable signal ENP is low level, and the output is low level. At this time, the low-side inverter chain source voltage is also undervoltage, that is, the inverter does not work. Figure 5 shown.

[0063] In the present invention, unless otherwise clearly stipulated and limited, the terms such as "installation", "setting", "connection", "fixation" and "rotation" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements. Unless otherwise clearly defined, ordinary technicians in this field can understand the specific meanings of the above terms in the present invention according to the specific circumstances.

[0064] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An undervoltage protection circuit, characterized in that: It includes inverters, resistors, capacitors, diodes and field effect transistors, among which: The first input terminal voltage VINP is connected to the input terminal of the inverter INV1, and the second input terminal voltage VINN is connected to the gate of the N-type field effect transistor MN1; the output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2; the output terminal of the inverter INV2 is connected to the gate of the P-type field effect transistor MP1; The gate of the P-type field effect transistor MP1 is also connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the power supply VDD; the drain of the P-type field effect transistor MP1 is connected to the output end; the source of the P-type field effect transistor MP1 is connected to the power supply VDD; the drain of the N-type field effect transistor MN1 is connected to the output end, and the source of the N-type field effect transistor MN1 is grounded; The gate of the P-type field effect transistor MP2 and the gate of the P-type field effect transistor MP3 are both connected to the drain of the N-type field effect transistor MN2; the drain of the P-type field effect transistor MP2 is connected to the gate of the N-type field effect transistor MN1, and the drain of the P-type field effect transistor MP3 is connected to the output end; the source of the P-type field effect transistor MP2 and the source of the P-type field effect transistor MP3 are both connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the drain of the N-type field effect transistor MN2; the gate of the N-type field effect transistor MN2 is connected to the gate of the N-type field effect transistor MN3, the drain of the N-type field effect transistor MN3, and the drain of the N-type field effect transistor MN4; the source of the N-type field effect transistor MN2, the source of the N-type field effect transistor MN3, and the source of the N-type field effect transistor MN4 are all grounded; one end of the resistor R2 is connected to the power supply VDD, and the other end of the resistor R2 is connected to the drain of the N-type field effect transistor MN3; The drain of the N-type field effect transistor MN5 and the gate of the N-type field effect transistor MN6 are both connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the output end; the source of the N-type field effect transistor MN5 and the source of the N-type field effect transistor MN6 are both grounded; the drain of the N-type field effect transistor MN6 is connected to the output end; One end of the resistor R6 is connected to the drain of the N-type field effect transistor MN7, the gate of the N-type field effect transistor MN8, and the output end of the diode D1; the other end of the resistor R6 is connected to one end of the resistor R5 and one end of the capacitor C1; the other end of the capacitor C1 and the input end of the diode D1 are both grounded; the other end of the resistor R5 is connected to the power supply VDD; the source of the N-type field effect transistor MN7 is grounded; the drain of the N-type field effect transistor MN8 is connected to the power supply VDD; the source of the N-type field effect transistor MN8 is connected to the drain of the N-type field effect transistor MN9, the gate of the N-type field effect transistor MN10, the gate of the N-type field effect transistor MN11, and one end of the resistor R7; the other end of the resistor R7, the source of the N-type field effect transistor MN9, the source of the N-type field effect transistor MN10, and the source of the N-type field effect transistor MN11 are all grounded; the drain of the N-type field effect transistor MN10 is connected to the output end; The first enable input terminal is connected to the input terminal of the inverter INV3 and the input terminal of the inverter INV6, the output terminal of the inverter INV3 is connected to the input terminal of the inverter INV4, the output terminal of the inverter INV4 is connected to the input terminal of the inverter INV5, and the output terminal of the inverter INV5 is connected to the gate of the N-type field effect transistor MN5; the output terminal of the inverter INV6 is connected to the input terminal of the inverter INV7, the output terminal of the inverter INV7 is connected to the input terminal of the inverter INV8, and the output terminal of the inverter INV8 is connected to the gate of the N-type field effect transistor MN7 and the gate of the N-type field effect transistor MN9; The second enable input terminal is connected to the input terminal of the inverter INV9, the output terminal of the inverter INV9 is connected to the input terminal of the inverter INV10, and the output terminal of the inverter INV10 is connected to the gate of the N-type field effect transistor MN4.

2. A gate drive circuit, characterized in that: The invention comprises an undervoltage protection circuit as claimed in claim 1, further comprising a voltage generator, a level shifter, an inverter INV11, a low-side control circuit, and an instantaneous pull-up enhancement circuit; wherein the output end of the inverter INV11 is connected to the input end of the inverter INV1 in the undervoltage protection circuit, and the inverter INV1, the inverter INV2 and the inverter INV11 together form a high-side inverter chain, and at the same time: A level shifter for converting an input signal VIN into a high-side square wave signal; A voltage generator, used for generating a signal VSSH, providing a floating ground for the high-side inverter chain; The input end of the inverter INV11 is connected to the output of the level shifter, and is used to convert the high-side square wave signal into a high-side control signal; A low-side control circuit, used for converting an input signal VIN into a low-side control signal; The instantaneous pull-up enhancement circuit and the undervoltage protection circuit are both used to protect the gate drive circuit; the instantaneous pull-up enhancement circuit and the undervoltage protection circuit are connected.

3. A gate drive circuit according to claim 2, characterized in that: The first input terminal voltage VINP is connected to the instantaneous pull-up enhancement circuit, and the drain of the N-type field effect transistor MN6 and the drain of the N-type field effect transistor MN11 of the undervoltage protection circuit are also connected to the instantaneous pull-up enhancement circuit.

4. The gate drive circuit according to claim 2, characterized in that: The low-side control circuit includes a low-side inverter chain and a dead-time adjustment circuit, where: A low-side inverter chain for converting an input signal VIN into a low-side control signal; The dead time adjustment circuit is used to make the rising edge of the low-side control signal arrive quickly, thereby reducing the dead time.

5. A gate drive circuit according to claim 4, characterized in that: The low-side inverter chain consists of: The input signal VIN is connected to the input end of the inverter INV12, the output end of the inverter INV12 is connected to the input end of the inverter INV13, the output end of the inverter INV13 is connected to the input end of the inverter INV14, the output end of the inverter INV14 is connected to the dead time adjustment circuit; the output end of the inverter INV13 is also connected to the dead time adjustment circuit.

6. The gate drive circuit according to claim 5, characterized in that: The dead time adjustment circuit includes: The output end of the inverter INV14 is connected to an input end of the NAND gate G1; the output end of the inverter INV13 is connected to an input end of the NAND gate G2; The output end of the NAND gate G1 is connected to the input end of the inverter INV15, the output end of the inverter INV15 is connected to the input end of the inverter INV16, and the output end of the inverter INV16 is connected to one input end of the NAND gate G3; The input signal VIN is connected to the other input terminal of the NAND gate G3, the output terminal of the NAND gate G3 is connected to the input terminal of the inverter INV17, the output terminal of the inverter INV17 is connected to the input terminal of the inverter INV18, the output terminal of the inverter INV18 is connected to the input terminal of the inverter INV19, the output terminal of the inverter INV19 is connected to the other input terminal of the NAND gate G2, the output terminal of the NAND gate G2 is connected to the input terminal of the inverter INV20, and the output terminal of the inverter INV20 provides a second input terminal voltage VINN.

Images