Peak current compensation circuit based on NTC (Negative Temperature Coefficient)

Abstract

The invention discloses a peak current compensation circuit based on NTC (Negative Temperature Coefficient), which comprises a main body circuit for realizing peak current compensation, four NMOS (N-channel Metal Oxide Semiconductor) tubes, ten PMOS (P-channel Metal Oxide Semiconductor) tubes, two PNP (Positive-Negative-Positive) tubes, five NPN (Negative-Positive-Negative-Positive) tubes and three resistors.

Description

Technical Field

[0001] The invention belongs to the field of power management, and in particular relates to a peak current mode switching power supply. Background Art

[0002] In the field of switching power supplies, the peak current control mode has been widely used as a mature control structure with the advantages of fast closed-loop response speed, single-pole system, and relatively simple loop control. Since the inductor current is directly sampled, the change of input voltage will be directly reflected in the inductor current. Therefore, the peak current mode has a faster transient response to the change of input voltage and the change of output load. When sampling the inductor current, it is usually adopted to directly detect the two ends of the inductor. This method of non-destructive detection of instantaneous current can provide higher efficiency and can realize the application of large output current. However, the inductor is made of copper, and its DC resistance is usually a positive temperature coefficient. As the temperature of the inductor increases, its DCR value increases. Therefore, the peak current limit of the peak current mode is reduced. Summary of the invention

[0003] The present invention realizes the compensation of peak current based on the fact that NTC voltage has negative temperature characteristics.

[0004] In order to solve the above problems existing in the prior art, the technical solution adopted by the present invention is:

[0005] A peak current compensation circuit based on NTC, characterized by comprising: a first P-type MOS transistor MP1, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3, a fourth P-type MOS transistor MP4, a fifth P-type MOS transistor MP5, a sixth P-type MOS transistor MP6, a seventh P-type MOS transistor MP7, an eighth P-type MOS transistor MP8, a ninth P-type MOS transistor MP9, a tenth P-type MOS transistor MP10, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a third N-type MOS transistor MN3, a fourth N-type MOS transistor MN4, a first NPN-type transistor NPN1, a second NPN-type transistor NPN2, a third NPN-type transistor NPN3, a fourth NPN-type transistor NPN4, a fifth NPN-type transistor NPN5, a first PNP-type transistor PNP1, a second PNP-type transistor PNP2, a first resistor R1, a second resistor R2 and a third resistor R3;

[0006] The source of the first P-type MOS transistor MP1, the source of the third P-type MOS transistor MP3, the source of the fifth P-type MOS transistor MP5, the source of the seventh P-type MOS transistor MP7, the source of the eighth P-type MOS transistor MP8, the source of the ninth P-type MOS transistor MP9, the source of the tenth P-type MOS transistor MP10, and one end of the current source IBIAS are connected to the power source INTVCC;

[0007] The gate of the first P-type MOS transistor MP1, the gate of the second P-type MOS transistor MP2, the drain of the second P-type MOS transistor MP2, the drain of the third N-type MOS transistor MN3, the gate of the third P-type MOS transistor MP3, the gate of the fourth P-type MOS transistor MP4, the gate of the fifth P-type MOS transistor MP5 and the gate of the sixth P-type MOS transistor MP6 are connected;

[0008] The other end of the current source IBIAS, the gate of the first N-type MOS transistor MN1, the drain of the first N-type MOS transistor MN1, the gate of the second N-type MOS transistor MN2, the gate of the third N-type MOS transistor MN3 and the gate of the fourth N-type MOS transistor MN4 are connected;

[0009] The source of the first N-type MOS transistor MN1 is connected to the drain of the second N-type MOS transistor MN2, and the source of the third N-type MOS transistor MN3 is connected to the drain of the fourth N-type MOS transistor MN4;

[0010] The drain of the first P-type MOS transistor MP1 is connected to the source of the second P-type MOS transistor MP2, the drain of the third P-type MOS transistor MP3 is connected to the source of the fourth P-type MOS transistor MP4, the drain of the fifth P-type MOS transistor MP5 is connected to the source of the sixth P-type MP6, the drain of the fourth P-type MOS transistor MP4, the collector of the first NPN-type transistor NPN1, the base of the first NPN-type transistor NPN1 and the base of the second NPN-type transistor NPN2 are connected;

[0011] The emitter of the first NPN transistor NPN1 and one end of the first resistor R1 are connected to the emitter of the third NPN transistor NPN3, the other end of the first resistor R1 is connected to the emitter of the first PNP transistor PNP1, the emitter of the second NPN transistor NPN2 is connected to one end of the second resistor R2, the other end of the second resistor R2 and the emitter of the second PNP transistor PNP2 are connected to the drain of the eighth P-type MOS transistor MP8, the base of the first PNP transistor PNP1 is connected to the external input port ITEMP, and the base of the second PNP transistor PNP2 is connected to the external input port VREF;

[0012] The drain of the sixth P-type MOS transistor MP6, the collector of the second NPN-type transistor NPN2, and the base of the third NPN-type transistor NPN3 are connected; the gate of the seventh N-type MOS transistor MP7, the drain of the seventh N-type MOS transistor MP7, the collector of the third NPN-type transistor NPN3, the gate of the eighth P-type MOS transistor MP8, the gate of the ninth P-type MOS transistor MP9, and the gate of the tenth N-type MOS transistor MP10 are connected; the drain of the ninth P-type MOS transistor MP9, the collector of the fourth NPN-type transistor NPN4, and the base of the fourth NPN-type transistor NPN4 are connected to the base of the fifth NPN-type transistor NPN5; the drain of the tenth P-type MOS transistor MP10 and one end of the third resistor R3 are connected to the external output port V1; and the other end of the third resistor R3 and the collector of the fifth NPN-type transistor NPN5 are connected to the external output port V2.

[0013] The beneficial effects of the present invention are as follows: the present invention realizes a voltage with a negative temperature coefficient through an NTC thermistor, and compares it with a reference voltage, converts it into a current to adjust the peak current of the system, thereby realizing compensation of the peak current. The entire circuit structure is simple in design, meets the current requirements for highly integrated and miniaturized integrated circuit design, and has high practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a structural schematic diagram of the present invention. DETAILED DESCRIPTION

[0015] The present invention will be further described below with reference to the accompanying drawings and the accompanying drawings.

[0016] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0017] The terms “first”, “second”, “third”, etc. are only used for distinguishing descriptions and should not be understood as indicating or implying relative importance.

[0018] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0019] The specific implementation of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the present invention, and is not used to limit the present invention.

[0020] Embodiment 1:

[0021] like Figure 1 As shown, a peak current compensation circuit based on NTC includes a first P-type MOS transistor MP1, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3, a fourth P-type MOS transistor MP4, a fifth P-type MOS transistor MP5, a sixth P-type MOS transistor MP6, a seventh P-type MOS transistor MP7, an eighth P-type MOS transistor MP8, a ninth P-type MOS transistor MP9, a tenth P-type MOS transistor MP10, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a third N-type MOS transistor MN3, a fourth N-type MOS transistor MN4, a first NPN-type transistor NPN1, a second NPN-type transistor NPN2, a third NPN-type transistor NPN3, a fourth NPN-type transistor NPN4, a fifth NPN-type transistor NPN5, a first PNP-type transistor PNP1, a second PNP-type transistor PNP2, a first resistor R1, a second resistor R2 and a third resistor R3;

[0022] The source of the first P-type MOS transistor MP1, the source of the third P-type MOS transistor MP3, the source of the fifth P-type MOS transistor MP5, the source of the seventh P-type MOS transistor MP7, the source of the eighth P-type MOS transistor MP8, the source of the ninth P-type MOS transistor MP9, the source of the tenth P-type MOS transistor MP10, and one end of the current source IBIAS are connected to the power source INTVCC;

[0023] The gate of the first P-type MOS transistor MP1, the gate of the second P-type MOS transistor MP2, the drain of the second P-type MOS transistor MP2, the drain of the third N-type MOS transistor MN3, the gate of the third P-type MOS transistor MP3, the gate of the fourth P-type MOS transistor MP4, the gate of the fifth P-type MOS transistor MP5 and the gate of the sixth P-type MOS transistor MP6 are connected;

[0024] The other end of the current source IBIAS, the gate of the first N-type MOS transistor MN1, the drain of the first N-type MOS transistor MN1, the gate of the second N-type MOS transistor MN2, the gate of the third N-type MOS transistor MN3 and the gate of the fourth N-type MOS transistor MN4 are connected;

[0025] The source of the first N-type MOS transistor MN1 is connected to the drain of the second N-type MOS transistor MN2, and the source of the third N-type MOS transistor MN3 is connected to the drain of the fourth N-type MOS transistor MN4;

[0026] The drain of the first P-type MOS transistor MP1 is connected to the source of the second P-type MOS transistor MP2, the drain of the third P-type MOS transistor MP3 is connected to the source of the fourth P-type MOS transistor MP4, the drain of the fifth P-type MOS transistor MP5 is connected to the source of the sixth P-type MP6, the drain of the fourth P-type MOS transistor MP4, the collector of the first NPN-type transistor NPN1, the base of the first NPN-type transistor NPN1 and the base of the second NPN-type transistor NPN2 are connected;

[0027] The emitter of the first NPN transistor NPN1 and one end of the first resistor R1 are connected to the emitter of the third NPN transistor NPN3, the other end of the first resistor R1 is connected to the emitter of the first PNP transistor PNP1, the emitter of the second NPN transistor NPN2 is connected to one end of the second resistor R2, the other end of the second resistor R2 and the emitter of the second PNP transistor PNP2 are connected to the drain of the eighth P-type MOS transistor MP8, the base of the first PNP transistor PNP1 is connected to the external input port ITEMP, and the base of the second PNP transistor PNP2 is connected to the external input port VREF;

[0028] The drain of the sixth P-type MOS transistor MP6, the collector of the second NPN-type transistor NPN2, and the base of the third NPN-type transistor NPN3 are connected; the gate of the seventh N-type MOS transistor MP7, the drain of the seventh N-type MOS transistor MP7, the collector of the third NPN-type transistor NPN3, the gate of the eighth P-type MOS transistor MP8, the gate of the ninth P-type MOS transistor MP9, and the gate of the tenth N-type MOS transistor MP10 are connected; the drain of the ninth P-type MOS transistor MP9, the collector of the fourth NPN-type transistor NPN4, and the base of the fourth NPN-type transistor NPN4 are connected to the base of the fifth NPN-type transistor NPN5; the drain of the tenth P-type MOS transistor MP10 and one end of the third resistor R3 are connected to the external output port V1; and the other end of the third resistor R3 and the collector of the fifth NPN-type transistor NPN5 are connected to the external output port V2.

[0029] Specific working principle:

[0030] In the circuit, because R1=R2, so:

[0031] (I1+I2)·R1+V e_PNP1 =I1·R2+V e_PNP2

[0032]

[0033] And because,

[0034] V1-V2=I1·R3,R3=2R1=2R2,so:

[0035]

[0036]

[0037] Since V NTC is a voltage with a negative temperature coefficient, V REF is the internal reference voltage, which is a voltage with zero temperature coefficient, and V2 is a voltage with zero temperature coefficient, so the change of V1 is related to V NTC The change is opposite, that is, when the temperature rises, V NTC When the voltage decreases, the voltage of V1 increases. When the temperature decreases, V NTC As the voltage increases, V1 decreases, so the change in peak current can be controlled by the change in V1, achieving temperature compensation.

[0038] The present invention is not limited to the above-mentioned optional implementation modes. Anyone can derive other various forms of products under the inspiration of the present invention. However, no matter what changes are made in the shape or structure, all technical solutions that fall within the scope defined by the claims of the present invention fall within the protection scope of the present invention.

Claims

1. A peak current compensation circuit based on NTC, characterized in that: Including a first P-type MOS transistor MP1, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3, a fourth P-type MOS transistor MP4, a fifth P-type MOS transistor MP5, a sixth P-type MOS transistor MP6, a seventh P-type MOS transistor MP7, an eighth P-type MOS transistor MP8, a ninth P-type MOS transistor MP9, a tenth P-type MOS transistor MP10, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a third N-type MOS transistor MN3, a fourth N-type MOS transistor MN4, a first NPN-type transistor NPN1, a second NPN-type transistor NPN2, a third NPN-type transistor NPN3, a fourth NPN-type transistor NPN4, a fifth NPN-type transistor NPN5, a first PNP-type transistor PNP1, a second PNP-type transistor PNP2, a first resistor R1, a second resistor R2 and a third resistor R3; The source of the first P-type MOS transistor MP1, the source of the third P-type MOS transistor MP3, the source of the fifth P-type MOS transistor MP5, the source of the seventh P-type MOS transistor MP7, the source of the eighth P-type MOS transistor MP8, the source of the ninth P-type MOS transistor MP9, the source of the tenth P-type MOS transistor MP10, and one end of the current source IBIAS are connected to the power source INTVCC; The gate of the first P-type MOS transistor MP1, the gate of the second P-type MOS transistor MP2, the drain of the second P-type MOS transistor MP2, the drain of the third N-type MOS transistor MN3, the gate of the third P-type MOS transistor MP3, the gate of the fourth P-type MOS transistor MP4, the gate of the fifth P-type MOS transistor MP5 and the gate of the sixth P-type MOS transistor MP6 are connected; The other end of the current source IBIAS, the gate of the first N-type MOS transistor MN1, the drain of the first N-type MOS transistor MN1, the gate of the second N-type MOS transistor MN2, the gate of the third N-type MOS transistor MN3 and the gate of the fourth N-type MOS transistor MN4 are connected; The source of the first N-type MOS transistor MN1 is connected to the drain of the second N-type MOS transistor MN2, and the source of the third N-type MOS transistor MN3 is connected to the drain of the fourth N-type MOS transistor MN4; The drain of the first P-type MOS transistor MP1 is connected to the source of the second P-type MOS transistor MP2, the drain of the third P-type MOS transistor MP3 is connected to the source of the fourth P-type MOS transistor MP4, the drain of the fifth P-type MOS transistor MP5 is connected to the source of the sixth P-type MP6, the drain of the fourth P-type MOS transistor MP4, the collector of the first NPN-type transistor NPN1, the base of the first NPN-type transistor NPN1 and the base of the second NPN-type transistor NPN2 are connected; The emitter of the first NPN transistor NPN1 and one end of the first resistor R1 are connected to the emitter of the third NPN transistor NPN3, the other end of the first resistor R1 is connected to the emitter of the first PNP transistor PNP1, the emitter of the second NPN transistor NPN2 is connected to one end of the second resistor R2, the other end of the second resistor R2 and the emitter of the second PNP transistor PNP2 are connected to the drain of the eighth P-type MOS transistor MP8, the base of the first PNP transistor PNP1 is connected to the external input port ITEMP, and the base of the second PNP transistor PNP2 is connected to the external input port VREF; The drain of the sixth P-type MOS transistor MP6, the collector of the second NPN-type transistor NPN2, and the base of the third NPN-type transistor NPN3 are connected; the gate of the seventh N-type MOS transistor MP7, the drain of the seventh N-type MOS transistor MP7, the collector of the third NPN-type transistor NPN3, the gate of the eighth P-type MOS transistor MP8, the gate of the ninth P-type MOS transistor MP9, and the gate of the tenth N-type MOS transistor MP10 are connected; the drain of the ninth P-type MOS transistor MP9, the collector of the fourth NPN-type transistor NPN4, and the base of the fourth NPN-type transistor NPN4 are connected to the base of the fifth NPN-type transistor NPN5; the drain of the tenth P-type MOS transistor MP10 and one end of the third resistor R3 are connected to the external output port V1; and the other end of the third resistor R3 and the collector of the fifth NPN-type transistor NPN5 are connected to the external output port V2.

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