SSO noise improvement circuit

Abstract

The invention provides an SSO noise improvement circuit. The SSO noise improvement circuit comprises an I / O input module and an I / O output module, the ideal power supply end is electrically connected with power supplies of the I / O input module and the I / O output module through a first bonding wire and a second bonding wire respectively; the I / O port is electrically connected with the I / O output module through a third bonding wire; the ideal grounding end is electrically connected with the grounds of the I / O input module and the I / O output module through a fourth bonding wire and a fifth bonding wire respectively; when the circuit works, the power supply and the ground of the I / O input module are not affected by SSO noise which is larger than a target value and caused by overturning of a driving tube in the I / O output module, and because the current of a logic tube in the I / O input module circuit is smaller than a preset value, power supply jitter of the I / O input module is basically restrained. When the circuit works, the voltage connected to the I / O input module after the ideal power supply end and the grounding end of the I / O module pass through the bonding wire is not influenced by the SSO noise of the I / O output module, and the current of a logic tube in the I / O input module circuit is smaller than a preset value, so that the power supply jitter of the I / O input module is basically inhibited.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a SSO noise improvement circuit. Background Art

[0002] SSO (simultaneously switching outputs) noise is one of the important factors that affect the normal operation of I / O circuits. Figure 1 As shown in the figure, the equivalent model of the package of a single pin of the chip is shown as the bonding wire in the figure, including the parasitic capacitance, parasitic resistance and parasitic inductance caused by the package. When the I / O pin (port) generates a logic flip, the driver tube of the I / O output module is turned on, and a certain current flows through the power supply / ground through the bonding wire inductance, generating a voltage difference V=L(di / dt) at both ends of the parasitic inductance. The more I / Os flip, the greater the voltage difference caused by the current superposition, making the power supply / ground of the chip different from the external VDDH / VSSH, resulting in I / O power jitter, that is, SSO noise. When the noise is serious, the potential recognition will be wrong, resulting in circuit logic errors.

[0003] For example, when the I / O pin flips from 1 to 0, the load capacitor discharges, and the current flows to the external ground through the bonding wire inductance, causing a voltage difference between the I / O ground and the external ground VSSH. The local jitter is large, and when it exceeds VIL, the low level in the circuit will be considered a high level, causing errors in the circuit logic, such as Figure 2 As shown in the figure, the output signal y of the I / O input module has glitches.

[0004] In order to solve the above problems, a new type of SSO noise improvement circuit needs to be proposed. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an SSO noise improvement circuit for solving the problem in the prior art that when the SSO noise is serious, errors may occur in potential identification, resulting in circuit logic errors.

[0006] To achieve the above objectives and other related objectives, the present invention provides a SSO noise improvement circuit, comprising:

[0007] I / O input module and I / O output module;

[0008] An ideal power supply terminal, which is electrically connected to the power supplies of the I / O input module and the I / O output module through first and second bonding wires respectively;

[0009] An I / O port electrically connected to the I / O output module via a third bonding wire;

[0010] an ideal ground terminal, which is electrically connected to the ground of the I / O input module and the ground of the I / O output module through the fourth and fifth bonding wires respectively;

[0011] When the circuit is working, the power supply / ground voltage of the I / O input module is not affected by the SSO noise greater than the target value caused by the flipping of the driving tube in the I / O output module, and the logic tube current in the I / O input module circuit is less than the preset value, so that the power supply jitter of the I / O input module is basically suppressed.

[0012] Preferably, the ideal power supply terminal is used to provide a power supply voltage VDDH.

[0013] Preferably, the ideal ground terminal is used to provide a ground voltage VSSH.

[0014] Preferably, the first to fifth bonding wires include parasitic capacitance, parasitic resistance and parasitic inductance caused by packaging.

[0015] Preferably, when the I / O port generates a logic flip, the driving tube of the I / O output module is turned on.

[0016] As described above, the SSO noise improvement circuit of the present invention has the following beneficial effects:

[0017] When the circuit of the present invention is working, the voltage of the ideal power supply terminal and the ideal ground terminal connected to the I / O input module after passing through the bonding wire is not affected by the SSO noise greater than the target value caused by the flipping of the driving tube in the I / O output module, and the logic tube current in the I / O input module circuit is less than the preset value, so that the power jitter of the I / O input module is basically suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Shown is a schematic diagram of the generation of SSO noise in the prior art;

[0019] Figure 2 Schematic diagram showing circuit logic error caused by SSO noise in the prior art (a is the input signal of the I / O input module, y is the output signal of the I / O input module, vssh1 is the ground voltage of the I / O module);

[0020] Figure 3 Shown is a schematic diagram of the SSO noise improvement circuit of the present invention;

[0021] Figure 4Shown is a schematic diagram of the circuit simulation results of the SSO noise improvement circuit of the present invention (vddh1 and vsh1 are the power supply and ground voltage of the I / O output module, vddh_input and vsh_input are the power supply and ground voltage of the I / O input module, and y is the output signal of the I / O input module). DETAILED DESCRIPTION

[0022] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0023] See also Figure 3 The present invention provides a SSO noise improvement circuit, comprising:

[0024] I / O input module 102 and I / O output module 101;

[0025] An ideal power supply terminal 103, which is electrically connected to the I / O input module 102 and the I / O output module 101 through first and second bonding wires (201, 202) respectively;

[0026] In some embodiments, the ideal power terminal 103 is used to provide a power supply voltage VDDH, which is used to power the device.

[0027] The I / O port 104 is electrically connected to the I / O output module 101 via a third bonding wire 203;

[0028] An ideal ground terminal 105, which is electrically connected to the I / O input module 102 and the I / O output module 101 through the fourth and fifth bonding wires (204, 205) respectively;

[0029] In some embodiments, the ideal ground terminal 105 is used to provide a ground voltage VSSH.

[0030] When the circuit is working, the voltage of the ideal power terminal 103 and the ideal ground terminal 105 connected to the I / O input module 102 after passing through the bonding wire is not affected by the SSO noise greater than the target value caused by the flipping of the driving tube in the I / O output module 101, and the logic tube current in the circuit of the I / O input module 102 is less than the preset value, so that the power jitter of the I / O input module 102 is basically suppressed.

[0031] In some embodiments, the first to fifth bonding wires include parasitic capacitance, parasitic resistance, and parasitic inductance caused by the package.

[0032] In some embodiments, when the I / O port 104 generates a logic flip, the driver tube of the I / O output module 101 is turned on.

[0033] See also Figure 4 ,The power jitter of the improved circuit is shown in the figure. The jitter of the power voltage (vddh_input) and the ground voltage (vssh_input) of the I / O input module 102 is very small and is not affected by the power jitter (vddh1 and vssh1) of the I / O output module 101. The burrs in the output signal y of the I / O input module 102 also disappear.

[0034] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0035] In summary, when the circuit of the present invention is working, the voltage of the ideal power supply terminal and the ground terminal of the I / O module connected to the I / O input module through the bonding wire is not affected by the SSO noise greater than the target value caused by the flipping of the driving tube in the I / O output module, and the logic tube current in the I / O input module circuit is less than the preset value, so that the power jitter of the I / O input module is basically suppressed. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0036] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A SSO noise improvement circuit, characterized in that: At least: I / O input module and I / O output module; An ideal power supply terminal, which is electrically connected to the power supplies of the I / O input module and the I / O output module through first and second bonding wires respectively; An I / O port electrically connected to the I / O output module via a third bonding wire; an ideal ground terminal, which is electrically connected to the ground of the I / O input module and the ground of the I / O output module through the fourth and fifth bonding wires respectively; When the circuit is working, the voltage of the ideal power supply terminal and the ideal ground terminal of the I / O module connected to the I / O input module through the bonding wire is not affected by the SSO noise greater than the target value caused by the flipping of the driving tube in the I / O output module. Since the logic tube current in the I / O input module circuit is less than the preset value, the power jitter of the I / O input module is basically suppressed.

2. The SSO noise improvement circuit according to claim 1, characterized in that: The ideal power supply terminal is used to provide a power supply voltage VDDH.

3. The SSO noise improvement circuit according to claim 1, characterized in that: The ideal ground terminal is used to provide a ground voltage VSSH.

4. The SSO noise improvement circuit according to claim 1, characterized in that: The first to fifth bonding wires include parasitic capacitance, parasitic resistance and parasitic inductance caused by packaging.

5. The SSO noise improvement circuit according to claim 1, characterized in that: When the I / O port generates a logic flip, the driver tube of the I / O output module is turned on.

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