Data low-delay transceiving method and device, network equipment and storage medium

Abstract

The embodiment of the invention relates to a data low-delay receiving and transmitting method and device, network equipment and a storage medium. The low-delay transceiver comprises the following steps of: analyzing a received message in a Pipeline mode on an MAC (Media Access Control) layer of the low-delay transceiver to obtain a frame detection sequence of the received message; in response to the inconsistency of the frame detection sequence and the verification sequence, updating the frame detection sequence of the received message to a target sequence, and forwarding the updated received message; the value of at least one bit in the target sequence is different from that of at least one bit in the verification sequence. According to the embodiment of the invention, the message is analyzed in a Pipeline mode, and the message does not need to be forwarded after the whole frame of message is received, so that the time delay of forwarding the message can be reduced, and the requirement of a service scene can be met.

Description

Technical Field

[0001] The present disclosure relates to the field of signal processing technology, and in particular to a method, device, network equipment and storage medium for low-latency data transmission and reception. Background Art

[0002] Some business scenarios require higher data transmission efficiency, such as securities quantitative trading, and therefore require network equipment such as low-latency switches.

[0003] Taking a low-latency switch as an example, existing solutions usually use a Field-Programmable Gate Array (FPGA) to implement the low-latency switch.

[0004] In actual applications, FPGA devices have a large delay in sending and receiving messages and cannot meet the needs of the above business scenarios. Summary of the invention

[0005] The present invention provides a method, apparatus, network device and storage medium for transmitting and receiving data with low latency to solve the deficiencies of related technologies.

[0006] According to a first aspect of an embodiment of the present disclosure, a method for low-latency data transceiver is provided, which is applicable to a low-latency transceiver, and the method includes:

[0007] The MAC layer of the low-latency transceiver uses a pipeline method to parse the received message to obtain a frame detection sequence of the received message;

[0008] In response to the frame detection sequence being inconsistent with the check sequence, the frame detection sequence of the received message is updated to a target sequence, and the updated received message is forwarded; the target sequence and the check sequence have different values ​​for at least one bit.

[0009] Optionally, the method further comprises:

[0010] The updated received message is logically processed and then sent to the opposite device. The opposite device discards the updated received message when detecting the target sequence in the received message.

[0011] Optionally, the method further comprises:

[0012] The MAC layer of the low-latency transceiver processes the transmission message in a Pipeline manner, and adds a preset control code to the transmission message during the Pipeline manner processing to obtain the coded transmission message.

[0013] Optionally, the method further comprises:

[0014] Scrambling the coded transmission message to obtain a transmission message of a second length;

[0015] Performing length conversion on the sending message of the second length to obtain a sending message of the first length;

[0016] The sending message of the first length is logically processed to obtain a receiving message to be forwarded.

[0017] Optionally, the method further comprises:

[0018] Obtaining a received message of a first length;

[0019] Aligning the message header and the received message according to the position information in the message header of the received message to obtain a received message of a second length; the second length is greater than the first length;

[0020] Performing descrambling processing on the received message of the second length to obtain a data block type;

[0021] The message payload of the received message is acquired and forwarded according to the data block type.

[0022] According to a second aspect of an embodiment of the present disclosure, a low-latency data transceiver device is provided, the device comprising:

[0023] A detection sequence acquisition module, used to parse the received message in a Pipeline manner at the MAC layer of the low-latency transceiver to obtain a frame detection sequence of the received message;

[0024] The update message acquisition module is used to update the frame detection sequence of the received message to a target sequence in response to the inconsistency between the frame detection sequence and the check sequence, and forward the updated received message; the target sequence and the check sequence have different values ​​for at least one bit.

[0025] Optionally, the device further comprises:

[0026] The update message forwarding module is used to perform logical processing on the updated received message and then send it to the opposite end device, and the opposite end device discards the updated received message when detecting the target sequence in the received message.

[0027] Optionally, the device further comprises:

[0028] The coded message acquisition module is used to process the transmitted message in a Pipeline manner at the MAC layer of the low-latency transceiver, and add a preset control code to the transmitted message during the Pipeline manner processing to obtain the coded transmitted message.

[0029] Optionally, the device further comprises:

[0030] A message transmission acquisition module, used for scrambling the coded message transmission to obtain a message transmission of a second length;

[0031] A sending message conversion module, used for performing length conversion on the sending message of the second length to obtain a sending message of the first length;

[0032] The sending message processing module is used to perform logical processing on the sending message of the first length to obtain the receiving message to be forwarded.

[0033] Optionally, the device further comprises:

[0034] A received message acquisition module, used to acquire a received message of a first length;

[0035] A received message alignment module, used to align the message header and the received message according to the position information in the message header of the received message, so as to obtain a received message of a second length; the second length is greater than the first length;

[0036] A received message scrambling module, used for performing a descrambling process on the received message of the second length to obtain a data block type;

[0037] A message payload forwarding module is used to obtain and forward the message payload of the received message according to the data block type.

[0038] According to a third aspect of an embodiment of the present disclosure, there is provided a network device, including: a processor and a memory;

[0039] The memory is used to store a computer program executable by the processor;

[0040] The processor is configured to execute the computer program in the memory to implement the method as described in any one of the first aspects.

[0041] According to a fourth aspect of an embodiment of the present disclosure, a non-transitory computer-readable storage medium is provided, and when an executable computer program in the storage medium is executed by a processor, the method described in any one of the first aspects can be implemented.

[0042] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects:

[0043] A method for low-latency data transmission and reception provided by an embodiment of the present disclosure can parse a received message in a Pipeline manner at the MAC layer of the low-latency transceiver to obtain a frame detection sequence of the received message; then, in response to the inconsistency between the frame detection sequence and the check sequence, the frame detection sequence of the received message is updated to a target sequence, and the updated received message is forwarded; the target sequence and the check sequence have different values ​​for at least one bit. In this way, in this embodiment, the message is parsed in a Pipeline manner without forwarding the message after receiving the entire frame message, which can reduce the delay of forwarding the message and is conducive to meeting the needs of business scenarios.

[0044] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0046] Figure 1 The invention is a block diagram of a low-latency transceiver according to an exemplary embodiment.

[0047] Figure 2 The figure is a block diagram showing a PCS layer receiving a message according to an exemplary embodiment.

[0048] Figure 3 It is a block diagram of a message receiving method shown in the related art.

[0049] Figure 4 The figure is a block diagram showing a PCS sending a message according to an exemplary embodiment.

[0050] Figure 5 It is a block diagram of sending a message shown in the related art.

[0051] Figure 6 The present invention is a flowchart of a method for transmitting and receiving data with low latency according to an exemplary embodiment. DETAILED DESCRIPTION

[0052] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described below by way of example do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices consistent with some aspects of the present disclosure as detailed in the appended claims.

[0053] The embodiments of the present disclosure provide a method, device, network device and storage medium for low-latency data transceiver. The above-mentioned method for low-latency data transceiver can be applicable to a low-latency transceiver, and the low-latency transceiver can be applicable to a network device. The network device may include but is not limited to a router, a switch or a server intelligent network card, etc. It is understandable that the above-mentioned low-latency transceiver and / or network device can be implemented in hardware, that is, by setting a circuit, the above-mentioned method for low-latency data transceiver is implemented by the circuit. The above-mentioned low-latency transceiver and / or network device can be implemented in software, that is, the above-mentioned method for low-latency data transceiver is implemented by a computer-readable program.

[0054] To facilitate understanding of the solution, this embodiment provides a logical architecture of a low-latency transceiver. Figure 1 , a low-latency transceiver provided by an embodiment of the present disclosure includes: a logic unit 11. The logic unit 11 is used to perform serial-to-parallel conversion processing and analog signal processing on original data to obtain a received message or a sent message.

[0055] In this embodiment, the original data refers to data without coding or decoding. Considering that the original data is not encoded, there is no need to set a buffer, and the redundant operation pipeline is removed, which can reduce the delay of sending and receiving messages, realize the low-latency transmission feature function, and thus meet the needs of business scenarios.

[0056] In this embodiment, the logic unit 11 reduces the latency in the physical medium attachment (PMA). Considering that the low latency transceiver also includes a physical coding sublayer (PCS), the latency of the PCS layer can be reduced based on the latency reduction of the PMA layer.

[0057] Continue to see Figure 1 The low-latency transceiver further includes a synchronization module 12, a first conversion module 13 and a descrambling module 14.

[0058] The synchronization module 12 is used to determine the position information of the message header in the received message; the received message is sent to the synchronization module 12 by the logic unit 11, and the length of the received message is a first length, such as 64 bits.

[0059] The first conversion module 13 is used to align the message header and the received message according to the position information of the message header to obtain a received message of a second length; the second length is greater than the first length; for example, the second length is 66 bits.

[0060] The descrambling module 14 is used to perform descrambling processing on the received message of the second length to obtain a data block type (blocktype); and obtain a message payload of the received message according to the data block type, wherein the message payload is the content to be transmitted.

[0061] Taking the FPGA using a high-speed transceiver as an example, it is provided with a 64 / / 66B encoded serial interface, namely a 10GBASE-R interface, which can support the transmission of data streams on optical media, and the data stream speed is 10Gbit / s. The above-mentioned 10GBASE-R interface adopts 64B / 66B encoding when implementing the above-mentioned first conversion module 13, that is, 64-bit data or control information is encoded into a 66-bit block for transmission, and the first two bits of the 66-bit block represent the message header. The above-mentioned message header is used for data alignment at the receiving end and synchronization of the received data bit stream. In one example, the message header can include "01" and "10", "01" means that the following 64 bits are all data, and "10" means that the following 64 bits are a combination of data and control information.

[0062] Continue to see Figure 1 The first conversion module 13 and the descrambling module 14 constitute a data path to transmit the content to be transmitted, that is, the message payload. The synchronization module 12 bypasses the data path to constitute a control path for aligning the transmission logic unit 11 and the first conversion module 13.

[0063] After receiving the serial data, the logic unit 11 converts the serial data into parallel data, i.e., the above-mentioned received message, and sends the received message to the first conversion module 13 and the synchronization module 12. The synchronization module 12 is used to detect the message header in the received message. The message header may be at any position in the received message, and the position of the message data can be determined only after determining the message header of the received message.

[0064] It should be noted that there are 66 possible positions of the message header. The message header occupies 2 bits and appears once every 32 bits of data. At this time, there will be a 2-bit misalignment, so each round is 32 clock cycles. Assuming that the start detection time is recorded as 0, the newly received 32-bit data is simultaneously matched with 66 patterns. When the message header position of the newly received 32-bit data is 2'b01 or 2'b10, the pattern match is determined, and the matching value is cnt+1 at this time; if the pattern is matched for 64 consecutive times and other patterns fail to match, the mode is confirmed to be the final alignment mode, and the synchronization valid flag Syn Valid is output as an alignment instruction for the first conversion module 13 to use.

[0065] The first conversion module 13 outputs a 2-bit message header and 64-bit data according to the position information of the message header to align the message header and the received message, obtain a received message of the second length, and realize alignment from 64-bit data to 66-bit data. It is understandable that in the process of aligning the 2-bit message header and the 64-bit data by the first conversion module 13, one beat of data will be invalid every 33 clock cycles, and the data will be delayed by 0-1 clock cycles to wait for the 64-bit data to be assembled.

[0066] In one embodiment, the descrambling module 14 performs descrambling processing on the received message of the second length output by the first conversion module 13. In one example, the descrambling module 14 can use a linear feedback shift register (LFSR) to generate a pseudo-random binary sequence (PRBS), which has a property similar to white noise. In this example, the generating polynomial of the PRBS sequence is represented by X58+X39+1, where X represents the delay unit in the shift register, the number represents the number of delay steps, and "+" represents an exclusive OR operation, that is, "X58" means that the bit after 58 steps of delay is fed back to the input, "X39" means that the bit after 39 steps of delay is fed back to the input, and "1" means that there is a fixed bit (usually the lowest bit of the register) fed back to the input. In this example, the data block and the data block type (Block type) of the received message can be obtained through decoding processing, and then the message header (sop) and the message tail (eop) are obtained according to the data block type, that is, the message payload is obtained.

[0067] In the above embodiment, the PCS is provided with a synchronization module 12, a first conversion module 13 and a descrambling module 14 to reduce the delay in receiving message transmission. In one embodiment, the delay in receiving messages by the medium access control layer (MAC) can also be reduced. Figure 1 The low-latency transceiver also includes a RX_MAC module 15 and a receiving processing module 16.

[0068] The RX_MAC module 15 is used to process the message payload in a pipeline manner, obtain a frame check sequence during the pipeline processing, and update the frame check sequence to a target sequence when the frame check sequence is inconsistent with the check sequence to obtain an updated received message.

[0069] It should be noted that the above-mentioned frame check sequence (FCS) is a redundant check method for detecting whether an error occurs in a data frame during transmission. It is an application of a cyclic redundancy check (CRC) and is usually attached to the end of a data frame. The process of obtaining the above-mentioned frame check sequence can refer to the relevant technology. In addition, the process of obtaining the check sequence can also refer to the relevant technology.

[0070] In one example, see Figure 2 During the Pipeline mode processing (about 2-3 clock cycles), the RX_MAC module 15 can obtain the FCS sequence; and the RX_MAC module 15 can calculate the check sequence according to the message payload. If the FCS sequence is consistent with the check sequence, it means that the message payload is correct; if the FCS sequence is inconsistent with the check sequence, it means that the message payload is wrong. The RX_MAC module 15 can flip at least one bit in the check sequence to obtain the above-mentioned target sequence. Since at least one bit of the target sequence is flipped compared to the check sequence, it is an abnormal sequence. Then the RX_MAC module 15 can replace the above-mentioned FCS sequence with the above-mentioned target sequence.

[0071] See also Figure 3 In the related art, the received message is stored in the RX BUFFER until the end of the message is detected, and then the complete received message is checked. If the FCS sequence of the received message passes the check, the complete received message is sent to the subsequent module. If the FCS sequence check fails, the message is discarded.

[0072] Combination Figure 2 and Figure 3 As can be seen from the example solution, the solution of this embodiment does not need to set BUFFER and does not need to obtain the entire message to forward the message, which can reduce the transmission delay. In other words, in the solution of this embodiment, all messages are forwarded, and only the error message needs to be marked, which can reduce the delay caused by receiving the entire message.

[0073] It should be noted that the above embodiment describes the process of the RX_MAC module 15 processing the received message through the Pipeline method. In addition, the RX_MAC module 15 also has functions such as counting statistics or other message processing methods, which can be set according to specific scenarios, and the corresponding scheme falls within the protection scope of this disclosure.

[0074] The above embodiment describes the receiving process from the FPGA transceiver IP core receiving the message to the receiving processing module sending the message. In one embodiment, the delay of the media access control layer sending the message can also be reduced. Figure 1The low-latency transceiver further includes a TX_MAC module 18 and a transmission processing module 17. The transmission processing module 17 is used to send the transmission message to the TX_MAC module. The TX_MAC module 18 is used to perform pipeline processing on the transmission message, and add a preset control code (such as the S code and T code required by 10GBASE-R) to the transmission message during the pipeline processing to obtain the coded transmission message.

[0075] See also Figure 4 After 2-3 clock cycles during the Pipeline processing, a preset control code (such as the S code, T code and other control codes required by 10GBASE-R) can be added to the transmission message to obtain the coded transmission message.

[0076] See also Figure 5 In the related art, during the process of receiving a transmission message, the transmission message is stored in a buffer TX BUFFER and is sent out after the transmission message is complete.

[0077] Combination Figure 4 and Figure 5 The illustrated solution, the solution of this embodiment does not need to set BUFFER and can send the coded sending message to the subsequent module after inserting the control code in 2-3 clock cycles, which can reduce the delay of sending data at the MAC layer.

[0078] In one embodiment, based on the PCS layer reducing the delay of sending the message, continue to refer to Figure 1 The low-latency transceiver further includes an scrambling module 19 and a second conversion module 20.

[0079] The scrambling module 19 is used to scramble the coded transmission message to obtain a transmission message of a second length;

[0080] The second conversion module 20 is used for performing length conversion on the second length of the sending message to obtain the first length of the sending message; and sending the first length of the sending message to the logic unit 11.

[0081] It should be noted that the scrambling module 19 scrambling the message and the descrambling module 14 descrambling operation are two inverse operations. Therefore, the scrambling module 19 and the descrambling module 14 can use the same linear feedback shift register to generate a pseudo-random binary sequence to ensure the randomness of the message during transmission and correctly restore the original data at the receiving end.

[0082] In this way, the low-latency transceiver provided in this embodiment can perform serial-to-parallel conversion on the original data in the logic unit 11, without using a cache BUFFER and reducing redundant pipelines, thereby achieving the effect of reducing latency at the PCS layer and MAC layer. It can be transplanted to different network devices and can also be applicable to FPGA circuit equipment and chip design.

[0083] Based on the above low-latency transceiver, the embodiment of the present disclosure further provides a method for low-latency data transceiver, which is applicable to the low-latency transceiver. Figure 6 , the method comprises steps 61 and 62:

[0084] In step 61, the MAC layer of the low-latency transceiver parses the received message in a Pipeline manner to obtain a frame detection sequence of the received message;

[0085] In this step, the MAC layer of the low-latency transceiver is provided with an RX_MAC module 15. Figure 1 , the RX_MAC module 15 no longer adopts the solution of receiving the entire message and buffering it in BUFFER, but adopts the following Figure 2 The RX_MAC module 15 can parse the frame detection sequence, ie, the FCS sequence, from the received message in 2-3 time cycles of the Pipeline processing.

[0086] In step 62, in response to the frame detection sequence being inconsistent with the check sequence, the frame detection sequence of the received message is updated to a target sequence, and the updated received message is forwarded; the target sequence and the check sequence have different values ​​for at least one bit.

[0087] In this step, the RX_MAC module 15 can also calculate a check sequence based on the message payload. Then, the RX_MAC module 15 can determine whether the FCS sequence is consistent with the check sequence. When the FCS sequence is consistent with the check sequence, it can be determined that the message payload is correct; when the FCS sequence is inconsistent with the check sequence, it can be determined that the message payload is wrong. The RX_MAC module 15 can flip at least one bit in the check sequence to obtain a target sequence. Since at least one bit of the target sequence is flipped compared to the check sequence, it is an abnormal sequence. Then the RX_MAC module 15 can replace the above FCS sequence with the above target sequence.

[0088] It should be noted that, in some possible examples, the RX_MAC module 15 can also replace the FCS sequence of the received message with a preset target sequence. For example, the target sequence is preset to a set of illegal values, and the opposite device cannot generate a check sequence when parsing the illegal value and directly discards the message, further reducing the delay.

[0089] In some possible examples, the low-latency data transmission and reception method provided by the present disclosure may further include: performing logical processing on the updated received message and then sending it to the peer device. Figure 1 The receiving processing module 16 of the low-latency transceiver can perform logical processing on the updated received message and send it to the peer device. When the peer device detects the target sequence in the received message, it can determine that the received message is wrong and discard the updated received message, and finally only retain the correct received message.

[0090] In some possible examples, the low-latency data transceiver method provided by the present disclosure may further include: processing the transmission message in a pipeline manner at the MAC layer of the low-latency transceiver, and adding a preset control code to the transmission message during the pipeline processing to obtain the coded transmission message. Figure 1 , the transmission processing module 17 of the low-latency transceiver can receive the transmission message and send it to the RX_MAC module 15. The RX_MAC module 15 can process the transmission message in a pipeline manner, and add a preset control code (such as the S code, T code and other control codes required by 10GBASE-R) to the transmission message during the processing in the pipeline manner to obtain the coded transmission message. In this way, the solution of this embodiment does not need to set the BUFFER and can send the coded transmission message to the subsequent module after inserting the control code in 2-3 clock cycles, which can reduce the delay of the MAC layer sending data.

[0091] In some possible examples, the low-latency data transmission and reception method provided by the present disclosure may also include: scrambling the coded transmission message to obtain a transmission message of a second length; performing length conversion on the transmission message of the second length to obtain a transmission message of a first length; performing logical processing on the transmission message of the first length to obtain a reception message to be forwarded. Figure 1 The scrambling module 19 of the low-latency transceiver can perform scrambling processing on the coded transmission message to obtain a transmission message of the second length. The second conversion module 20 of the low-latency transceiver can perform length conversion on the transmission message of the second length to obtain a transmission message of the first length. The logic unit 11 of the low-latency transceiver can perform logic processing on the transmission message of the first length to obtain a received message to be forwarded.

[0092] In some possible examples, the low-latency data transmission and reception method provided by the present disclosure may also include: obtaining a received message of a first length; aligning the message header and the received message according to the position information in the message header of the received message to obtain a received message of a second length; the second length is greater than the first length; performing descrambling processing on the received message of the second length to obtain a data block type; obtaining and forwarding the message payload of the received message according to the data block type. Figure 1 The synchronization module 12, the first conversion module 13 and the descrambling module 14 of the low-latency transceiver cooperate to complete the conversion and descrambling operation of the received message length, and finally obtain the message payload of the received message. In this way, the PCS layer in this example does not need to set the BUFFER to reduce the latency.

[0093] It should be noted that a low-latency data transceiver method provided in the present disclosure has been described in the description of the working process of the low-latency transceiver, and can be specifically combined with the content of the low-latency transceiver embodiment.

[0094] Based on the above-mentioned data low-latency transceiver method, the embodiment of the present disclosure further provides a data low-latency transceiver device, which is applicable to a low-latency transceiver, including:

[0095] A detection sequence acquisition module, used to parse the received message in a Pipeline manner at the MAC layer of the low-latency transceiver to obtain a frame detection sequence of the received message;

[0096] The update message acquisition module is used to update the frame detection sequence of the received message to a target sequence in response to the inconsistency between the frame detection sequence and the check sequence, and forward the updated received message; the target sequence and the check sequence have different values ​​for at least one bit.

[0097] In some possible examples, the device further includes:

[0098] The update message forwarding module is used to perform logical processing on the updated received message and then send it to the opposite end device, and the opposite end device discards the updated received message when detecting the target sequence in the received message.

[0099] In some possible examples, the device further includes:

[0100] The coded message acquisition module is used to process the transmitted message in a Pipeline manner at the MAC layer of the low-latency transceiver, and add a preset control code to the transmitted message during the Pipeline manner processing to obtain the coded transmitted message.

[0101] In some possible examples, the device further includes:

[0102] A message transmission acquisition module, used for scrambling the coded message transmission to obtain a message transmission of a second length;

[0103] A sending message conversion module, used for performing length conversion on the sending message of the second length to obtain a sending message of the first length;

[0104] The sending message processing module is used to perform logical processing on the sending message of the first length to obtain the receiving message to be forwarded.

[0105] In some possible examples, the device further includes:

[0106] A received message acquisition module, used to acquire a received message of a first length;

[0107] A received message alignment module, used to align the message header and the received message according to the position information in the message header of the received message, so as to obtain a received message of a second length; the second length is greater than the first length;

[0108] A received message scrambling module, used for performing a descrambling process on the received message of the second length to obtain a data block type;

[0109] A message payload forwarding module is used to obtain and forward the message payload of the received message according to the data block type.

[0110] It should be noted that the low-latency data transceiver device provided in this embodiment matches the above-mentioned low-latency data transceiver method. For details, please refer to the solution content of the low-latency data transceiver method and the low-latency transceiver, which will not be repeated here.

[0111] In an exemplary embodiment, there is also provided a network device, comprising a processor and a memory;

[0112] The memory is used to store a computer program executable by the processor;

[0113] The processor is configured to execute the computer program in the memory to implement the above method.

[0114] In an exemplary embodiment, a non-transitory computer-readable storage medium is also provided. When an executable computer program in the storage medium is executed by a processor, the above method can be implemented.

[0115] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the disclosed scheme. The present disclosure is intended to cover any variations, uses or adaptations that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The description and examples are to be regarded as exemplary only, and the true scope of the present disclosure is indicated by the claims.

[0116] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A method for transmitting and receiving data with low latency, characterized in that: Applicable to a low-latency transceiver, the method comprises: The MAC layer of the low-latency transceiver uses a pipeline method to parse the received message to obtain a frame detection sequence of the received message; In response to the frame detection sequence being inconsistent with the check sequence, the frame detection sequence of the received message is updated to a target sequence, and the updated received message is forwarded; the target sequence and the check sequence have different values ​​for at least one bit.

2. The method according to claim 1, characterized in that The method further comprises: The updated received message is logically processed and then sent to the opposite device. The opposite device discards the updated received message when detecting the target sequence in the received message.

3. The method according to claim 1, characterized in that The method further comprises: The MAC layer of the low-latency transceiver processes the transmission message in a Pipeline manner, and adds a preset control code to the transmission message during the Pipeline manner processing to obtain the coded transmission message.

4. The method according to claim 3, characterized in that The method further comprises: Scrambling the coded transmission message to obtain a transmission message of a second length; Performing length conversion on the sending message of the second length to obtain a sending message of the first length; The sending message of the first length is logically processed to obtain a receiving message to be forwarded.

5. The method according to claim 1, characterized in that The method further comprises: Obtaining a received message of a first length; Aligning the message header and the received message according to the position information in the message header of the received message to obtain a received message of a second length; the second length is greater than the first length; Performing descrambling processing on the received message of the second length to obtain a data block type; The message payload of the received message is acquired and forwarded according to the data block type.

6. A low-latency data transceiver device, characterized in that: The device comprises: A detection sequence acquisition module, used to parse the received message in a Pipeline manner at the MAC layer of the low-latency transceiver to obtain a frame detection sequence of the received message; The update message acquisition module is used to update the frame detection sequence of the received message to a target sequence in response to the inconsistency between the frame detection sequence and the check sequence, and forward the updated received message; the target sequence and the check sequence have different values ​​for at least one bit.

7. The device according to claim 6, characterized in that The device also includes: The update message forwarding module is used to perform logical processing on the updated received message and then send it to the opposite end device, and the opposite end device discards the updated received message when detecting the target sequence in the received message.

8. The device according to claim 6, characterized in that The device also includes: The coded message acquisition module is used to process the sent message in a Pipeline manner at the MAC layer of the low-latency transceiver, and add a preset control code to the sent message during the Pipeline manner processing to obtain the coded sent message.

9. The device according to claim 8, characterized in that The device also includes: A message transmission acquisition module, used for scrambling the coded message transmission to obtain a message transmission of a second length; A sending message conversion module, used for performing length conversion on the sending message of the second length to obtain a sending message of the first length; The sending message processing module is used to perform logical processing on the sending message of the first length to obtain the receiving message to be forwarded.

10. The device according to claim 6, characterized in that The device also includes: A received message acquisition module, used to acquire a received message of a first length; A received message alignment module, used to align the message header and the received message according to the position information in the message header of the received message, so as to obtain a received message of a second length; the second length is greater than the first length; A received message scrambling module, used for performing a descrambling process on the received message of the second length to obtain a data block type; A message payload forwarding module is used to obtain and forward the message payload of the received message according to the data block type.

11. A network device, characterized in that: include: Processor and memory; The memory is used to store a computer program executable by the processor; The processor is configured to execute the computer program in the memory to implement the method according to any one of claims 1 to 5.

12. A non-transitory computer-readable storage medium, characterized in that: When the executable computer program in the storage medium is executed by a processor, the method according to any one of claims 1 to 5 can be implemented.

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