Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem that the semiconductor structure is easy to break. The semiconductor structure comprises a substrate; the first isolation layer is arranged on the substrate and is provided with an isolation hole penetrating through the first isolation layer; the first conductive structure is arranged in the isolation hole and comprises a first part and a second part, the bottom of the isolation hole is filled with the first part, the second part is located on the first part, and a gap exists between at least part of the peripheral surface of the second part and the inner wall of the isolation hole; the second conductive structure at least filled in the gap ensures the contact between the second conductive structure and the first conductive structure, and avoids the open circuit between the second conductive structure and the first conductive structure, thereby avoiding the open circuit of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Dynamic random access memory (DRAM) is a semiconductor structure commonly used in computers and other electronic devices. It consists of multiple storage units, each of which usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line (WL), the source is electrically connected to the bit line (BL), and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor.

[0003] The capacitor and the drain are often electrically connected via a contact structure, which is prone to short circuits, resulting in poor performance of the semiconductor structure. Summary of the invention

[0004] In view of the above problems, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, so as to reduce short circuits in the semiconductor structure.

[0005] According to some embodiments, a first aspect of the present disclosure provides a semiconductor structure comprising:

[0006] substrate;

[0007] A first isolation layer disposed on the substrate, wherein the first isolation layer has an isolation hole penetrating the first isolation layer;

[0008] A first conductive structure is disposed in the isolation hole, the first conductive structure comprising a first portion filled in the bottom of the isolation hole, and a second portion located on the first portion, and a gap exists between at least a portion of an outer peripheral surface of the second portion and an inner wall of the isolation hole;

[0009] A second conductive structure is at least filled in the gap.

[0010] In some possible embodiments, a portion of the outer circumference of the second part is in corresponding contact with a portion of the inner wall of the isolation hole, and the remaining outer circumference of the second part and the remaining inner wall of the isolation hole enclose the gap.

[0011] In some possible embodiments, taking a plane parallel to the surface of the substrate as a cross section, the cross-sectional shape of the first portion is a quadrilateral, the cross-sectional shape of the second portion is a triangle, and two sides of the triangle coincide with two sides of the quadrilateral.

[0012] In some possible embodiments, the orthographic projection of the first portion on the substrate covers the orthographic projection of the second portion on the substrate.

[0013] In some possible embodiments, the substrate includes a plurality of active regions arranged at intervals, and both ends of the active regions are first contact regions;

[0014] There are a plurality of isolation holes, which are arranged at intervals along the first direction and along the second direction, each of the isolation holes correspondingly exposes one of the first contact areas, and the first direction intersects with the second direction.

[0015] In some possible embodiments, along the first direction or along the second direction, the second portions of two adjacent first conductive structures are distributed in a centrally symmetrical manner.

[0016] In some possible embodiments, there are a plurality of the second conductive structures, the plurality of the second conductive structures correspond one-to-one to the plurality of the gaps, and each of the second conductive structures includes:

[0017] a first layer filled in the gap, wherein a top surface of the first layer is flush with a top surface of the first isolation layer;

[0018] A second layer is located on the first isolation layer, the second portion, and the first layer.

[0019] In some possible embodiments, the semiconductor structure further includes a second isolation layer, wherein the second isolation layer is disposed on the first isolation layer and filled between adjacent second layers.

[0020] In some possible embodiments, the second part includes a conductive column located on the first part, and a protective layer covering a top surface of the conductive column, the top surface of the protective layer is flush with a top surface of the first isolation layer, and the conductive column and the first part are an integral structure.

[0021] The semiconductor structure provided by the embodiments of the present disclosure has at least the following advantages:

[0022] In the semiconductor structure provided by the embodiment of the present disclosure, the first isolation layer has an isolation hole that penetrates the first isolation layer, and a first conductive structure is arranged in the isolation hole. The first conductive structure includes a first part filled at the bottom of the isolation hole, and a second part located on the first part, and there is a gap between at least part of the outer peripheral surface of the second part and the inner wall of the isolation hole, and the second conductive structure is at least filled in the gap. The second conductive structure contacts part of the top surface of the first part of the first conductive structure and contacts part of the side surface of the second part. On the one hand, the contact between the second conductive structure and the first conductive structure can be ensured to avoid a circuit break between the second conductive structure and the first conductive structure. On the other hand, the contact resistance between the second conductive structure and the first conductive structure can be reduced, thereby improving the signal transmission speed of the semiconductor structure. In addition, the contact area between the first conductive structure and the second part can be increased by increasing the depth of the gap, so as to achieve a reduction in the contact resistance between the first conductive structure and the second conductive structure.

[0023] According to some embodiments, a second aspect of the present disclosure provides a method for manufacturing a semiconductor structure, comprising: forming a first isolation layer on a substrate, wherein the first isolation layer has an isolation hole penetrating the first isolation layer;

[0024] forming a first conductive structure in the isolation hole, wherein the first conductive structure comprises a first portion filled at the bottom of the isolation hole, and a second portion located on the first portion, and a gap exists between at least a portion of an outer peripheral surface of the second portion and an inner wall of the isolation hole;

[0025] A second conductive structure is formed to fill at least the gap.

[0026] In some possible embodiments, forming a first isolation layer on a substrate, wherein the first isolation layer has an isolation hole penetrating the first isolation layer, includes:

[0027] Providing a substrate, the substrate comprising a plurality of active regions arranged at intervals, both ends of the active regions being first contact regions;

[0028] forming a first isolation layer on the substrate;

[0029] The first isolation layer is etched to form a plurality of isolation holes penetrating the first isolation layer and extending to the substrate, wherein the plurality of isolation holes are arranged at intervals along the first direction and arranged at intervals along the second direction, each of the isolation holes correspondingly exposes one of the first contact areas, and the first direction intersects with the second direction.

[0030] In some possible embodiments, forming a first conductive structure in the isolation hole includes:

[0031] forming a first conductive layer in the isolation hole and on the first isolation layer, wherein the first conductive layer completely fills the isolation hole and covers a top surface of the first isolation layer;

[0032] forming a first dielectric layer, a second conductive layer and a first mask layer stacked in sequence on the first conductive layer;

[0033] Removing a portion of the first mask layer to form a plurality of first bosses spaced apart along the first direction and spaced apart along a third direction, wherein an orthographic projection of each of the first bosses on the substrate partially overlaps with two adjacent isolation holes along the first direction, and each isolation hole partially overlaps with an orthographic projection of one of the first bosses on the substrate, and the third direction intersects both the first direction and the second direction;

[0034] Using the remaining first mask layer as a mask, etching the second conductive layer, the first dielectric layer and the first conductive layer, the first conductive layer located on the first isolation layer forms a plurality of second bosses arranged at intervals, and the first conductive layer located in the isolation hole and exposed outside the second bosses forms an initial gap;

[0035] A plurality of the second bosses on the first isolation layer are removed by etching, and a portion of the first conductive layer is removed by etching along the initial gap to form the gap, and the remaining first conductive layer forms the first conductive structure.

[0036] In some possible embodiments, the second conductive layer, the first dielectric layer, and the first conductive layer are etched using the remaining first mask layer as a mask, so that the first conductive layer located on the first isolation layer forms a plurality of second bosses, and the first conductive layer located in the isolation hole and exposed outside the second bosses forms an initial gap, including:

[0037] Using the remaining first mask layer as a mask, etching and removing a portion of the second conductive layer and a portion of the first dielectric layer to form a plurality of third bosses arranged at intervals, wherein the first conductive layer is exposed between the plurality of third bosses;

[0038] removing the remaining first mask layer to expose the third boss;

[0039] Etching and removing the second conductive layer of the third bosses and the first conductive layer exposed between the third bosses, exposing the first dielectric layer of the third bosses, and forming the second bosses and the initial gap;

[0040] The first dielectric layer of the third boss is removed.

[0041] In some possible embodiments, a portion of the first mask layer is removed to form a plurality of first bosses spaced apart along the first direction and spaced apart along the third direction, including:

[0042] forming a second dielectric layer on the first mask layer, and forming a third isolation layer on the second dielectric layer, wherein the third isolation layer has a plurality of first grooves extending along a first direction and spaced apart along the second direction, the first grooves exposing the second dielectric layer and being opposite to the isolation holes located in the same column along the first direction;

[0043] forming a third dielectric layer, a first intermediate layer and a fourth isolation layer, wherein the third dielectric layer fills the first trench, the first intermediate layer covers the third dielectric layer and the third isolation layer, and the fourth isolation layer covers the first intermediate layer;

[0044] Etching and removing a portion of the fourth isolation layer and a portion of the first intermediate layer to form a plurality of second grooves extending along the third direction and arranged at intervals, wherein the second grooves expose the third dielectric layer and the third isolation layer;

[0045] Etching away the remaining fourth isolation layer and the third isolation layer exposed in the second trench, forming a plurality of first etching holes spaced apart along the third direction at the bottom of the second trench, wherein the first etching holes expose the second dielectric layer;

[0046] Etching and removing the second dielectric layer exposed in the first etching hole and the third dielectric layer exposed in the second groove, wherein the first etching hole exposes the first mask layer, and the second groove exposes the second dielectric layer;

[0047] removing the remaining first intermediate layer to expose the third dielectric layer and the third isolation layer between adjacent second trenches;

[0048] Etching away the remaining third isolation layer, and etching the first mask layer along the first etching hole, wherein the first etching hole extends into the first mask layer, and the remaining third dielectric layer forms a third boss;

[0049] Etching away at least a portion of the third dielectric layer and the exposed second dielectric layer, and etching the first mask layer along the first etching hole, wherein the first etching hole penetrates the first mask layer, and the remaining second dielectric layer forms a fourth boss;

[0050] The first mask layer exposed between the fourth protrusions is removed, so that the remaining first mask layer forms the first protrusions.

[0051] In some possible embodiments, forming a second conductive structure at least filling the gap includes:

[0052] forming a first layer in the gap, wherein the first layer fills the gap;

[0053] Converting a portion of the first conductive structure away from the substrate into a protective layer, wherein the bottom surface of the protective layer is higher than the bottom surface of the first layer;

[0054] forming an initial layer on the first isolation layer, the first layer and the protective layer, and forming a first stacked structure and a transfer layer stacked on the initial layer;

[0055] removing a portion of the transfer layer to form first grooves extending along the first direction and spaced apart along the second direction, wherein the first grooves expose the first stacked structure;

[0056] forming a second stacked structure in the first groove and on the transfer layer;

[0057] removing a portion of the second stacked structure to form second grooves extending along a fourth direction and spaced apart along the second direction, wherein the second grooves expose the transfer layer, and the fourth direction intersects the first direction, the second direction, and the third direction;

[0058] removing the transfer layer exposed in the second groove, so that the transfer layer forms a plurality of fifth bosses arranged at intervals along the first direction and arranged at intervals along the fourth direction;

[0059] removing the second stacked structure and the first stacked structure exposed between the fifth bosses, so that the first stacked structure forms a plurality of sixth bosses arranged at intervals;

[0060] The initial layer exposed between the sixth bosses is removed to form a plurality of second layers arranged at intervals, the plurality of second layers are in corresponding contact with the plurality of first layers, and the second layers and the first layers form a second conductive structure

[0061] The method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure has at least the following advantages:

[0062] The method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure forms a filling hole in the first isolation layer, forms a first conductive structure in the filling hole, a gap exists between the part of the first conductive structure away from the bottom of the filling hole and the inner wall of the isolation hole, and fills the second conductive structure at least in the gap to ensure that the second conductive structure is in contact with the first conductive structure, and avoids a short circuit between the second conductive structure and the first conductive structure. The contact area between the second conductive structure and the first conductive structure is large, which can reduce the contact resistance between the second conductive structure and the first conductive structure. In addition, the contact area between the first conductive structure and the second part can be increased by increasing the depth of the gap, so as to reduce the contact resistance between the first conductive structure and the second conductive structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 A schematic diagram of the relative positions of the first conductive structure and the second conductive structure in the related art;

[0064] Figure 2 is a three-dimensional schematic diagram of a semiconductor structure in an embodiment of the present disclosure;

[0065] Figure 3 is a schematic structural diagram of a semiconductor structure in an embodiment of the present disclosure;

[0066] Figure 4 A schematic diagram of the relative positions of the active area, the bit line and the word line in one embodiment of the present disclosure;

[0067] Figure 5 is a schematic structural diagram of an isolation hole in an embodiment of the present disclosure;

[0068] Figure 6 is a schematic diagram of the bottom of the isolation hole in one embodiment of the present disclosure;

[0069] Figure 7 is a schematic diagram of a gap in an embodiment of the present disclosure;

[0070] Figure 8 is a flow chart of a method for manufacturing a semiconductor structure in an embodiment of the present disclosure;

[0071] Fig. 9 is a schematic diagram of a structure after forming a first conductive material in an embodiment of the present disclosure;

[0072] Fig.10 is a schematic diagram of a structure after a first conductive layer is formed in an embodiment of the present disclosure;

[0073] Fig.11 is a schematic diagram of a structure after forming a first mask layer in an embodiment of the present disclosure;

[0074] Fig.12It is a schematic diagram of the structure after the first boss is formed in one embodiment of the present disclosure;

[0075] Fig.13 It is a schematic diagram of the structure after a part of the first boss is removed in one embodiment of the present disclosure;

[0076] Fig.14 for Fig.13 A top view of

[0077] Fig.15 It is a schematic diagram of the structure after a portion of the second conductive layer is removed in one embodiment of the present disclosure;

[0078] Fig.16 It is a schematic diagram of the structure after a portion of the first dielectric layer is removed in one embodiment of the present disclosure;

[0079] Fig.17 It is a schematic diagram of the structure after a portion of the first conductive layer is removed in one embodiment of the present disclosure;

[0080] Fig.18 It is a schematic diagram of the structure after removing the remaining first dielectric layer in one embodiment of the present disclosure;

[0081] Fig.19 for Fig.18 A top view of

[0082] Fig. 20 for Fig.18 Schematic diagram of the cross section at EE;

[0083] Fig.21 is a schematic diagram of a structure after a gap is formed in an embodiment of the present disclosure;

[0084] Fig. 22 is a top view after a gap is formed in one embodiment of the present disclosure;

[0085] Fig.23 is a manufacturing flow chart of forming an intermediate groove in one embodiment of the present disclosure;

[0086] Fig.24 is a manufacturing flow chart of forming a third isolation layer in one embodiment of the present disclosure;

[0087] Fig.25 is a schematic diagram of a structure after a first groove is formed in an embodiment of the present disclosure;

[0088] Fig.26 It is a three-dimensional schematic diagram after forming a first groove in one embodiment of the present disclosure;

[0089] Fig. 27 is a schematic diagram of a structure after forming a third dielectric layer in an embodiment of the present disclosure;

[0090] Fig.28 It is a three-dimensional schematic diagram after forming a second photoresist layer in one embodiment of the present disclosure;

[0091] Fig.29 A top view after forming a second preset pattern in one embodiment of the present disclosure;

[0092] Fig.30 is a top view after forming a second groove in one embodiment of the present disclosure;

[0093] Fig.31 for Fig.30 Sectional view at AA in the middle;

[0094] Fig.32 is a top view after forming a first etching hole in one embodiment of the present disclosure;

[0095] Fig.33 and Fig.34 They are Fig.32 Cross-sectional views at BB and CC;

[0096] Fig.35 It is a top view after a portion of the second dielectric layer is removed in one embodiment of the present disclosure;

[0097] Fig.36 and Fig.37 They are Fig.35 Cross-sectional views at BB and CC;

[0098] Fig.38 It is a three-dimensional schematic diagram after removing the remaining first intermediate layer in one embodiment of the present disclosure;

[0099] Fig.39 and Fig.40 and Fig.41 They are Fig.38 Cross-sectional views at BB, CC and DD;

[0100] Fig.42 It is a top view after a portion of the first mask layer and the third isolation layer are removed in one embodiment of the present disclosure;

[0101] Fig.43 and Fig.44 They are Fig.42 Cross-sectional views at BB and CC;

[0102] Fig.45 It is a top view after removing the third dielectric layer in one embodiment of the present disclosure;

[0103] Fig.46 and Fig.47 They are Fig.45 Cross-sectional views at BB and CC;

[0104] Fig.48 It is a top view after a portion of the fifth isolation layer is removed in one embodiment of the present disclosure;

[0105] Fig.49 and Fig.50 They are Fig.48 Cross-sectional views at BB and CC;

[0106] Fig.51 It is a schematic diagram of the structure after the first layer is formed in one embodiment of the present disclosure;

[0107] Fig.52 It is a schematic diagram of a structure after a portion of the first layer is removed in an embodiment of the present disclosure;

[0108] Fig.53 It is a schematic diagram of the structure after forming a transfer layer in one embodiment of the present disclosure;

[0109] Fig.54 It is a schematic diagram of the structure after the first groove is formed in one embodiment of the present disclosure;

[0110] Fig.55 is a top view after the first groove is formed in one embodiment of the present disclosure;

[0111] Fig.56 is a flowchart of manufacturing a mask of a second groove in one embodiment of the present disclosure;

[0112] Fig.57 is a top view of a mask of a second groove in an embodiment of the present disclosure;

[0113] Fig.58 It is a schematic diagram of forming a second layer in one embodiment of the present disclosure.

[0114] Description of reference numerals:

[0115] 10-substrate; 11-active area; 12-word line; 13-shallow trench isolation structure; 20-first isolation layer; 21-isolation hole; 22-bit line; 23-first contact area; 30-first conductive structure; 31-first conductive material; 32-first conductive layer; 33-initial gap; 34-gap; 35-protective layer; 40-second conductive structure; 41-first layer; 42-initial layer; 43-second layer; 44-diffusion barrier layer; 50-second isolation layer; 61-first dielectric layer; 62-second conductive layer; 63-first mask layer; 64-fourth dielectric layer; 65 -fifth isolation layer; 71-second dielectric layer; 72-third isolation layer; 73-first groove; 74-second intermediate layer; 75-sixth isolation layer; 76-first photoresist layer; 77-intermediate groove; 78-side wall layer; 81-third dielectric layer; 82-first intermediate layer; 83-fourth isolation layer; 84-second photoresist layer; 85-second groove; 86-first etching hole; 91-first stacking structure; 92-third intermediate layer; 93-seventh isolation layer; 94-transfer layer; 95-first groove; 96-second stacking structure; 97-fourth intermediate layer; 98-eighth isolation layer. DETAILED DESCRIPTION

[0116] The semiconductor structure in the related art is prone to short circuit. The inventor has found that the reason is: Figure 1 , the contact structure includes a first conductive structure 30 and a second conductive structure 40 in contact with each other, the first conductive structure 30 is filled in the isolation hole of the first isolation layer 20 and in contact with the substrate, and the second conductive structure 40 is located above the first conductive structure 30 and in contact with the first conductive structure 30. The bottom surface of the second conductive structure 40 is in contact with the top surface of the first conductive structure 30, that is, the second conductive structure 40 and the first conductive structure 30 are stacked up and down. When the second conductive structure 40 is manufactured, there is a deviation between the second conductive structure 40 and the first conductive structure 30, the actual contact area between the second conductive structure 40 and the first conductive structure 30 is reduced, the contact resistance between the second conductive structure 40 and the first conductive structure 30 is increased, and even a circuit is broken.

[0117] To this end, the embodiment of the present disclosure provides a semiconductor structure, wherein the first conductive structure includes a first portion filled at the bottom of the isolation hole, and a second portion located on the first portion, and there is a gap between at least part of the outer peripheral surface of the second portion and the inner wall of the isolation hole, and the second conductive structure is at least filled in the gap to ensure contact between the second conductive structure and the first conductive structure, and to avoid a circuit break between the second conductive structure and the first conductive structure. The contact area between the second conductive structure and the first conductive structure is large, which can reduce the contact resistance, and the contact area between the first conductive structure and the second portion can be increased by increasing the depth of the gap, so as to reduce the contact resistance between the first conductive structure and the second conductive structure.

[0118] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0119] See also Figure 2 and Figure 3 The present disclosure provides a semiconductor structure, which includes a substrate 10, a first isolation layer 20, a first conductive structure 30, and a second conductive structure 40. The substrate 10 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a germanium-arsenic substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0120] like Figures 2 to 4 As shown, the substrate 10 includes a plurality of active regions 11 spaced apart from each other, and both ends of the active regions 11 are first contact regions 23, and the first contact regions 23 are used to connect capacitors. Figure 4 The Y direction is shown) and is arranged at intervals along the second direction (as shown Figure 4 The first direction and the second direction are intersecting, for example, perpendicular to each other. The extension direction of each active region 11 (as shown in the X direction) is arranged at intervals. Figure 4 The M direction) intersects both the first direction and the second direction.

[0121] The substrate 10 further includes a shallow trench isolation (STI) structure 13 disposed between the plurality of active regions 11 to fill the gaps between the plurality of active regions 11 and ensure that the active regions 11 are insulated. The substrate 10 further includes a plurality of word lines 12 disposed at intervals and extending along the second direction, the word lines 12 passing through the active regions 11 and being insulated and isolated from the active regions 11. The depths of the word line trenches corresponding to the word lines 12 are different, such as Figures 2 to 4 As shown, the depth of the part of the word line 12 opposite to the active area 11 is smaller, and the depth of the part of the word line located between the active areas 11 is larger, that is, the depth of the word line trench located in the shallow trench isolation structure 13 is greater than the depth of the word line trench located in the active area 11. Figure 4 As shown, each active region 11 corresponds to two word lines 12 , so that each active region 11 is divided into three parts, and the parts located at the two ends correspond to a first contact region 23 .

[0122] See also Figure 5 , a first isolation layer 20 is disposed on the substrate 10, and has an isolation hole 21 penetrating the first isolation layer 20, so that the isolation layer exposes the substrate 10. The material of the first isolation layer 20 may include silicon nitride, silicon oxynitride, or silicon nitride carbide, etc. In some examples, the isolation hole 21 also extends into the substrate 10. On the one hand, it can remove the oxide existing on the substrate 10 to ensure the exposure of the substrate 10, especially the active area 11, and on the other hand, it can increase the area of ​​the substrate 10 exposed by the isolation hole 21. The bottom surface of the isolation hole 21 can be a curved surface to further increase the exposed area in the isolation hole 21. For example, the bottom surface of the isolation hole 21 is a hemispherical surface, a hemispherical surface, or a curved surface (see Figure 6 )wait.

[0123] In the example where the substrate 10 includes a plurality of active areas 11 arranged at intervals, and both ends of the active areas 11 are first contact areas 23, there may be a plurality of isolation holes 21. The plurality of isolation holes 21 are arranged at intervals along the first direction and arranged at intervals along the second direction, and each isolation hole 21 exposes a corresponding first contact area 23, that is, the plurality of isolation holes 21 correspond to the plurality of first contact areas 23, that is, each active area 11 corresponds to two isolation holes 21. Among them, a plurality of bit lines 22 arranged at intervals and extending along the first direction are also arranged in the first isolation layer 20. The isolation hole 21 is provided between every two adjacent bit lines 22, and the bit line 22 is spaced from the isolation hole 21, that is, the bit line 22 is not exposed in the isolation hole 21. The bit line 22 contacts the active area 11, and specifically, the bit line 22 contacts the middle of the active area 11.

[0124] Continue reading Figure 2 and Figure 3 , the first conductive structure 30 is disposed in the isolation hole 21, and the first conductive structure 30 includes a first portion filled in the bottom of the isolation hole 21, and a second portion located on the first portion. The first portion is in contact with the substrate 10, for example, the first portion is in contact with the first contact area 23, and the second portion is located on a side of the first portion away from the substrate 10. In some examples, the orthographic projection of the first portion on the substrate 10 covers the orthographic projection of the second portion on the substrate 10, so that the second portion is located directly above the first portion, and the cross-sectional size of the second portion is smaller than the cross-sectional size of the first portion, taking the plane perpendicular to the stacking direction of the first portion and the second portion as the cross section, so as to facilitate the formation of the second portion.

[0125] There is a gap 34 between at least part of the outer circumference of the second part and the inner wall of the isolation hole 21, that is, the outer circumference of the second part is not completely in contact with the inner wall of the isolation hole 21. For example, the outer circumference of the second part does not contact the inner wall of the isolation hole 21 at all, or part of the outer circumference of the second part contacts the inner wall of the isolation hole 21, and the rest of the outer circumference does not contact the inner wall of the isolation hole 21. The first part is exposed between the second part and the isolation hole 21. In this configuration, the top surface of the second part is exposed, the top surface of the first part not covered by the second part is exposed, and at least part of the outer circumference of the second part is exposed, so that the exposed surface area of ​​the first conductive structure 30 is larger.

[0126] For some examples, see Figure 7 , part of the outer circumference of the second part contacts part of the inner wall of the isolation hole 21, and the remaining outer circumference of the second part and the remaining inner wall of the isolation hole 21 enclose a gap 34. The top surface of the second part can be flush with the top surface of the first isolation layer 20, the outer circumference of the second part is the side surface of the second part, the bottom surface of the second part contacts the top surface of the first part, part of the side surface of the second part contacts the isolation hole 21, and the remaining side surfaces of the second part and the top surface of the second part are exposed.

[0127] Among them, taking the plane parallel to the surface of the substrate 10 as the cross section, the cross-sectional shape of the first part is a quadrilateral, and the cross-sectional shape of the second part is a triangle, and the two sides of the triangle coincide with the two sides of the quadrilateral. For example, the first part is a quadrangular prism, and the second part is a triangular prism, and the two adjacent cylindrical surfaces of the triangular prism are respectively aligned with the two adjacent cylindrical surfaces of the quadrangular prism, and the other cylindrical surface of the triangular prism is aligned with a diagonal surface of the quadrangular prism. In this way, the second part is easy to form, and the area of ​​the exposed cylindrical surface is larger.

[0128] like Figure 2 As shown, along the first direction or along the second direction, the second parts of two adjacent first conductive structures 30 are centrally symmetrically distributed. For example, along the first direction, the second parts of two adjacent first conductive structures 30 are centrally symmetrically distributed, and along the second direction, the second parts of two adjacent first conductive structures 30 are centrally symmetrically distributed. The plurality of first conductive structures 30 are arranged in an array, and the first conductive structures 30 located in the diagonal direction of the array are the same.

[0129] In some examples, the second portion includes a conductive column located on the first portion, and a protective layer 35 covering the top surface of the conductive column. The top surface of the protective layer 35 is flush with the top surface of the first isolation layer 20, and the shape of the protective layer 35 is the same as that of the conductive column, and is located directly above the conductive column to isolate and protect the conductive column to prevent the material in the subsequent manufacturing process from penetrating the conductive column, so as to ensure the conductive performance of the conductive column.

[0130] The conductive column and the first part can be an integrated structure to reduce the separation of the conductive column and the second part. The conductive column and the second part can be made of polysilicon, and the protective layer 35 can be made of silicon oxide, so that the protective layer 35 can be obtained by oxidation, which is convenient for forming the protective layer 35. For example, the protective layer 35 is formed by thermal oxidation (full name of Rapid Thermal Oxidation, English abbreviation RTO)

[0131] The second conductive structure 40 is at least filled in the gap 34, and the gap 34 is fully filled, and the second conductive structure 40 is in contact with the first conductive structure 30. By filling the gap 34 with the second conductive structure 40, the second conductive structure 40 is in contact with a portion of the top surface of the first part of the first conductive structure 30, and is in contact with a portion of the side surface of the second part. In this way, on the one hand, the contact between the second conductive structure 40 and the first conductive structure 30 can be ensured, and the isolation between the second conductive structure 40 and other structures can be ensured, thereby reducing the short circuit or open circuit of the semiconductor structure. On the other hand, the contact area between the second conductive structure 40 and the first conductive structure 30 can be increased, the contact resistance between the second conductive structure 40 and the first conductive structure 30 can be reduced, and the signal transmission speed of the semiconductor structure can be improved. In addition, by increasing the depth of the gap 34, the contact area between the first conductive structure 30 and the second part can be increased, so as to achieve the reduction of the contact resistance between the first conductive structure 30 and the second conductive structure 40.

[0132] In some examples, there are multiple second conductive structures 40, and the multiple second conductive structures 40 correspond to the multiple gaps 34 one by one. The second conductive structures 40 fill the gaps 34 and also extend above the first isolation layer 20 and the first conductive structure 30, that is, each second conductive structure 40 includes a first layer 41 and a second layer 43, the first layer 41 fills the gap 34, and the top surface of the first layer 41 is flush with the top surface of the first isolation layer 20. The second layer 43 is located on the first isolation layer 20, the second portion and the first layer 41. Figure 3 , the first layer 41 includes a core layer and a diffusion barrier layer 44. The material of the diffusion barrier layer 44 can be titanium nitride, etc. The material of the core layer can be the same as the material of the second layer 43, for example, including tungsten or tungsten alloy, so that the core layer and the second layer 43 form an integral body. The diffusion barrier layer 44 is coated on the side and bottom of the core layer, that is, the diffusion barrier layer 44 is located between the core layer and the first conductive structure 30, and between the core layer and the first isolation layer 20, to prevent ions (such as metal) in the core layer from diffusing into the first conductive structure 30 and the first isolation layer 20. In order to represent other structures, except Figure 3 In addition, the diffusion barrier layer 44 is not shown in other figures.

[0133] In order to ensure the insulation performance between the multiple second conductive structures 40, the semiconductor structure also includes a second isolation layer 50, which is arranged on the first isolation layer 20 and filled between adjacent second layers 43. The second isolation layer 50 isolates and supports the second layers 43. The material of the second isolation layer 50 can be silicon nitride, silicon oxynitride or silicon carbide. Among them, the material of the second isolation layer 50 can be the same as that of the first isolation layer 20, so that the second isolation layer 50 and the first isolation layer 20 are integrated to reduce the interlayer separation between the second isolation layer 50 and the first isolation layer 20.

[0134] In summary, in the embodiment of the present application, the first isolation layer 20 has an isolation hole 21 that penetrates the first isolation layer 20, and a first conductive structure 30 is arranged in the isolation hole 21. The first conductive structure 30 includes a first part filled at the bottom of the isolation hole 21, and a second part located on the first part, and there is a gap 34 between at least part of the outer peripheral surface of the second part and the inner wall of the isolation hole 21, and the second conductive structure 40 is at least filled in the gap 34. The second conductive structure 40 contacts the part of the top surface of the first part of the first conductive structure 30, and contacts the part of the side surface of the second part. On the one hand, the contact between the second conductive structure 40 and the first conductive structure 30 can be ensured to avoid the disconnection between the second conductive structure 40 and the first conductive structure 30. On the other hand, the contact resistance between the second conductive structure 40 and the first conductive structure 30 can be reduced, and the signal transmission speed of the semiconductor structure can be improved. In addition, by increasing the depth of the gap 34, the contact area between the first conductive structure 30 and the second part can be increased, so as to achieve the reduction of the contact resistance between the first conductive structure 30 and the second conductive structure 40.

[0135] The present application also provides a method for manufacturing a semiconductor structure. Figure 8 , the preparation method specifically comprises the following steps:

[0136] Step S100: forming a first isolation layer on a substrate, wherein the first isolation layer has an isolation hole penetrating the first isolation layer.

[0137] See also Figures 4 to 6 , the substrate 10 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a germanium-arsenic substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate. The first isolation layer 20 covers the substrate 10, and has an isolation hole 21 penetrating the first isolation layer 20, and the isolation hole 21 exposes the substrate 10. The material of the first isolation layer 20 may include silicon nitride, silicon oxynitride, or silicon nitride carbide. In some possible implementations, forming the first isolation layer 20 on the substrate 10, the first isolation layer 20 having the isolation hole 21 penetrating the first isolation layer 20 (step S100), includes:

[0138] A substrate 10 is provided, the substrate 10 includes a plurality of active regions 11 arranged at intervals, and both ends of the active regions 11 are first contact regions 23. The substrate 10 also includes a shallow trench isolation structure 13 (see Figure 2 ) to ensure insulation isolation between the active areas 11.

[0139] A first isolation layer 20 is formed on the substrate 10. The first isolation layer 20 covers the substrate 10 and can be formed by a deposition process, such as physical vapor deposition (Physical Vapor Deposition, English abbreviation PVD), chemical vapor deposition (Chemical Vapor Deposition, English abbreviation CVD) or atomic layer deposition (Atomic Layer Deposition, English abbreviation ALD).

[0140] The first isolation layer 20 is etched to form a plurality of isolation holes 21 penetrating the first isolation layer 20 and extending to the substrate 10. The plurality of isolation holes 21 are arranged at intervals along the first direction and at intervals along the second direction. Each isolation hole 21 correspondingly exposes a first contact area 23. The first direction intersects the second direction.

[0141] The first isolation layer 20 is etched to form a plurality of isolation holes 21 arranged in an array in the first isolation layer 20. The plurality of isolation holes 21 are arranged along the first direction and along the second direction. Figure 4 Y direction) and the second direction ( Figure 4 Each isolation hole 21 exposes a first contact area 23, that is, each active area 11 corresponds to two isolation holes 21. Figure 5 As shown, the isolation hole 21 also extends into the substrate 10, that is, the bottom of the isolation hole 21 is located in the substrate 10. On the one hand, the oxide on the substrate 10 can be removed to ensure the exposure of the active area 11, and on the other hand, the area of ​​the active area 11 exposed by the isolation hole 21 can be increased. The bottom surface of the isolation hole 21 can be a curved surface to further increase the exposed area in the isolation hole 21. For example, the bottom surface of the isolation hole 21 is a hemispherical surface, a hemispherical surface, or a curved surface (see Figure 6 )wait.

[0142] Step S200: forming a first conductive structure in the isolation hole, the first conductive structure comprising a first portion filling the bottom of the isolation hole, and a second portion located on the first portion, and a gap exists between at least a portion of the outer circumference of the second portion and the inner wall of the isolation hole.

[0143] See also Figure 2 , Figure 3 and Figure 7, the first conductive structure 30 is disposed in the isolation hole 21, and the first conductive structure 30 includes a first portion and a second portion, the first portion fills the bottom of the isolation hole 21 and contacts the substrate 10, and the second portion is located on a side of the first portion away from the substrate 10. In some examples, the orthographic projection of the first portion on the substrate 10 covers the orthographic projection of the second portion on the substrate 10 to ensure that the second portion is located directly above the first portion.

[0144] There is a gap 34 between at least part of the outer circumference of the second portion and the inner wall of the isolation hole 21, for example, the outer circumference of the second portion does not contact the inner wall of the isolation hole 21 at all, or part of the outer circumference of the second portion contacts the inner wall of the isolation hole 21, and the rest of the outer circumference does not contact the inner wall of the isolation hole 21. The top surface of the second portion may be flush with the top surface of the first isolation layer 20.

[0145] In some examples, the second part includes a conductive column located on the first part, and a protective layer 35 covering the top surface of the conductive column. The top surface of the protective layer 35 is flush with the top surface of the first isolation layer 20. The shape of the protective layer 35 is the same as that of the conductive column, and it is located directly above the conductive column to isolate and protect the conductive column and prevent the material in the subsequent manufacturing process from penetrating into the conductive column to ensure the conductive performance of the conductive column. The conductive column and the first part are an integral structure, which reduces the separation of the conductive column and the second part, and also facilitates the formation of the conductive column and the first part. For example, the conductive column and the first part can be formed by deposition and back etching. The material of the conductive column and the second part can both be polysilicon, and the material of the protective layer 35 can be silicon oxide, so that the protective layer 35 can be formed by oxidation treatment, which facilitates the formation of the protective layer 35.

[0146] Step S300: forming a second conductive structure at least filling the gap.

[0147] Continue reading Figure 2 , Figure 3 and Figure 7 , the second conductive structure 40 is deposited in the gap 34 so that the second conductive structure 40 at least fills the gap 34, ensuring that the second conductive structure 40 contacts the first conductive structure 30, and avoiding a circuit break between the second conductive structure 40 and the first conductive structure 30. The second conductive structure 40 contacts a portion of the top surface of the first portion of the first conductive structure 30, and contacts a portion of the side surface of the second portion, and the contact area is large, which can reduce the contact resistance between the second conductive structure 40 and the first conductive structure 30. In addition, by increasing the depth of the gap 34, the contact area between the first conductive structure 30 and the second portion can be increased, so as to reduce the contact resistance between the first conductive structure 30 and the second conductive structure 40.

[0148] The second conductive structure 40 fills the gap 34 and can also extend above the first isolation layer 20 and the first conductive structure 30, that is, each second conductive structure 40 includes a first layer 41 and a second layer 43, the first layer 41 fills the gap 34, and the top surface of the first layer 41 is flush with the top surface of the first isolation layer 20. The second layer 43 is located on the first isolation layer 20, the second portion of the first conductive structure 30 and the first layer 41. The first layer 41 includes a core layer and a diffusion barrier layer 44 (such as Figure 3 As shown in the figure, the material of the diffusion barrier layer 44 can be titanium nitride, etc., and the material of the core layer can be the same as that of the second layer 43, for example, including tungsten or tungsten alloy, so that the core layer and the second layer 43 are integrated. The diffusion barrier layer 44 is coated on the side and bottom of the core layer, that is, the diffusion barrier layer 44 is located between the core layer and the first conductive structure 30, and between the core layer and the first isolation layer 20, so as to prevent ions (such as metal) in the core layer from diffusing into the first conductive structure 30 and the first isolation layer 20. By setting the second layer 43, it is convenient to realize the external connection of the second conductive structure 40.

[0149] In summary, the method for manufacturing the semiconductor structure in the embodiment of the present application forms an isolation hole 21 in the first isolation layer 20, forms a first conductive structure 30 in the isolation hole 21, and a gap 34 exists between the portion of the first conductive structure 30 away from the bottom of the isolation hole 21 and the inner wall of the isolation hole 21, and fills the second conductive structure 40 at least in the gap 34, so as to ensure that the second conductive structure 40 is in contact with the first conductive structure 30, and avoid the circuit break between the second conductive structure 40 and the first conductive structure 30. The contact area between the second conductive structure 40 and the first conductive structure 30 is large, which can reduce the contact resistance between the second conductive structure 40 and the first conductive structure 30. In addition, the contact area between the first conductive structure 30 and the second portion can be increased by increasing the depth of the gap 34, so as to reduce the contact resistance between the first conductive structure 30 and the second conductive structure 40.

[0150] For some possible implementations, see Fig. 9 As shown in FIG. 1 , forming a first conductive structure 30 in the isolation hole 21 (step S200 ) includes the following steps:

[0151] Step S201 : forming a first conductive layer 32 in the isolation hole 21 and on the first isolation layer 20 , wherein the first conductive layer 32 completely fills the isolation hole 21 and covers the top surface of the first isolation layer 20 .

[0152] See also Fig. 9 and Fig.10The first conductive layer 32 can be formed by two depositions, wherein the first conductive material 31 is first deposited in the isolation hole 21 and etched back to expose part of the isolation hole 21. The first conductive material 31 is then deposited in the isolation hole 21 and on the first isolation layer 20, and the top surface of the first conductive material 31 is planarized to prepare for the subsequent formation of the film layer. All the first conductive materials 31 form the first conductive layer 32, which fills the isolation hole 21 and covers the top surface of the first isolation layer 20.

[0153] Since the depth and width of the isolation hole 21 are relatively large, after the first conductive material 31 is deposited in the isolation hole 21 for the first time, a gap may be formed in the first conductive material 31. The gap can be exposed by etching back, and when the first conductive material 31 is deposited for the second time, the first conductive material 31 can fill the exposed gap. The gap of the first conductive layer 32 formed by the first conductive material 31 is small, and the transmission performance is good.

[0154] Step S202 : forming a first dielectric layer 61 , a second conductive layer 62 , and a first mask layer 63 which are stacked in sequence on the first conductive layer 32 .

[0155] A first dielectric layer 61 is deposited on the first conductive layer 32, a second conductive layer 62 is deposited on the first dielectric layer 61, and a first mask layer 63 is deposited on the second conductive layer 62. The material of the first dielectric layer 61 may be an oxide, and the first mask layer 63 may be a stacked structure, including a fourth dielectric layer 64 and a fifth isolation layer 65 disposed on the fourth dielectric layer 64. The material of the fourth dielectric layer 64 may be an oxide, and the material of the fifth isolation layer 65 may be a nitride. The material of the fourth dielectric layer 64 may be the same as that of the first dielectric layer 61, so as to achieve simultaneous etching of the fourth dielectric layer 64 and the first dielectric layer 61. The material of the second conductive layer 62 may be the same as that of the first conductive layer 32, so as to achieve simultaneous etching of the second conductive layer 62 and the first conductive layer 32.

[0156] Step S203: remove part of the first mask layer 63 to form a plurality of first bosses arranged at intervals along the first direction and arranged at intervals along the third direction, wherein the orthographic projection of each first boss on the substrate 10 partially overlaps with two adjacent isolation holes 21 along the first direction, and each isolation hole 21 partially overlaps with the orthographic projection of a first boss on the substrate 10, and the third direction intersects with both the first direction and the second direction.

[0157] See also Fig.12 , Fig.13 and Fig.14 , using the second conductive layer 62 as an etching stop layer, removing part of the first mask layer 63, and the remaining first mask layer 63 forms a plurality of first bosses arranged at intervals, the first bosses extending in the first direction ( Fig.14Y direction) and arranged in a spaced manner along the third direction ( Fig.14 The third direction is arranged in a spaced manner with the first direction and the second direction ( Fig.14 Two adjacent isolation holes 21 along the first direction are opposite to one first boss, and each isolation hole 21 corresponds to only one first boss.

[0158] Among them, along the second direction, the isolation hole 21 ( Fig.14 The two ends of the isolation hole 21 (indicated by the dotted line) are aligned with the two ends of the first boss, that is, the width of the isolation hole 21 is equal to the width of the first boss, and the isolation hole 21 is directly opposite to the first boss. In some examples, the isolation hole 21 can be a rectangular column, and the first boss can be a parallelogram column. Along the first direction, the two opposite side surfaces of the first boss are arranged opposite to the diagonal surface of the rectangular column.

[0159] Step S204: Using the remaining first mask layer 63 as a mask, the second conductive layer 62, the first dielectric layer 61 and the first conductive layer 32 are etched, the first conductive layer 32 located on the first isolation layer 20 forms a plurality of second bosses arranged at intervals, and the first conductive layer 32 located in the isolation hole 21 and exposed outside the second bosses forms an initial gap 33.

[0160] See also Fig.13 , Figures 15 to 20 , using the remaining first mask layer 63 (i.e., the first boss) as a mask, the second conductive layer 62, the first dielectric layer 61, and the first conductive layer 32 are etched, and during the etching process, the first boss, the second conductive layer 62, the first dielectric layer 61, and a portion of the first conductive layer 32 are removed simultaneously by using the selection ratio. Fig.19 and Fig. 20 As shown, part of the first conductive layer 32 in the remaining isolation hole 21 and part of the first conductive layer 32 on the first isolation layer 20 remain.

[0161] See also Figures 18 to 20 The first conductive layer 32 on the first isolation layer 20 forms a plurality of second bosses, which are arranged at intervals and correspond to the plurality of first bosses. The first conductive layer 32 in the isolation hole 21 forms an initial gap 33, which is located on both sides of the second boss along the first direction. Each second boss spans the first conductive layer 32 in two adjacent isolation holes 21 along the first direction.

[0162] Step S205 : etching and removing the plurality of second protrusions on the first isolation layer 20 , and etching and removing a portion of the first conductive layer 32 along the initial gap 33 to form a gap 34 .

[0163] See also Fig. 20 , Fig.21 and Fig. 22, using the first isolation layer 20 as an etching stop layer, multiple second bosses are etched away to expose the first isolation layer 20. Since the bottom of the initial gap 33 is the first conductive layer 32, which is made of the same material as the second bosses, when etching away the multiple second bosses, part of the first conductive layer 32 is also etched away along the initial gap 33 to increase the depth of the initial gap 33 to form a gap 34, and the remaining first conductive layer 32 forms the first conductive structure 30. Among them, the remaining first conductive layer 32 flush with the gap 34 forms the second part of the first conductive structure 30, that is, the bottom surface of the second part is flush with the bottom surface of the gap 34. The remaining first conductive layer 32 located on the side of the gap 34 close to the substrate 10 forms the first part of the first conductive structure 30.

[0164] In some possible implementations, the second conductive layer 62, the first dielectric layer 61, and the first conductive layer 32 are etched using the remaining first mask layer 63 as a mask, so that the first conductive layer 32 located on the first isolation layer 20 forms a plurality of second bosses, and the first conductive layer 32 located in the isolation hole 21 and exposed outside the second bosses forms an initial gap 33 (step S204), including:

[0165] Step S2041: using the remaining first mask layer 63 as a mask, etching and removing a portion of the second conductive layer 62 and a portion of the first dielectric layer 61 to form a plurality of third bosses arranged at intervals, with the first conductive layer 32 exposed between the plurality of third bosses.

[0166] See also Fig.15 and Fig.16 , using the remaining first mask layer 63 as a mask, remove the second conductive layer 62 and the first dielectric layer 61 not covered by the remaining first mask layer 63, retain the second conductive layer 62 and the first dielectric layer 61 located below the remaining first mask layer 63, and the remaining second conductive layer 62 and the first dielectric layer 61 form a plurality of third bosses, which are arranged at intervals and correspond to the first bosses. The first conductive layer 32 is exposed between the plurality of first bosses.

[0167] Step S2042: removing the remaining first mask layer 63 to expose the third boss.

[0168] The remaining first mask layer 63 is removed to expose the third boss, the upper layer of the third boss is the remaining second conductive layer 62, and the lower layer is the first dielectric layer 61. In some examples, the remaining first mask layer 63 is removed while the third boss is formed, that is, the remaining first mask layer 63 does not need to be removed separately in this step. Fig.15 and Fig.16, after etching the second conductive layer 62 with the remaining first mask layer 63 as a mask, the first dielectric layer 61 is exposed between the remaining second conductive layers 62. The material of the first dielectric layer 61 is the same as that of the remaining first mask layer 63 (fourth dielectric layer), or the etching selectivity is relatively small, and while etching the first dielectric layer 61, the remaining first mask layer 63 is also etched away.

[0169] Step S2043 : etching and removing the second conductive layer 62 of the third bosses and the first conductive layer 32 exposed between the third bosses, exposing the first dielectric layer 61 of the third bosses, and forming second bosses and initial gaps 33 .

[0170] See also Fig.16 and Fig.17 The second conductive layer 62 and the first conductive layer 32 can be made of the same material or have a relatively small etching selection. When the second conductive layer 62 of the third boss is etched away, the first conductive layer 32 not covered by the third boss is also etched away. The first dielectric layer 61 of the third boss is exposed. The remaining first conductive layer 32 on the first isolation layer 20 forms a second boss, which is opposite to the third boss, and after a portion of the first conductive layer 32 in the isolation hole 21 is removed, an initial gap 33 is formed.

[0171] Step S2044: removing the first dielectric layer 61 of the third boss.

[0172] See also Fig.17 and Fig.18 , remove the first dielectric layer 61 of the third protrusion to expose the second protrusion. In other examples, the first dielectric layer 61 of the third protrusion can be completely consumed during the etching of the second conductive layer 62 and the first conductive layer 32, and does not need to be removed separately.

[0173] In some examples, a portion of the first mask layer 63 is removed to form a plurality of first bosses spaced apart along the first direction and spaced apart along the third direction (step S205), including:

[0174] Step S2051: A second dielectric layer 71 is formed on the first mask layer 63, and a third isolation layer 72 is formed on the second dielectric layer 71, wherein the third isolation layer 72 has a plurality of first grooves 73 extending along the first direction and spaced apart along the second direction, the first grooves 73 expose the second dielectric layer 71, and the third isolation layer 72 between adjacent first grooves 73 is opposite to the isolation holes 21 located in the same column along the first direction.

[0175] See also Figure 23 to Figure 26, a second dielectric layer 71 and a third isolation layer 72 are sequentially deposited on the first mask layer 63, and the first mask layer 63, the second dielectric layer 71 and the third isolation layer 72 are sequentially stacked. The third isolation layer 72 has a plurality of first grooves 73, and the plurality of first grooves 73 extend along the first direction and are spaced apart along the second direction. The third isolation layer 72 between adjacent first grooves 73 is opposite to, for example, directly opposite to, the isolation holes 21 located in the same column along the first direction. The plurality of first grooves 73 all penetrate the third isolation layer 72 to expose the second dielectric layer 71.

[0176] It can be understood that the third isolation layer 72 includes a plurality of isolation strips extending along the first direction and spaced apart along the second direction, a first groove 73 is formed between two adjacent isolation strips, and each isolation strip is opposite to a column of isolation holes 21. The specific structure of the third isolation layer 72 can be formed by a self-aligned double patterning (SADP) process, a self-aligned quadruple patterning (SAQP) process, a self-aligned multiple patterning (SAMP) process, etc.

[0177] For example, see Fig.11 A second intermediate layer 74, a sixth isolation layer 75 and a first photoresist layer 76 are sequentially stacked on the second dielectric layer 71, wherein the second intermediate layer 74 may be a spin-on carbon layer, and the sixth isolation layer 75 may be a nitride layer, such as a silicon nitride layer. Fig.23 , the first photoresist layer 76 is exposed and developed, so that the first photoresist layer 76 forms a first preset pattern. Using the first photoresist layer 76 as a mask, the sixth isolation layer 75 and the second intermediate layer 74 are etched to form an intermediate groove 77, and the intermediate groove 77 exposes the second dielectric layer 71. Fig.24 After removing the first photoresist layer 76, a spacer layer 78 is deposited. The spacer layer 78 covers the bottom wall and sidewall of the middle trench 77 and the top surface of the sixth isolation layer 75. The spacer layer 78 is etched to expose the second dielectric layer 71 and the sixth isolation layer 75. The remaining spacer layer 78 forms the third isolation layer 72. Fig.25 and Fig.26 , the sixth isolation layer 75 and the second intermediate layer 74 are removed to form a first trench 73 .

[0178] Step S2052 : forming a third dielectric layer 81 , a first intermediate layer 82 and a fourth isolation layer 83 , wherein the third dielectric layer 81 fills the first trench 73 , the first intermediate layer 82 covers the third dielectric layer 81 and the third isolation layer 72 , and the fourth isolation layer 83 covers the first intermediate layer 82 .

[0179] See also Fig.26 and Fig. 27 A third dielectric layer 81 is deposited between the first trenches 73 to fill the first trenches 73. The material of the third dielectric layer 81 can be the same as that of the second dielectric layer 71, so that the third dielectric layer 81 and the second dielectric layer 71 form a whole. Fig. 27 and Fig.28 , a first intermediate layer 82 is deposited on the third dielectric layer 81 and the third isolation layer 72, and a fourth isolation layer 83 is deposited on the first intermediate layer 82. The material of the first intermediate layer 82 can be spin-coated carbon, and the material of the fourth isolation layer 83 can be the same as that of the third isolation layer 72.

[0180] Step S2053 : etching and removing a portion of the fourth isolation layer 83 and a portion of the first intermediate layer 82 to form a plurality of second trenches 85 extending along the third direction and arranged at intervals, wherein the second trenches 85 expose the third dielectric layer 81 and the third isolation layer 72 .

[0181] See also Figure 28 to Figure 31 , forming a second photoresist layer 84 on the fourth isolation layer 83, and exposing and developing the second photoresist layer 84, so that the second photoresist layer 84 forms a second preset pattern (such as Fig.29 ). Using the second photoresist layer 84 having the second preset pattern as a mask, the fourth isolation layer 83 and the first intermediate layer 82 are etched to form a plurality of second grooves 85. Fig.30 and Fig.31 As shown, a plurality of second grooves 85 are arranged at intervals and extend along the third direction, and each second groove 85 is opposite to a portion of the adjacent regions of two isolation holes 21 adjacent to each other along the first direction. The bottom of the second groove 85 alternately exposes the third dielectric layer 81 and the third isolation layer 72 along the third direction. After the second grooves 85 are formed, the second photoresist layer 84 is removed.

[0182] Step S2054 : etching away the remaining fourth isolation layer 83 and the third isolation layer 72 exposed in the second trench 85 , forming a plurality of first etching holes 86 spaced apart along the third direction at the bottom of the second trench 85 , wherein the first etching holes 86 expose the second dielectric layer 71 .

[0183] See also Figure 30 to Figure 33, the exposed fourth isolation layer 83 is etched away to expose the remaining first intermediate layer 82, and the exposed third isolation layer 72 is etched away to form a plurality of first etching holes 86 arranged at intervals along the third direction. The plurality of first etching holes 86 located in the same column along the third direction are connected to a second trench 85, and the bottom of the first etching hole 86 exposes the second dielectric layer 71.

[0184] Step S2055 : etching and removing the second dielectric layer 71 exposed in the first etching hole 86 and the third dielectric layer 81 exposed in the second trench 85 . The first etching hole 86 exposes the first mask layer 63 , and the second trench 85 exposes the second dielectric layer 71 .

[0185] See also Figure 32 to Figure 37 , the third dielectric layer 81 exposed in the second groove 85 is etched away, so that the second groove 85 extends to the second dielectric layer 71, that is, the extended second groove 85 exposes the second dielectric layer 71, and the extended second groove 85 includes a portion of the first etching hole 86. And the second dielectric layer 71 exposed in the first etching hole 86 is etched away, so that the first etching hole 86 extends to the first mask layer 63, that is, the first etching hole 86 exposes the first mask layer 63. The second dielectric layer 71 exposed at the bottom of the second groove 85 has a certain height difference with the remaining third dielectric layer 81 (the third dielectric layer 81 covered by the first intermediate layer 82).

[0186] Step S2056 : removing the remaining first intermediate layer 82 to expose the third dielectric layer 81 and the third isolation layer 72 between adjacent second trenches 85 .

[0187] See also Figures 35 to 40 , the remaining first intermediate layer 82 is etched away to expose the third isolation layer 72 and the third dielectric layer 81, the third isolation layer 72 and the third dielectric layer 81 are located between adjacent second trenches 85, and the third isolation layer 72 and the third dielectric layer 81 between any two adjacent second trenches 85 are alternately arranged in sequence along the third direction. It can be understood that the third isolation layer 72 includes a plurality of third isolation blocks, and the third dielectric layer 81 includes a plurality of third dielectric blocks, and along the third direction, the third isolation blocks and the third dielectric blocks are alternately arranged in sequence. The third isolation blocks and the first mask layer 63 exposed by the first etching hole 86 are located in a row along the first direction, and have different heights, such as Fig.41 shown.

[0188] Step S2057 : etching away the remaining third isolation layer 72 , and etching the first mask layer 63 along the first etching hole 86 , wherein the first etching hole 86 extends into the first mask layer 63 , and the remaining third dielectric layer 81 forms a seventh boss.

[0189] See also Figures 38 to 43, the remaining third isolation layer 72 is etched away, and the remaining third dielectric layer 81 forms a plurality of seventh bosses, which are arranged at intervals along the third direction and at intervals along the first direction. A portion of the first mask layer 63 is etched away along the first etching hole 86, so that the first etching hole 86 extends into the first mask layer 63. In some examples, the first mask layer 63 includes a fourth dielectric layer 64, and a fifth isolation layer 65 disposed on the fourth dielectric layer 64. The material of the fifth isolation layer 65 can be the same as that of the third isolation layer 72, and the material of the fourth dielectric layer 64 can be the same as that of the third dielectric layer 81. When the first mask layer 63 is etched along the first etching hole 86, the fifth isolation layer 65 is etched away along the first etching hole 86, so that the first etching hole 86 extends to and exposes the fourth dielectric layer 64.

[0190] Step S2058: etching away at least a portion of the third dielectric layer 81 and the exposed second dielectric layer 71, and etching the first mask layer 63 along the first etching hole 86, the first etching hole 86 penetrates the first mask layer 63, and the remaining second dielectric layer 71 forms a fourth boss.

[0191] See also Figure 42 to Figure 47 , the remaining third dielectric layer 81, the second dielectric layer 71 exposed between the seventh bosses, and the remaining first mask layer 63 exposed at the bottom of the first etching hole 86 are etched, and part or all of the third dielectric layer 81, the second dielectric layer 71 between adjacent second trenches 85, the second dielectric layer 71 at the bottom of the second trench 85, and the first mask layer 63 at the bottom of the first etching hole 86 are removed. The first etching hole 86 exposes the second conductive layer 62, and the remaining second dielectric layer 71 (at least part of the second dielectric layer 71 at the bottom of the remaining third dielectric layer 81) forms a plurality of fourth bosses, and the plurality of fourth bosses are arranged along the third direction.

[0192] It can be understood that after etching away at least a portion of the third dielectric layer 81 and the exposed second dielectric layer 71, and etching the first mask layer 63 along the first etching hole 86, a first etching hole 86 of the layer is formed in the first mask layer 63, and a plurality of fourth bosses arranged at intervals are formed on the first mask layer 63. Among them, the plurality of fourth bosses are arranged along the third direction and along the first direction, and the plurality of first etching holes 86 are arranged along the third direction and along the first direction. And along the first direction and the third direction, the first etching hole 86 and the fourth bosses are staggered. That is, along the first direction, a first etching hole 86 is correspondingly arranged between two adjacent fourth bosses, and along the third direction, a first etching hole 86 is correspondingly arranged between two adjacent fourth bosses.

[0193] Step S2059: removing the first mask layer 63 exposed between the fourth protrusions, so that the remaining first mask layer 63 forms the first protrusions.

[0194] See also Figures 45 to 50 In the example where the first mask layer 63 includes the fourth dielectric layer and the fifth isolation layer 65, the exposed fifth isolation layer 65 is removed by etching, and the fifth isolation layer 65 covered by the fourth bosses and the fourth dielectric layer 64 remain, and the fourth dielectric layer 64 is exposed between the fourth bosses. The exposed fourth dielectric layer 64 and the fourth bosses are then removed by etching to form first bosses, and the first conductive layer 32 is exposed between the first bosses (see FIG. Fig.21 ).

[0195] In some examples, forming a second conductive structure 40 at least filling the gap 34 (step S300) includes:

[0196] Step S301 : forming a first layer 41 in the gap 34 , wherein the first layer 41 fills the gap 34 .

[0197] See also Fig.32 and Fig.52 , a first layer 41 is deposited in the gap 34, on the first isolation layer 20 and on the first conductive structure 30, and the first layer 41 fills the gap 34 and covers the first isolation layer 20 and the first conductive structure 30. Fig.51 and Fig.52 After the top surface of the first layer 41 is planarized, the first layer 41 is etched to expose the first conductive structure 30 and the first isolation layer 20. The remaining first layer 41 fills the gap 34, that is, the top surface of the first layer 41 is flush with the top surface of the first isolation layer 20.

[0198] Step S302 : converting a portion of the first conductive structure 30 away from the substrate 10 into a protection layer 35 , wherein the bottom surface of the protection layer 35 is higher than the bottom surface of the first layer 41 .

[0199] See also Fig.52 and Figure 2 , the exposed part of the first conductive structure 30 is oxidized and converted into a protective layer 35, that is, the part of the first conductive structure 30 away from the substrate 10 is the protective layer 35. The protective layer 35 can be provided to isolate the structure below the protective layer 35, to prevent the material of the second layer 43 from penetrating into the structure below the protective layer 35 when the second layer 43 is subsequently formed, and to ensure the performance of the structure below the protective layer 35. The bottom surface of the protective layer 35 is higher than the bottom surface of the first layer 41, so as to ensure that part of the side surface of the first layer 41 is in contact with the first conductive structure 30 below the protective layer 35, and the bottom surface of the first layer 41 is in contact with the first conductive structure 30 below the protective layer 35, thereby increasing the contact area between the first layer 41 and the first conductive structure 30.

[0200] Step S303 : forming an initial layer 42 on the first isolation layer 20 , the first layered layer 41 and the protective layer 35 , and forming a first stacked structure 91 and a transfer layer 94 stacked on the initial layer 42 .

[0201] See also Fig.52 and Fig.53 , the initial layer 42 covers the first isolation layer 20, the first layer 41 and the protective layer 35, the first stacked structure 91 covers the initial layer 42, and the transfer layer 94 covers the first stacked structure 91, that is, the initial layer 42, the first stacked structure 91 and the transfer layer 94 are stacked in sequence. The first stacked structure 91 includes a third intermediate layer 92 and a seventh isolation layer 93 disposed on the third intermediate layer 92, the third intermediate layer 92 may be a spin-on carbon layer, the seventh isolation layer 93 may be a silicon nitride layer, and the transfer layer 94 may be a polysilicon layer.

[0202] Step S304 : removing a portion of the transfer layer 94 to form first grooves 95 extending along the first direction and spaced apart along the second direction, wherein the first grooves 95 expose the first stacked structure 91 .

[0203] See also Fig.54 and Fig.55 , a portion of the transfer layer 94 is removed to form a plurality of first grooves 95, which extend along the first direction and are spaced apart along the second direction. The first grooves 95 expose the first stacked structure 91, and the first grooves 95 may also extend into the first stacked structure 91, that is, the bottom of the first groove 95 is located in the first stacked structure 91. For example, the bottom of the first groove 95 is located in the seventh isolation layer 93.

[0204] Step S305 : forming a second stacked structure 96 in the first groove 95 and on the transfer layer 94 .

[0205] See also Fig.55 and Fig.56 , a second stacked structure 96 is formed on the first groove 95 and the transfer layer 94, and the second stacked structure 96 fills the first groove 95 and covers the transfer layer 94. Exemplarily, the second stacked structure 96 includes a fourth intermediate layer 97 and an eighth isolation layer 98 disposed on the third intermediate layer 92, and the top surface of the fourth intermediate layer 97 is higher than the top surface of the transfer layer 94.

[0206] Step S306: removing part of the second stacked structure 96 to form second grooves extending along the fourth direction and spaced apart along the second direction, wherein the second grooves expose the transfer layer 94 , and the fourth direction intersects the first direction, the second direction and the third direction.

[0207] See also Fig.56 and Fig.57, etching the second stacked structure 96 to form a plurality of second grooves, the plurality of second grooves extending along the fourth direction and spaced apart along the second direction. The fourth direction intersects the first direction, the second direction, and the third direction. The second grooves expose the transfer layer 94 and a portion of the second stacked structure 96. For example, at the bottom of the second groove, the transfer layer 94 and the fourth intermediate layer 97 are alternately formed in sequence along the fourth direction. The second grooves can be formed by a self-aligned double patterning process, such as Fig.56 shown.

[0208] Step S307 : removing the transfer layer 94 exposed in the second groove, so that the transfer layer 94 forms a plurality of fifth bosses arranged at intervals along the first direction and arranged at intervals along the fourth direction.

[0209] The transfer layer 94 exposed in the second groove is removed by etching to form a second etching hole, which is connected to the second groove and exposes the first stacked structure 91. The remaining transfer layer 94 forms a plurality of fifth bosses, that is, the transfer layer 94 forms a transfer pattern. The plurality of fifth bosses are arranged at intervals in the first direction and at intervals in the fourth direction. The plurality of fifth bosses correspond to the plurality of first layers 41, and the orthographic projection of the fifth bosses on the substrate 10 has a partial overlap with the orthographic projection of the corresponding first layer 41 on the substrate 10.

[0210] Step S308 : removing the second stacked structure 96 and the first stacked structure 91 exposed between the fifth bosses, so that the first stacked structure 91 forms a plurality of sixth bosses arranged at intervals.

[0211] The second stacked structure 96 and the exposed first stacked structure 91 are removed by etching, and the remaining first stacked structure 91 forms a plurality of sixth bosses arranged at intervals, and the initial layer 42 is exposed between the plurality of sixth bosses. The plurality of sixth bosses correspond to the plurality of fifth bosses, that is, the transfer pattern is transferred to the first stacked structure 91.

[0212] Step S309 : removing the initial layer 42 exposed between the sixth bosses to form a plurality of second layers 43 spaced apart from each other. The plurality of second layers 43 are in contact with the plurality of first layers 41 , and the second layers 43 and the first layers 41 form a second conductive structure 40 .

[0213] See also Fig.58 , the exposed initial layer 42 is removed by etching, and the remaining initial layer 42 forms a plurality of second layers 43 arranged at intervals. The first layers 41, the first isolation layer 20 and the protective layer 35 are exposed between the plurality of second layers 43. The plurality of second layers 43 are in contact with the plurality of first layers 41 correspondingly, and the corresponding second layers 43 are in contact with part of the first layers 41. The second layers 43 and the first layers 41 form a second conductive structure 40.

[0214] See also Fig.58 and Figure 3 In order to ensure the isolation of the second layers 43, a second isolation layer 50 is formed between the second layers 43, and the second isolation layer 50 fills the second layers 43. The material of the second isolation layer 50 can be the same as that of the first isolation layer 20, so that the second isolation layer 50 and the first isolation layer 20 form a whole.

[0215] In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The description of reference terms such as "one implementation", "some implementations", "illustrative implementations", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0216] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A first isolation layer disposed on the substrate, wherein the first isolation layer has an isolation hole penetrating the first isolation layer; A first conductive structure is disposed in the isolation hole, the first conductive structure comprising a first portion filled in the bottom of the isolation hole, and a second portion located on the first portion, and a gap exists between at least a portion of an outer peripheral surface of the second portion and an inner wall of the isolation hole; A second conductive structure is at least filled in the gap.

2. The semiconductor structure according to claim 1, characterized in that: Part of the outer circumferential surface of the second part is in corresponding contact with part of the inner wall of the isolation hole, and the remaining outer circumferential surface of the second part and the remaining inner wall of the isolation hole are enclosed to form the gap.

3. The semiconductor structure according to claim 2, characterized in that: Taking a plane parallel to the surface of the substrate as a cross section, the cross-sectional shape of the first portion is a quadrilateral, the cross-sectional shape of the second portion is a triangle, and two sides of the triangle coincide with two sides of the quadrilateral.

4. The semiconductor structure according to claim 2, characterized in that: An orthographic projection of the first portion on the substrate covers an orthographic projection of the second portion on the substrate.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The substrate comprises a plurality of active regions arranged at intervals, and both ends of the active regions are first contact regions; There are a plurality of isolation holes, which are arranged at intervals along the first direction and along the second direction, each of the isolation holes correspondingly exposes one of the first contact areas, and the first direction intersects with the second direction.

6. The semiconductor structure according to claim 5, characterized in that: Along the first direction or along the second direction, the second portions of two adjacent first conductive structures are distributed in a centrally symmetrical manner.

7. The semiconductor structure according to claim 5, characterized in that: There are a plurality of the second conductive structures, and the plurality of the second conductive structures correspond one-to-one to the plurality of the gaps, and each of the second conductive structures includes: a first layer filled in the gap, wherein a top surface of the first layer is flush with a top surface of the first isolation layer; A second layer is located on the first isolation layer, the second portion, and the first layer.

8. The semiconductor structure according to claim 7, characterized in that: The semiconductor structure further includes a second isolation layer, which is disposed on the first isolation layer and filled between adjacent second layers.

9. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The second part includes a conductive column located on the first part, and a protective layer covering the top surface of the conductive column, the top surface of the protective layer is flush with the top surface of the first isolation layer, and the conductive column and the first part are an integral structure.

10. A method for manufacturing a semiconductor structure, characterized in that: include: forming a first isolation layer on a substrate, wherein the first isolation layer has an isolation hole penetrating through the first isolation layer; forming a first conductive structure in the isolation hole, wherein the first conductive structure comprises a first portion filled at the bottom of the isolation hole, and a second portion located on the first portion, and a gap exists between at least a portion of an outer peripheral surface of the second portion and an inner wall of the isolation hole; A second conductive structure is formed to fill at least the gap.

11. The manufacturing method according to claim 10, characterized in that: A first isolation layer is formed on a substrate, wherein the first isolation layer has an isolation hole penetrating the first isolation layer, comprising: Providing a substrate, the substrate comprising a plurality of active regions arranged at intervals, both ends of the active regions being first contact regions; forming a first isolation layer on the substrate; The first isolation layer is etched to form a plurality of isolation holes penetrating the first isolation layer and extending to the substrate, wherein the plurality of isolation holes are arranged at intervals along the first direction and arranged at intervals along the second direction, each of the isolation holes correspondingly exposes one of the first contact areas, and the first direction intersects with the second direction.

12. The manufacturing method according to claim 11, characterized in that: Forming a first conductive structure in the isolation hole, comprising: forming a first conductive layer in the isolation hole and on the first isolation layer, wherein the first conductive layer completely fills the isolation hole and covers a top surface of the first isolation layer; forming a first dielectric layer, a second conductive layer and a first mask layer stacked in sequence on the first conductive layer; Removing a portion of the first mask layer to form a plurality of first bosses spaced apart along the first direction and spaced apart along a third direction, wherein an orthographic projection of each of the first bosses on the substrate partially overlaps with two adjacent isolation holes along the first direction, and each isolation hole partially overlaps with an orthographic projection of one of the first bosses on the substrate, and the third direction intersects both the first direction and the second direction; Using the remaining first mask layer as a mask, etching the second conductive layer, the first dielectric layer and the first conductive layer, the first conductive layer located on the first isolation layer forms a plurality of second bosses arranged at intervals, and the first conductive layer located in the isolation hole and exposed outside the second bosses forms an initial gap; A plurality of the second bosses on the first isolation layer are removed by etching, and a portion of the first conductive layer is removed by etching along the initial gap to form the gap, and the remaining first conductive layer forms the first conductive structure.

13. The manufacturing method according to claim 12, characterized in that: Using the remaining first mask layer as a mask, etching the second conductive layer, the first dielectric layer and the first conductive layer, the first conductive layer located on the first isolation layer forms a plurality of second bosses, and the first conductive layer located in the isolation hole and exposed outside the second bosses forms an initial gap, including: Using the remaining first mask layer as a mask, etching and removing a portion of the second conductive layer and a portion of the first dielectric layer to form a plurality of third bosses arranged at intervals, wherein the first conductive layer is exposed between the plurality of third bosses; removing the remaining first mask layer to expose the third boss; Etching and removing the second conductive layer of the third bosses and the first conductive layer exposed between the third bosses, exposing the first dielectric layer of the third bosses, and forming the second bosses and the initial gap; The first dielectric layer of the third boss is removed.

14. The production method according to claim 12 or 13, characterized in that: Removing a portion of the first mask layer to form a plurality of first bosses spaced apart along the first direction and spaced apart along the third direction, comprising: forming a second dielectric layer on the first mask layer, and forming a third isolation layer on the second dielectric layer, wherein the third isolation layer has a plurality of first grooves extending along a first direction and spaced apart along the second direction, the first grooves exposing the second dielectric layer and being opposite to the isolation holes located in the same column along the first direction; forming a third dielectric layer, a first intermediate layer and a fourth isolation layer, wherein the third dielectric layer fills the first trench, the first intermediate layer covers the third dielectric layer and the third isolation layer, and the fourth isolation layer covers the first intermediate layer; Etching and removing a portion of the fourth isolation layer and a portion of the first intermediate layer to form a plurality of second grooves extending along the third direction and arranged at intervals, wherein the second grooves expose the third dielectric layer and the third isolation layer; Etching away the remaining fourth isolation layer and the third isolation layer exposed in the second trench, forming a plurality of first etching holes spaced apart along the third direction at the bottom of the second trench, wherein the first etching holes expose the second dielectric layer; Etching and removing the second dielectric layer exposed in the first etching hole and the third dielectric layer exposed in the second groove, wherein the first etching hole exposes the first mask layer, and the second groove exposes the second dielectric layer; removing the remaining first intermediate layer to expose the third dielectric layer and the third isolation layer between adjacent second trenches; Etching away the remaining third isolation layer, and etching the first mask layer along the first etching hole, wherein the first etching hole extends into the first mask layer, and the remaining third dielectric layer forms a third boss; Etching away at least a portion of the third dielectric layer and the exposed second dielectric layer, and etching the first mask layer along the first etching hole, wherein the first etching hole penetrates the first mask layer, and the remaining second dielectric layer forms a fourth boss; The first mask layer exposed between the fourth protrusions is removed, so that the remaining first mask layer forms the first protrusions.

15. The production method according to claim 12 or 13, characterized in that: Forming a second conductive structure at least filling the gap, comprising: forming a first layer in the gap, wherein the first layer fills the gap; Converting a portion of the first conductive structure away from the substrate into a protective layer, wherein the bottom surface of the protective layer is higher than the bottom surface of the first layer; forming an initial layer on the first isolation layer, the first layer and the protective layer, and forming a first stacked structure and a transfer layer stacked on the initial layer; removing a portion of the transfer layer to form first grooves extending along the first direction and spaced apart along the second direction, wherein the first grooves expose the first stacked structure; forming a second stacked structure in the first groove and on the transfer layer; removing a portion of the second stacked structure to form second grooves extending along a fourth direction and spaced apart along the second direction, wherein the second grooves expose the transfer layer, and the fourth direction intersects the first direction, the second direction, and the third direction; removing the transfer layer exposed in the second groove, so that the transfer layer forms a plurality of fifth bosses arranged at intervals along the first direction and arranged at intervals along the fourth direction; removing the second stacked structure and the first stacked structure exposed between the fifth bosses, so that the first stacked structure forms a plurality of sixth bosses arranged at intervals; The initial layer exposed between the sixth bosses is removed to form a plurality of second layers spaced apart from each other, the plurality of second layers are in corresponding contact with the plurality of first layers, and the second layers and the first layers form the second conductive structure.

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