Integrated circuit device and method of manufacturing same

Abstract

An integrated circuit device and a method of manufacturing an integrated circuit device are disclosed. The integrated circuit device includes a substrate having a memory cell region and a peripheral circuit region extending around the memory cell region; a cell transistor in the memory cell region; and a peripheral circuit transistor in the peripheral circuit region. The device further includes a capacitor structure including a lower electrode on the cell transistor, a dielectric layer on a surface of the lower electrode, an upper material layer on the dielectric layer, and a metal plate layer on the upper material layer; an interlayer insulating layer on the metal plate layer in the memory cell region and on the peripheral circuit transistor in the peripheral circuit region; and an etch stop pattern in the interlayer insulating layer at a boundary portion of the memory cell region and the peripheral circuit region. The etch stop pattern is laterally spaced from the sidewalls of the sheet metal layer and extends vertically.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0075551 filed in the Korean Intellectual Property Office on June 13, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The inventive concept generally relates to integrated circuit devices and methods of manufacturing the same, and more particularly, to integrated circuit devices including capacitors and methods of manufacturing the same. Background Art

[0004] Recently, with the rapid development of sophisticated semiconductor processing technology, integrated circuit devices have been highly integrated at an accelerated rate to have a reduced unit cell area. Therefore, the area occupied by the capacitor in the unit cell has also been reduced. For example, in the case of integrated circuit devices such as dynamic random access memory (DRAM), the integration level is increased and the unit cell area is reduced, but the required capacitance is maintained or increased. Therefore, it is very challenging to maintain or increase the capacitance in the structure while maintaining the desired electrical characteristics of the structure despite the reduction of the unit cell area. Summary of the invention

[0005] An aspect of the inventive concept provides an integrated circuit device capable of preventing a crack defect of a metal plate layer in a capacitor structure including an upper material layer as an upper electrode and a metal plate layer, and a method of manufacturing the same.

[0006] The objects of the inventive concept are not limited to the above-mentioned objects, and other unmentioned objects will be clearly understood by one of ordinary skill in the art from the following description.

[0007] According to one aspect of the inventive concept, an integrated circuit device is provided, comprising: a substrate having a memory cell region and a peripheral circuit region extending around the memory cell region; a plurality of cell transistors located in the memory cell region; a peripheral circuit transistor located in the peripheral circuit region; a capacitor structure comprising a lower electrode on the plurality of cell transistors, a dielectric layer on a surface of the lower electrode, an upper material layer on the dielectric layer, and a metal plate layer on the upper material layer; an interlayer insulating layer located on the metal plate layer in the memory cell region and above the peripheral circuit transistor in the peripheral circuit region; and an etch stop pattern located in the interlayer insulating layer at a boundary portion of the memory cell region and the peripheral circuit region, the etch stop pattern being separated from a sidewall of the metal plate layer in a horizontal direction and extending in a vertical direction.

[0008] According to another aspect of the inventive concept, an integrated circuit device is provided, comprising: a substrate having a memory cell region and a peripheral circuit region extending around the memory cell region; a plurality of cell transistors located in the memory cell region; a peripheral circuit transistor located in the peripheral circuit region; a capacitor structure comprising a lower electrode on the plurality of cell transistors, a dielectric layer on the surface of the lower electrode, an upper material layer on the dielectric layer, and a metal plate layer on the upper material layer; an interlayer insulating layer located above the metal plate layer in the memory cell region and above the peripheral circuit transistor in the peripheral circuit region; a first etch stop pattern located in the interlayer insulating layer at a boundary portion of the memory cell region and the peripheral circuit region, the first etch stop pattern being separated from a sidewall of the metal plate layer in a horizontal direction and extending in a vertical direction; and a second etch stop pattern located on the interlayer insulating layer in the memory cell region, the second etch stop pattern being separated from an uppermost surface of the metal plate layer in a vertical direction and extending in a horizontal direction.

[0009] According to another aspect of the inventive concept, an integrated circuit device is provided, comprising: a substrate including a memory cell region and a peripheral circuit region on at least one side of the memory cell region; a plurality of cell transistors located in the memory cell region; a peripheral circuit transistor located in the peripheral circuit region; a capacitor structure including a lower electrode on the plurality of cell transistors, a dielectric layer on a surface of the lower electrode, an upper material layer on the dielectric layer, and a metal plate layer on the upper material layer; an interlayer insulating layer located above the metal plate layer in the memory cell region and above the peripheral circuit transistor in the peripheral circuit region; a vertical etch stop pattern located in the interlayer insulating layer at a boundary portion of the memory cell region and the peripheral circuit region, the vertical etch stop pattern being separated from a sidewall of the metal plate layer in a horizontal direction and extending in a vertical direction; a metal contact passing through the interlayer insulating layer in the memory cell region and connected to the metal plate layer; and a peripheral circuit contact passing through the interlayer insulating layer in the peripheral circuit region and connected to the peripheral circuit transistor, wherein the vertical etch stop pattern comprises a material having an etching selectivity relative to the interlayer insulating layer.

[0010] According to another aspect of the inventive concept, a method for manufacturing an integrated circuit device is provided, the method comprising providing a substrate having a memory cell region and a peripheral circuit region extending around the memory cell region; forming a plurality of cell transistors in the memory cell region and forming a peripheral circuit transistor and a contact pad connected to the peripheral circuit transistor in the peripheral circuit region; sequentially forming a lower electrode on the plurality of cell transistors, a dielectric layer on a surface of the lower electrode, and an upper material layer on the dielectric layer; conformally forming a metal plate layer over the upper material layer in the memory cell region and over the contact pad in the peripheral circuit region; forming a conformally A first interlayer insulating layer covering a metal plate layer; forming an etch stop layer that conformally covers the first interlayer insulating layer and includes a material having an etch selectivity relative to the first interlayer insulating layer; exposing a portion of the metal plate layer by removing a portion of the etch stop layer located in a peripheral circuit area and a portion of the first interlayer insulating layer located in the peripheral circuit area; exposing a contact pad by removing a portion of the metal plate layer located in the peripheral circuit area; forming a second interlayer insulating layer that conformally covers the etch stop layer and the contact pad; exposing the uppermost surface of the etch stop layer by polishing the second interlayer insulating layer; and removing a portion of the etch stop layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals (where used) designate corresponding elements throughout the several views, and

[0012] In the attached picture:

[0013] Figure 1 is a plan view depicting a layout diagram of an example integrated circuit device according to an embodiment;

[0014] Figure 2 It is a depiction Figure 1 A plan view of an enlarged view of a region A1 of the example integrated circuit device shown in FIG.

[0015] Figure 3 It is along Figure 2 The line B1-B1' intercepts Figure 2 A cross-sectional view of an example integrated circuit device shown in;

[0016] Figure 4 , Figure 5A and Figure 5B is a cross-sectional view of an integrated circuit device according to other embodiments;

[0017] Figure 6 is a flow chart of an example method of manufacturing an integrated circuit device according to an embodiment;

[0018] Figures 7 to 17is a cross-sectional view depicting an intermediate process of an exemplary method of manufacturing an integrated circuit device in a process sequence according to an embodiment;

[0019] Fig.18 is a plan view depicting a layout diagram of an example integrated circuit device according to another embodiment;

[0020] Fig.19 It is along Fig.18 The line C1-C1' intercepts Fig.18 A cross-sectional view of the example integrated circuit device shown in ; and

[0021] Fig. 20 is a block diagram of an example system including an integrated circuit device according to an embodiment. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0023] Figure 1 is a plan view depicting a layout diagram of an example integrated circuit device 100 according to an embodiment, Figure 2 yes Figure 1 , and Figure 3 It is along Figure 2 1 is a cross-sectional view of the example integrated circuit device 100 taken along line B1 - B1 ′.

[0024] Refer to Figures 1 to 3 , the integrated circuit device 100 may include a substrate 110, the substrate 110 including a memory cell area MCA and a peripheral circuit area PCA surrounding the memory cell area MCA (i.e., extending around the memory cell area MCA). The term "surrounding" (or "enclosing" and other terms) as may be used herein is intended to broadly refer to an element, structure, or layer that extends around, surrounds, encapsulates, or surrounds another element, structure, or layer on all sides, although there may also be breaks or gaps. Thus, for example, a material layer having a void or gap therein may still "surround" another layer that it encapsulates.

[0025] The memory cell area MCA may be an area of ​​a volatile memory cell array of a dynamic random access memory (DRAM), and the peripheral circuit area PCA may be a core area or a peripheral circuit area of ​​the DRAM. For example, the peripheral circuit area PCA may include a peripheral circuit transistor PG configured to transmit a signal and / or power (i.e., a voltage) to the memory cell array included in the memory cell area MCA.

[0026] According to some embodiments, peripheral circuit transistor PG can be used (alone or in combination with other circuit elements) to form various circuits such as command decoders, control logic, address buffers, row decoders, column decoders, sense amplifiers, data input / output circuits, etc.

[0027] A device isolation trench 112T may be formed in the substrate 110, and a device isolation layer 112 may be formed in the device isolation trench 112T (i.e., filling the device isolation trench 112T). The term "fill" as may be used herein is intended to broadly refer to completely filling a defined space (e.g., the trench 112T) or partially filling a defined space; that is, the defined space does not need to be completely filled, but may, for example, be partially filled or have a void or other space in the entire space. The device isolation layer 112 may include, for example, silicon oxide, silicon nitride, or a combination thereof, although embodiments are not limited thereto. The device isolation layer 112 may define a plurality of first active regions AC1 on the substrate 110 in the memory cell area MCA and a second active region AC2 on the substrate 110 in the peripheral circuit area PCA.

[0028] Each of the plurality of first active regions AC1 may be arranged in the memory cell area MCA to have a long axis in a diagonal direction relative to the first horizontal direction X and the second horizontal direction Y. The plurality of word lines WL may extend across the plurality of first active regions AC1 in parallel with each other in the first horizontal direction X. The plurality of bit lines BL may extend in parallel with each other in the second horizontal direction Y over the plurality of word lines WL. The plurality of bit lines BL may be connected to the plurality of first active regions AC1 through a plurality of direct contacts DC.

[0029] A plurality of buried contacts BC may be formed between two adjacent bit lines BL among a plurality of bit lines BL. A plurality of buried contacts BC may be arranged in series in a first horizontal direction X and a second horizontal direction Y. A plurality of landing pads LP may be formed above the plurality of buried contacts BC. The plurality of buried contacts BC and the plurality of landing pads LP may connect the lower electrode 181 of the capacitor structure 180 formed above the plurality of bit lines BL to the first active region AC1. Each of the plurality of landing pads LP may be arranged so that a portion thereof overlaps with the buried contact BC in a vertical direction Z. The term "overlap" as used herein is intended to broadly refer to a first element that intersects at least a portion of a second element in a vertical direction (i.e., direction Z), but does not require that the first element and the second element be completely aligned with each other in a horizontal plane (i.e., in the first horizontal direction X and the second horizontal direction Y).

[0030] The substrate 110 may include a wafer including silicon (Si). According to some embodiments, the substrate 110 may include a wafer including a semiconductor element such as germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The substrate 110 may have a silicon-on-insulator (SOI) structure. In addition, the substrate 110 may include a conductive region, for example, a well doped with impurities or a structure doped with impurities.

[0031] A plurality of direct contacts DC may be formed in a plurality of direct contact holes DCH in the substrate 110. The plurality of direct contacts DC may be connected to the plurality of first active regions AC1. The plurality of direct contacts DC may include doped polysilicon, although the embodiment is not limited thereto. For example, the plurality of direct contacts DC may include polysilicon including impurities such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) at a relatively high concentration.

[0032] A plurality of bit lines BL may extend in a second horizontal direction Y over the substrate 110 and the plurality of direct contacts DC. Each of the plurality of bit lines BL may be connected to the first active region AC1 through the direct contact DC. Each of the plurality of bit lines BL may include a lower conductive pattern 132A, an intermediate conductive pattern 134A, and an upper conductive pattern 136A sequentially stacked on the substrate 110 in the vertical direction Z. The lower conductive pattern 132A may include doped polysilicon. Each of the intermediate conductive pattern 134A and the upper conductive pattern 136A may include, for example, titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten silicide (WSiN), or the like. 2 ) or a combination thereof, although the embodiment is not limited thereto. According to some embodiments, the middle conductive pattern 134A may include, for example, TiN, TiSiN, or a combination thereof, and the upper conductive pattern 136A may include W.

[0033] A plurality of bit lines BL may be covered by a plurality of insulating capping layers 140A. The term "covering" as used herein is intended to broadly refer to a material, layer or structure on or above another material, layer or structure, but does not require that the material, layer or structure completely covers the other material, layer or structure unless otherwise specifically stated. A plurality of insulating capping layers 140A may extend in a second horizontal direction Y on a plurality of bit lines BL. Spacers 150A may be arranged on both side walls of each of a plurality of bit lines BL. The spacers 150A may extend in a second horizontal direction Y on both side walls of a plurality of bit lines BL, and a portion of the spacers 150A may extend in a vertical direction Z into the direct contact hole DCH, and may cover both side walls of the direct contact DC.

[0034] The direct contact DC may be formed in the direct contact hole DCH formed in the substrate 110, and may extend to a level higher than the upper surface of the substrate 110 in the vertical direction Z. For example, the upper surface of the direct contact DC may be arranged at the same level as the upper surface of the lower conductive pattern 132A relative to the bottom surface of the substrate 110 (i.e., coplanar with the upper surface of the lower conductive pattern 132A), and the upper surface of the direct contact DC may contact the bottom surface of the middle conductive pattern 134A. In addition, the bottom surface of the direct contact DC may be arranged at a level lower than the upper surface of the substrate 110.

[0035] A plurality of insulating fences (not shown) and a plurality of conductive plugs 152 may be arranged in series between each of the plurality of bit lines BL in the second horizontal direction Y. The plurality of conductive plugs 152 may extend from the recessed space RS formed in the substrate 110 in the vertical direction Z. Both sidewalls of each of the plurality of conductive plugs 152 may be insulated from each other by the plurality of insulating fences in the second horizontal direction Y. The plurality of conductive plugs 152 may form a plurality of buried contacts BC.

[0036] A plurality of landing pads LP may be formed over the plurality of conductive plugs 152. A metal silicide layer (not shown) may also be arranged between the plurality of conductive plugs 152 and the plurality of landing pads LP. The metal silicide layer may include, for example, cobalt silicide, nickel silicide, or manganese silicide. Each of the plurality of landing pads LP may include a conductive barrier layer 162A and a landing pad conductive layer 164A. The conductive barrier layer 162A may include Ti, TiN, or a combination thereof. The landing pad conductive layer 164A may include a metal, a metal nitride, a conductive polysilicon, or a combination thereof. The plurality of landing pads LP may have an island pattern shape in a plan view. The plurality of landing pads LP may be electrically insulated from each other by an insulating pattern 166 surrounding the plurality of landing pads LP.

[0037] In the peripheral circuit area PCA, the peripheral circuit transistor PG may be arranged on the second active area AC2. The peripheral circuit transistor PG may include a gate dielectric layer 116, a gate electrode PGS, and a gate capping pattern 140B sequentially stacked on the second active area AC2. The term "sequentially stacked" as may be used herein is intended to broadly refer to an arrangement in which multiple material layers, elements, or structures are formed on each other in a specified order in the vertical direction Z.

[0038] The gate dielectric layer 116 may include at least one material selected from a high dielectric material having a dielectric constant higher than that of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxide. The gate electrode PGS may include a lower conductive pattern 132B, an intermediate conductive pattern 134B, and an upper conductive pattern 136B. The materials included in the lower conductive pattern 132B, the intermediate conductive pattern 134B, and the upper conductive pattern 136B may be the same as the materials included in the lower conductive pattern 132A, the intermediate conductive pattern 134A, and the upper conductive pattern 136A included in the bit line BL arranged in the memory cell area MCA. In addition, the gate capping pattern 140B may include silicon nitride.

[0039] According to some embodiments, both sidewalls of the gate electrode PGS may be covered by the gate spacer 150B. The gate spacer 150B may include an insulating material such as silicon oxide, silicon nitride, or a combination thereof, for example.

[0040] The peripheral circuit transistor PG may be covered by the first insulating layer 142. The second insulating layer 144 may be disposed on the first insulating layer 142. The contact plug CP may be formed in the peripheral circuit area PCA in a contact hole CPH vertically passing through the first insulating layer 142 and the second insulating layer 144 (i.e., extending into the first insulating layer 142 and the second insulating layer 144). Like the plurality of landing pads LP formed in the memory cell area MCA, the contact plug CP may include a conductive barrier layer 162B and a landing pad conductive layer 164B.

[0041] An upper insulating pattern 170 may be disposed on the insulating pattern 166 in the memory cell area MCA. The upper insulating pattern 170 may include a material having an etch selectivity with respect to the second insulating layer 144 and the insulating pattern 166. For example, the upper insulating pattern 170 may include silicon nitride.

[0042] The capacitor structure 180 may be arranged on the upper insulating pattern 170 in the memory cell area MCA. The capacitor structure 180 may include a plurality of lower electrodes 181, a capacitor dielectric layer 183, a silicon germanium layer 185, and a metal plate layer 187. Here, the silicon germanium layer 185 and the metal plate layer 187 may be provided as upper electrodes of the capacitor structure 180. The silicon germanium layer 185 may be referred to as an upper material layer. However, the material included in the upper material layer is not limited to silicon germanium.

[0043] The plurality of lower electrodes 181 may extend in the vertical direction Z on the plurality of landing pads LP. The bottoms of the plurality of lower electrodes 181 may be arranged in the opening portion of the upper insulating pattern 170. The support layer SPT may be arranged on the corresponding side walls of the plurality of lower electrodes 181. Due to the support layer SPT, two adjacent lower electrodes 181 may maintain a predetermined distance between each other in the first horizontal direction X, and tilting or pulling down of the plurality of lower electrodes 181 may be prevented. The support layer SPT may be formed in plurality on the side walls of the plurality of lower electrodes 181 at different levels from each other in the vertical direction Z.

[0044] The capacitor dielectric layer 183 may be disposed on the plurality of lower electrodes 181. The capacitor dielectric layer 183 may extend in the vertical direction Z on the sidewalls of the plurality of lower electrodes 181 and onto the upper and bottom surfaces of the support layer SPT, and may extend onto the upper insulating pattern 170. A silicon germanium layer 185 may be disposed on the capacitor dielectric layer 183 to cover the plurality of lower electrodes 181.

[0045] According to some embodiments, each of the plurality of lower electrodes 181 may include, for example, a metal such as ruthenium (Ru), Ti, tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), and W, a conductive metal nitride such as TiN, TaN, NbN, MoN, and WN, and a conductive metal oxide such as IrO 2 、RuO 2 and SrRuO 3 ) at least one material selected.

[0046] According to some embodiments, capacitor dielectric layer 183 may include at least one material from among zirconium oxide, hafnium oxide, titanium oxide, niobium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium strontium titanium oxide, scandium oxide, and lanthanum oxide.

[0047] The plurality of lower electrodes 181, the capacitor dielectric layer 183, and the silicon germanium layer 185 may be formed only in the memory cell area MCA. That is, the plurality of lower electrodes 181, the capacitor dielectric layer 183, and the silicon germanium layer 185 may not be formed in the peripheral circuit area PCA. Therefore, due to the large step difference in the vertical direction Z between the memory cell area MCA and the peripheral circuit area PCA, the surface of the silicon germanium layer 185 may include a horizontal upper surface and a vertical side surface. That is, the silicon germanium layer 185 arranged on the plurality of lower electrodes 181 in the memory cell area MCA may have a substantially right-angled (i.e., L-shaped) surface.

[0048] The metal plate layer 187 may be arranged along the surface of the silicon germanium layer 185, which is shaped as such. Therefore, the surface of the metal plate layer 187 may include a flat (i.e., horizontal) upper surface and a vertical side surface. However, the lower portion of the metal plate layer 187 may be arranged in the peripheral circuit area PCA (i.e., extending into the peripheral circuit area PCA). According to some embodiments, the metal plate layer 187 may include W, but is not limited thereto.

[0049] The interlayer insulating layer 190 may be arranged to cover both the memory cell area MCA and the peripheral circuit area PCA. In order to cover the step difference between the memory cell area MCA and the peripheral circuit area PCA according to the presence or absence of the capacitor structure 180, the interlayer insulating layer 190 in the memory cell area MCA and the peripheral circuit area PCA may have different thicknesses from each other in the vertical direction Z; that is, the vertical levels of the bottom surfaces of the interlayer insulating layer 190 in the memory cell area MCA and in the peripheral circuit area PCA may be different from each other relative to the upper surface of the substrate 110, while the upper surfaces of the interlayer insulating layer 190 in the memory cell area MCA and in the peripheral circuit area PCA may be located at the same level (i.e., coplanar) relative to the upper surface of the substrate 110.

[0050] In the integrated circuit device 100 according to the inventive concept, the etch stop pattern ESP may be arranged in the interlayer insulating layer 190 at a boundary portion of the memory cell area MCA and the peripheral circuit area PCA (more precisely, at a portion relatively more toward the peripheral circuit area PCA). According to some embodiments, the etch stop pattern ESP may be arranged to be spaced apart from the vertical sidewall of the metal plate layer 187 in the first horizontal direction X and to extend in the vertical direction Z.

[0051] According to some embodiments, the etch stop pattern ESP may include a material having an etch selectivity with respect to the interlayer insulating layer 190. For example, the interlayer insulating layer 190 may include silicon oxide, and the etch stop pattern ESP may include at least one selected from amorphous silicon, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon germanium.

[0052] According to some embodiments, the level of the uppermost surface of the etch stop pattern ESP may be higher than the level of the uppermost surface of the metal plate layer 187 relative to the upper surface of the substrate 110. In addition, the level of the lowermost surface of the etch stop pattern ESP may be higher than the level of the lowermost surface of the metal plate layer 187 relative to the upper surface of the substrate 110. In addition, the level of the uppermost surface of the etch stop pattern ESP may be lower than the level of the uppermost surface of the interlayer insulating layer 190 relative to the upper surface of the substrate 110. That is, the etch stop pattern ESP may be completely surrounded by the interlayer insulating layer 190.

[0053] According to some embodiments, a sidewall of the etch stop pattern ESP may be arranged to face a vertical sidewall of the metal plate layer 187 in the first horizontal direction X. In addition, the etch stop pattern ESP may be arranged to overlap a lower portion of the metal plate layer 187 in the vertical direction Z. The reason why the etch stop pattern ESP may be formed in this position is described in detail below by describing a manufacturing method.

[0054] A plurality of metal contacts MC may be arranged in the memory cell area MCA to pass through the interlayer insulating layer 190 and extend in the vertical direction Z. Bottom portions of the plurality of metal contacts MC may contact the metal plate layer 187 and may be electrically connected to the metal plate layer 187. That is, the plurality of metal contacts MC may be electrically connected to the upper electrode of the capacitor structure 180 through the metal plate layer 187. Each of the plurality of metal contacts MC may include a conductive barrier layer 192 and a contact conductive layer 194.

[0055] The peripheral circuit contact PC may be arranged in the peripheral circuit area PCA to pass through the interlayer insulating layer 190 and extend in the vertical direction Z. The bottom of the peripheral circuit contact PC may be connected to a contact pad as an upper portion of the contact plug CP. That is, the peripheral circuit contact PC may be electrically connected to the peripheral circuit transistor PG through the contact plug CP. The term "connection" as may be used herein is intended to broadly include electrical connections and / or physical connections, and may include other intermediate elements unless otherwise stated. Like the metal contacts MC formed in the memory cell area MCA, the peripheral circuit contact PC may include a conductive barrier layer 192 and a contact conductive layer 194.

[0056] In the integrated circuit device 100 according to the inventive concept, the level of the lowermost surface of the plurality of metal contacts MC may be lower than the level of the uppermost surface of the etch stop pattern ESP relative to the upper surface of the substrate 110. In addition, the level of the lowermost surface of the peripheral circuit contact PC may be lower than the level of the lowermost surface of the etch stop pattern ESP relative to the upper surface of the substrate 110. In addition, the vertical length of the peripheral circuit contact PC may be substantially the same as the sum of the vertical length of the metal plate layer 187 and the vertical length of the metal contact MC relative to the vertical direction Z.

[0057] Recently, with the rapid development of fine semiconductor processing technology, integrated circuit devices have been highly integrated at an accelerated rate, and therefore, the area of ​​the unit cell of the integrated circuit device has been reduced. Therefore, the area that the capacitor in the unit cell can occupy has also been reduced. For example, in the case of an integrated circuit device such as a DRAM, the integration level is increased and the unit cell area is reduced, but the required capacitance is maintained or increased. Therefore, a structure is needed in the capacitor to maintain the desired electrical characteristics and improve the capacitance by overcoming the limitations of space limitations and design rules.

[0058] Recently, in the integrated circuit device 100, in order to obtain a sensing margin in the capacitor structure 180, the metal plate layer 187 may be formed to cover the silicon germanium layer 185, and the silicon germanium layer 185 and the metal plate layer 187 may be used together as an upper electrode of the capacitor. In this case, a cleavage defect in which a corner portion of the metal plate layer 187 is also cleaved may occur in a process of polishing the interlayer insulating layer 190 covering the metal plate layer 187.

[0059] In order to effectively remove such defects, according to the present inventive concept, first, a portion of the interlayer insulating layer 190 (referred to as a first interlayer insulating layer) may be formed on the metal plate layer 187 to completely cover the metal plate layer 187, and then, an etch stop layer may be formed on the first interlayer insulating layer. Next, the remaining portion of the interlayer insulating layer 190 (referred to as a second interlayer insulating layer) may be formed, and finally, a polishing process may be performed on the second interlayer insulating layer to form the interlayer insulating layer 190 of the integrated circuit device 100. According to some embodiments, by removing a portion of the etch stop layer, an etch stop pattern ESP may be formed in the interlayer insulating layer 190. In the case of the above-described manufacturing method, a first interlayer insulating layer having a sufficient cross-sectional thickness may be formed below the etch stop layer, and therefore, even at a portion (e.g., a corner portion) where over-etching may occur, the metal plate layer 187 may be protected by the first interlayer insulating layer.

[0060] Finally, in the integrated circuit device 100 according to the inventive concept, crack defects of the metal plate layer 187 in the capacitor structure 180 including the silicon germanium layer 185 as the upper electrode and the metal plate layer 187 can be prevented, and thus, the defect rate can be reduced and the reliability can be improved.

[0061] Figure 4 , Figure 5A and Figure 5B are cross-sectional views of example integrated circuit devices 100A, 100B, and 100C according to other embodiments.

[0062] Most of the elements included in the integrated circuit devices 100A, 100B, and 100C described below and the materials included in the elements may be the same as those described above with reference to FIG. Figures 1 to 3 Therefore, for convenience of explanation, the description is given based on the difference from the above-described integrated circuit device 100 .

[0063] Reference Figure 4 , the integrated circuit device 100A may include a substrate 110 , and the substrate 110 includes a memory cell area MCA and a peripheral circuit area PCA.

[0064] In the integrated circuit device 100A according to the inventive concept, the first etch stop pattern ESP1 may be arranged in the interlayer insulating layer 190A at a boundary portion of the memory cell area MCA and the peripheral circuit area PCA (more precisely, at a portion relatively more toward the peripheral circuit area PCA). According to some embodiments, the first etch stop pattern ESP1 may be arranged to be spaced apart from the vertical sidewall of the metal plate layer 187 in the first horizontal direction X and to extend in the vertical direction Z. The first etch stop pattern ESP1 may be referred to as a vertical etch stop pattern.

[0065] In the integrated circuit device 100A according to the inventive concept, the second etch stop pattern ESP2 is arranged on the interlayer insulating layer 190A in the memory cell area MCA, is spaced apart from the uppermost surface of the metal plate layer 187 in the vertical direction Z, and extends in the first horizontal direction X. According to some embodiments, the second etch stop pattern ESP2 may be arranged to be spaced apart from the horizontal upper surface of the metal plate layer 187 in the vertical direction Z and extend in the first horizontal direction X. The second etch stop pattern ESP2 may be referred to as a horizontal etch stop pattern.

[0066] The first etch stop pattern ESP1 and the second etch stop pattern ESP2 may be arranged at different vertical levels to be spaced apart from each other with respect to the upper surface of the substrate 110. According to some embodiments, each of the first etch stop pattern ESP1 and the second etch stop pattern ESP2 may include a material having an etching selectivity with respect to the interlayer insulating layer 190A. For example, the interlayer insulating layer 190A may include silicon oxide, and each of the first etch stop pattern ESP1 and the second etch stop pattern ESP2 may include at least one selected from amorphous silicon, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon germanium. Here, the first etch stop pattern ESP1 and the second etch stop pattern ESP2 may include the same material as each other.

[0067] A plurality of metal contacts MC may be arranged in the memory cell area MCA to pass through the second etch stop pattern ESP2 and the interlayer insulating layer 190A and extend in the vertical direction Z. Bottom portions of the plurality of metal contacts MC may contact the metal plate layer 187 and may be electrically connected to the metal plate layer 187. That is, the plurality of metal contacts MC may be electrically connected to the upper electrode of the capacitor structure 180 through the metal plate layer 187. Sidewalls of the plurality of metal contacts MC may contact the second etch stop pattern ESP2 and the interlayer insulating layer 190A.

[0068] The peripheral circuit contact PC may be arranged in the peripheral circuit area PCA to pass through the interlayer insulating layer 190A and extend in the vertical direction Z. The bottom of the peripheral circuit contact PC may be connected to a contact pad which is a horizontal extension of an upper portion of the contact plug CP in the first horizontal direction X. That is, the peripheral circuit contact PC may be electrically connected to the peripheral circuit transistor PG through the contact plug CP. The sidewall of the peripheral circuit contact PC may contact the interlayer insulating layer 190A, but may not contact the second etch stop pattern ESP2.

[0069] Reference Figure 5A , the integrated circuit device 100B may include a substrate 110 , and the substrate 110 includes a memory cell area MCA and a peripheral circuit area PCA.

[0070] In the integrated circuit device 100B according to the present inventive concept, the interlayer insulating layer 190B may be arranged to cover both the memory cell region MCA and the peripheral circuit region PCA. In order to cover the step difference between the memory cell region MCA and the peripheral circuit region PCA according to the presence or absence of the capacitor structure 180, the interlayer insulating layer 190B of each of the memory cell region MCA and the peripheral circuit region PCA may have different cross-sectional thicknesses from each other in the vertical direction Z.

[0071] In the integrated circuit device 100B according to the inventive concept, the etching stop pattern ESP (see Figure 3). In more detail, first, a portion of the interlayer insulating layer 190B (referred to as a first interlayer insulating layer) may be formed on the metal plate layer 187 to completely cover the metal plate layer 187, and then, an etch stop layer may be formed on the first interlayer insulating layer. Next, a portion of the first interlayer insulating layer and a portion of the etch stop layer may be removed. Next, the remaining portion of the interlayer insulating layer 190B (referred to as a second interlayer insulating layer) may be formed, and finally, a polishing process may be performed on the second interlayer insulating layer to form the interlayer insulating layer 190B of the integrated circuit device 100B. In this manner, the interlayer insulating layer 190B may have a bottom surface that is located at a higher level in the memory cell area MCA than in the peripheral circuit area PCA relative to the upper surface of the substrate 110, while the upper surface of the interlayer insulating layer 190B is substantially flat and extends across the memory cell area MCA and the peripheral circuit area PCA in a direction parallel to the upper surface of the substrate 110. After the polishing process, the etch stop layer may be completely removed, and thus, the etch stop pattern ESP may not exist inside or outside the interlayer insulating layer 190B (see Figure 3 ).

[0072] Reference Figure 5B , the integrated circuit device 100C may include a substrate 110 , and the substrate 110 includes a memory cell area MCA and a peripheral circuit area PCA.

[0073] In the integrated circuit device 100C according to the present invention, the interlayer insulating layer 190C may be arranged to cover both the memory cell area MCA and the peripheral circuit area PCA. Figure 5A ) is the same as that in the integrated circuit device 100C, the etching stop pattern ESP (see Figure 3 ).

[0074] In the integrated circuit device 100C according to the present inventive concept, during the deposition process of the silicon germanium layer 185C, more deposition may be performed on the corner portion of the silicon germanium layer 185C than on other portions of the silicon germanium layer 185C. Therefore, the corner portion of the silicon germanium layer 185C may have an overhang OH. In addition, the metal plate layer 187C may be conformally formed along the silicon germanium layer 185C, and therefore, the corner portion of the metal plate layer 187C may also have an overhang OH. The term "conformally" (or "conformal" or the like) as used herein in the context of a material layer or coating is intended to broadly refer to a material layer or coating having a substantially uniform cross-sectional thickness relative to the contour of the surface to which the material layer is applied.

[0075] Figure 6 The present invention is a method for manufacturing an integrated circuit device (eg, Figures 1 to 5BFlowchart of an example method S200 of any one of the illustrative devices shown in .

[0076] Reference Figure 6 , the method S200 of manufacturing an integrated circuit device may include a process sequence of a first operation S210 to an eighth operation S280.

[0077] When a particular embodiment is implemented differently, the specific order of operations may be different from the order described. For example, two operations described sequentially may be performed substantially simultaneously, or may be performed in an order opposite to the order described.

[0078] Reference Figure 6 , a method S200 for manufacturing an integrated circuit device according to the present invention may include: a first operation S210 of forming cell transistors in a memory cell area MCA and peripheral circuit transistors in a peripheral circuit area PCA and contact pads connected to the peripheral circuit transistors; a second operation S220 of forming lower electrodes, a dielectric layer, and a silicon germanium layer on a plurality of cell transistors; a third operation S230 of conformally forming a metal plate layer covering the silicon germanium layer in the memory cell area and covering the contact pads in the peripheral circuit area; a fourth operation S240 of forming a first interlayer insulating layer conformally covering the metal plate layer; a fifth operation S250 of forming an etch stop layer conformally covering the first interlayer insulating layer; a sixth operation S260 of exposing the contact pads by removing a portion of the etch stop layer, a portion of the first interlayer insulating layer, and a portion of the metal plate layer in the peripheral circuit area; a seventh operation S270 of forming a second interlayer insulating layer conformally covering the etch stop layer and the contact pads; and an eighth operation S280 of exposing the etch stop layer by polishing the second interlayer insulating layer.

[0079] Reference will be made to the following description Figures 7 to 17 Technical characteristics with respect to each of the first to eighth operations S210 to S280 are described in detail.

[0080] Figures 7 to 17 is a cross-sectional view for illustrating an intermediate process in an exemplary method of manufacturing an integrated circuit device according to a process order according to an embodiment.

[0081] Reference Figure 7 , a plurality of device isolation trenches 112T and a plurality of device isolation layers 112 at least partially filling the corresponding device isolation trenches 112T may be formed on a substrate 110 having a memory cell area MCA and a peripheral circuit area PCA.

[0082] The plurality of device isolation layers 112 may define a plurality of first active regions AC1 (see Figure 2) and define a second active area AC2 on the substrate 110 in the peripheral circuit area PCA (see Figure 2 ).

[0083] Next, a gate dielectric layer 116 may be formed on the substrate 110 in the peripheral circuit area PCA.

[0084] Next, a direct contact hole DCH exposing the first active region AC1 may be formed by removing a portion of the substrate 110 , and a direct contact DC may be formed in the direct contact hole DCH.

[0085] Next, the bit line BL and the insulating capping layer 140A may be formed on the direct contact DC, and the gate electrode PGS and the gate capping pattern 140B may be formed on the gate dielectric layer 116 .

[0086] Next, the gate spacer 150B may be formed on the sidewall of the gate electrode PGS, and the first insulating layer 142 covering the gate electrode PGS may be formed.

[0087] Next, spacers 150A may be formed on sidewalls of the bit lines BL and the insulating capping layer 140A in the memory cell area MCA, and a plurality of insulating barriers (not shown) may be formed between the plurality of bit lines BL.

[0088] Next, portions of the substrate 110 disposed at the bottom of the contact spaces (not shown) between the plurality of bit lines BL and between the plurality of insulating barriers may be removed to form a plurality of recess spaces RS exposing the first active region AC1 between the plurality of bit lines BL.

[0089] Next, a plurality of conductive plugs 152 filling the plurality of recess spaces RS and filling portions of the contact space between the plurality of bit lines BL may be formed.

[0090] Next, a plurality of contact holes CPH exposing the second active area AC2 may be formed by etching the first insulating layer 142 in the peripheral circuit area PCA.

[0091] Next, a plurality of landing pads LP including the conductive barrier layer 162A and the landing pad conductive layer 164A may be formed in the memory cell area MCA, and a plurality of contact plugs CP including the conductive barrier layer 162B and the landing pad conductive layer 164B may be formed in the peripheral circuit area PCA.

[0092] Next, an insulating pattern 166 surrounding sidewalls of the plurality of landing pads LP and a second insulating layer 144 covering sidewalls of the contact plugs CP may be formed.

[0093] Reference Figure 8, in the memory cell area MCA, a mold structure including a first mold layer, a second mold layer, and a third mold layer sequentially arranged on the upper insulating pattern 170 may be formed.

[0094] In addition, a support layer SPT may be selectively formed between the first and second mold layers, between the second and third mold layers, and on the third mold layer.

[0095] Next, a mask pattern may be formed on the mold structure, an opening may be formed through the mold structure by using the mask pattern as an etching mask, and a lower electrode 181 may be formed in the opening.

[0096] Next, by removing the mold structure, the upper insulating pattern 170 , the lower electrode 181 , and the supporting layer SPT may be formed.

[0097] Reference Fig. 9 , a capacitor dielectric layer 183 may be formed on the upper insulating pattern 170 , the lower electrode 181 , and the support layer SPT, and a silicon germanium layer 185 and a metal plate layer 187 may be sequentially formed.

[0098] In detail, the metal plate layer 187 may be conformally formed to cover the silicon germanium layer 185 in the memory cell area MCA and to cover the contact pad of each of the plurality of contact plugs CP in the peripheral circuit area PCA. The metal plate layer 187 may include W, but is not limited thereto.

[0099] Reference Fig.10 , the first interlayer insulating layer 190P may be formed to conformally cover the metal plate layer 187 .

[0100] In detail, the first interlayer insulating layer 190P may include the interlayer insulating layer 190 described below (see Fig.15 The first interlayer insulating layer 190P may include silicon oxide, but is not limited thereto.

[0101] Reference Fig.11 , the etch stop layer ESL may be formed to conformally cover the first interlayer insulating layer 190P.

[0102] In detail, the etch stop layer ESL may be separated into first etch stop patterns ESP1 (see FIG. 1 ) extending in the vertical direction Z described below. Fig.12 ) and a second etch stop pattern ESP2 extending in the first horizontal direction X (see Fig.12 ). The etch stop layer ESL may include a material having an etch selectivity with respect to the first interlayer insulating layer 190P. The etch stop layer ESL may include at least one material selected from amorphous silicon, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon germanium, but is not limited thereto.

[0103] Reference Fig.12 , by removing the etch stop layer ESL (see Fig.11 ) located in the peripheral circuit area PCA and a portion of the first interlayer insulating layer 190P located in the peripheral circuit area PCA may expose a portion of the metal plate layer 187.

[0104] In detail, the etching stop layer ESL (see Fig.11 ) may be separated into a first etch stop pattern ESP1 and a second etch stop pattern ESP2. The first etch stop pattern ESP1 may be arranged on the sidewall of the first interlayer insulating layer 190P at a boundary portion between the memory cell area MCA and the peripheral circuit area PCA (more precisely, at a portion relatively more toward the peripheral circuit area PCA). In addition, in the memory cell area MCA, the second etch stop pattern ESP2 may be arranged on the upper surface of the first interlayer insulating layer 190P.

[0105] Reference Fig.13 , in the peripheral circuit area PCA, a portion of the metal plate layer 187 may be removed to expose a contact pad of each of the plurality of contact plugs CP.

[0106] In detail, the outermost sidewall of the first etch stop pattern ESP1, the outermost sidewall of the first interlayer insulating layer 190P, and the outermost sidewall of the metal plate layer 187 may be coplanar in the vertical direction Z.

[0107] Reference Fig.14 A second interlayer insulating layer 190Q conformally covering the first and second etch stop patterns ESP1 and ESP2 and the contact pad of each of the plurality of contact plugs CP may be formed.

[0108] In detail, the second interlayer insulating layer 190Q may include the interlayer insulating layer 190 described below (see Fig.15 Like the first interlayer insulating layer 190P, the second interlayer insulating layer 190Q may include silicon oxide, but is not limited thereto.

[0109] Reference Fig.15 The second interlayer insulating layer 190Q (see Fig.14 )polishing.

[0110] In detail, the second interlayer insulating layer 190Q (see Fig.14 ) is polished to expose the upper surface of the second etch stop pattern ESP2. Through this polishing process, the first interlayer insulating layer 190P and the second interlayer insulating layer 190Q (see Fig.14) forms an interlayer insulating layer 190.

[0111] That is, first, a first interlayer insulating layer 190P may be formed on the metal plate layer 187 (see Fig.10 ), and then, the first interlayer insulating layer 190P (see Fig.11 ) is formed on the etching stop layer ESL (see Fig.11 ). Afterwards, a second interlayer insulating layer 190Q may be formed (see Fig.14 ), and the second interlayer insulating layer 190Q (see Fig.14 )A polishing process is performed to form an interlayer insulating layer 190.

[0112] According to the present invention, the etching stop layer ESL (see Fig.11 ) below to form a first interlayer insulating layer 190P having a sufficient thickness (see Fig.11 ), and therefore, even if the second interlayer insulating layer 190Q (see Fig.14 ) in the polishing process where over-etching may occur (for example, corner portions), the metal plate layer 187 may also be formed by the first interlayer insulating layer 190P (see Fig.11 )Protect.

[0113] Reference Fig.16 , the second etching stop pattern ESP2 can be selectively removed (see Fig.15 ), and a plurality of metal contact holes MCH passing through the interlayer insulating layer 190 may be formed in the memory cell area MCA, and a peripheral circuit contact hole PCH passing through the interlayer insulating layer 190 may be formed in the peripheral circuit area PCA.

[0114] Here, the removal of the second etching stop pattern ESP2 (see Fig.15 ), however, according to other embodiments, the second etch stop pattern ESP2 (see Fig.15 ).

[0115] In detail, a plurality of metal contact holes MCH formed through the interlayer insulating layer 190 may expose the uppermost surface of the metal plate layer 187 , and a peripheral circuit contact hole PCH formed through the interlayer insulating layer 190 may expose the uppermost surface of the contact pad of the contact plug CP.

[0116] Reference Fig.17 , a conductive barrier layer 192 that conformally covers the inner sidewalls of the plurality of metal contact holes MCH and a conductive barrier layer 192 that conformally covers the inner sidewalls of the peripheral circuit contact holes PCH may be formed.

[0117] In detail, the conductive barrier layer 192 may be continuously and conformally formed throughout the memory cell area MCA and the peripheral circuit area PCA. The conductive barrier layer 192 may include Ti, TiN, or a combination thereof, but is not limited thereto.

[0118] Refer again Figure 3 , a contact conductive layer 194 filling a plurality of metal contact holes MCH and peripheral circuit contact holes PCH may be formed, and an upper portion of the contact conductive layer 194 and an upper portion of the conductive barrier layer 192 may be polished to form a plurality of metal contacts MC and peripheral circuit contacts PC.

[0119] According to the above-described method of manufacturing an integrated circuit device according to the present inventive concept, crack defects of the metal plate layer 187 in the capacitor structure 180 including the silicon germanium layer 185 as the upper electrode and the metal plate layer 187 can be prevented, and therefore, the defect rate can be reduced and the reliability can be improved.

[0120] Fig.18 is a plan view depicting a layout diagram of an example integrated circuit device 300 according to another embodiment, and Fig.19 It is along Fig.18 The line C1-C1' intercepts Fig.18 00 is a cross-sectional view of an integrated circuit device 300 shown in FIG.

[0121] Most of the elements included in the integrated circuit device 300 described below and the materials included in the elements may be the same as those described above with reference to Figures 1 to 3 Therefore, for convenience of explanation, the description will be given based on the differences from the above-described integrated circuit device 100 .

[0122] Refer to Fig.18 and Fig.19 , the integrated circuit device 300 may include a plurality of first conductive lines 320 , a channel layer 330 , a gate electrode layer 340 , a gate insulating layer 350 , and a capacitor structure 180 arranged in a memory cell area MCA of a substrate 110 .

[0123] The integrated circuit device 300 according to the inventive concept may be a memory device including a vertical channel transistor, and the vertical channel transistor may refer to a structure in which a channel length of a channel layer 330 extends in a vertical direction Z from a substrate 110 .

[0124] A lower insulating layer 312 may be disposed on the substrate 110, and a plurality of first conductive lines 320 may be disposed on the lower insulating layer 312 to be spaced apart from each other in the first horizontal direction X, and may extend in the second horizontal direction Y. A plurality of first insulating patterns 322 may be disposed on the lower insulating layer 312 to fill spaces between the plurality of first conductive lines 320. The plurality of first conductive lines 320 may correspond to bit lines BL of the integrated circuit device 300.

[0125] According to some embodiments, the plurality of first conductive lines 320 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. The plurality of first conductive lines 320 may include a single layer or multiple layers including the above materials. According to other embodiments, the plurality of first conductive lines 320 may include a two-dimensional semiconductor material. For example, the two-dimensional semiconductor material may include graphene, carbon nanotubes, nanosheets, or a combination thereof.

[0126] The channel layer 330 may be arranged to have an island shape arranged on the plurality of first conductive lines 320 to be spaced apart from each other in the first horizontal direction X and the second horizontal direction Y. The channel layer 330 may have a first width in the first horizontal direction X and a first height in the vertical direction Z relative to the upper surface of the lower insulating layer 312, wherein the first height may be greater than the first width. The bottom of the channel layer 330 may be used as a first source / drain region (not shown), the upper portion of the channel layer 330 may be used as a second source / drain region (not shown), and a portion of the channel layer 330 located between the first source / drain region and the second source / drain region may be used as a channel region (not shown).

[0127] The gate electrode layer 340 may surround the sidewalls of the channel layer 330 and extend in the first horizontal direction X. In a plan view, the gate electrode layer 340 may be a gate-all-around type surrounding all sidewalls (eg, four sidewalls in total) of the channel layer 330. The gate electrode layer 340 may correspond to a word line WL of the integrated circuit device 300.

[0128] According to other embodiments, the gate electrode layer 340 may be a dual-gate type, for example, the gate electrode layer 340 may include a first sub-gate electrode (not shown) facing the first sidewall of the channel layer 330 and a second sub-gate electrode (not shown) facing the second sidewall of the channel layer 330 opposite to the first sidewall. According to other embodiments, the gate electrode layer 340 may be a single-gate type covering only the first sidewall of the channel layer 330 and extending in the first horizontal direction X.

[0129] The gate electrode layer 340 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof, although the embodiment is not limited thereto.

[0130] Gate insulating layer 350 may surround sidewalls of channel layer 330 and may be disposed between channel layer 330 and gate electrode layer 340. According to some embodiments, gate insulating layer 350 may include silicon oxide, silicon oxynitride, a high dielectric material, or a combination thereof, although embodiments are not limited thereto.

[0131] A first buried insulating layer 342 surrounding a lower sidewall of the channel layer 330 may be disposed on the plurality of first insulating patterns 322 , and a second buried insulating layer 344 surrounding an upper sidewall of the channel layer 330 and covering the gate electrode layer 340 may be disposed on the first buried insulating layer 342 .

[0132] The capacitor contact 360 may be arranged on the channel layer 330. The capacitor contact 360 may be arranged to overlap the channel layer 330 in the vertical direction Z, and may be arranged to have a matrix shape (i.e., islands arranged in rows and columns) in the first horizontal direction X and the second horizontal direction Y (i.e., in a plan view). The upper insulating layer 362 may surround the sidewalls of the capacitor contact 360 on the second buried insulating layer 344. The upper insulating pattern 170 may be arranged on the upper insulating layer 362, and the capacitor structure 180 may be arranged on the upper insulating pattern 170.

[0133] Fig. 20 is a block diagram of an example system 1000 including an integrated circuit device according to an embodiment.

[0134] Reference Fig. 20 , the system 1000 may include a controller 1010 , an input / output device 1020 , a memory device 1030 , an interface 1040 , and a bus 1050 .

[0135] System 1000 may include a mobile system or a system configured to send or receive information. According to some embodiments, the mobile system may include a portable computer, a web tablet, a mobile phone, a digital music player, or a memory card.

[0136] The controller 1010 may be configured to control an execution program in the system 1000 , and may include a microprocessor, a digital signal processor, a microcontroller, or a device similar thereto.

[0137] The input / output device 1020 may be used to input or output data of the system 1000. The system 1000 may be connected to an external device such as a personal computer or a network, and may exchange data with the external device by using the input / output device 1020. The input / output device 1020 may include, for example, a touch screen, a touch pad, a keyboard, or a display.

[0138] The memory device 1030 may store data used for the operation of the controller 1010 or data processed by the controller 1010. The memory device 1030 may include any one of the above-described integrated circuit devices 100, 100A, 100B, 100C, and 300 described according to the inventive concept.

[0139] The interface 1040 may be a data transmission path between the system 1000 and an external device. The controller 1010 , the input / output device 1020 , the memory device 1030 , and the interface 1040 may communicate with each other through a bus 1050 .

[0140] While the inventive concepts have been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, include: a substrate having a memory cell region and a peripheral circuit region extending around the memory cell region when viewed in a plan view; a plurality of cell transistors located in the memory cell region; a peripheral circuit transistor located in the peripheral circuit region; a capacitor structure comprising a lower electrode on the plurality of unit transistors, a dielectric layer on a surface of the lower electrode, an upper material layer on the dielectric layer, and a metal plate layer on the upper material layer; an interlayer insulating layer located on the metal plate layer in the memory cell region and on the peripheral circuit transistor in the peripheral circuit region; as well as An etch stop pattern is located in the interlayer insulating layer at a boundary portion of the memory cell region and the peripheral circuit region, the etch stop pattern is spaced apart from the side wall of the metal plate layer in a first direction parallel to the upper surface of the substrate, and extends in a second direction perpendicular to the first direction.

2. The integrated circuit device according to claim 1, in, With respect to the upper surface of the substrate, a first level of the uppermost surface of the etch stop pattern is higher than a second level of the uppermost surface of the metal plate layer, With respect to the upper surface of the substrate, a third level of the lowermost surface of the etch stop pattern is higher than a fourth level of the lowermost surface of the metal plate layer, and The first level is lower than a fifth level of an uppermost surface of the interlayer insulating layer with respect to an upper surface of the substrate.

3. The integrated circuit device according to claim 1, in, In the first direction, a sidewall of the etch stop pattern is arranged to face a sidewall of the metal plate layer, and In the second direction, the etch stop pattern is arranged to at least partially overlap the metal plate layer.

4. The integrated circuit device according to claim 1, in, The etch stop pattern is completely surrounded by the interlayer insulating layer in a plan view.

5. The integrated circuit device according to claim 1, further comprising: include: a metal contact extending through the interlayer insulating layer in the second direction in the memory cell region and electrically connected to the metal plate layer; as well as A peripheral circuit contact extends through the interlayer insulating layer in the second direction in the peripheral circuit region and is electrically connected to the peripheral circuit transistor.

6. The integrated circuit device according to claim 5, in, With respect to the upper surface of the substrate, a first level of a lowermost surface of the metal contact is lower than a second level of an uppermost surface of the etch stop pattern, and With respect to the upper surface of the substrate, a third level of a lowermost surface of the peripheral circuit contact is lower than a fourth level of a lowermost surface of the etch stop pattern.

7. The integrated circuit device according to claim 5, in, A length of the peripheral circuit contact in the second direction is greater than a length of the metal plate layer in the second direction.

8. The integrated circuit device according to claim 1, in, The upper material layer and the metal plate layer are upper electrodes of the capacitor structure, the upper material layer includes a silicon germanium layer, and the metal plate layer includes tungsten.

9. The integrated circuit device according to claim 1, in, The etch stop pattern includes a material having an etch selectivity with respect to the interlayer insulating layer.

10. The integrated circuit device according to claim 9, in, The interlayer insulating layer includes silicon oxide, and The etch stop pattern includes at least one of amorphous silicon, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon germanium.

11. An integrated circuit device, include: a substrate having a memory cell region and a peripheral circuit region extending around the memory cell region when viewed in a plan view; a plurality of cell transistors located in the memory cell region; a peripheral circuit transistor located in the peripheral circuit region; a capacitor structure comprising a lower electrode on the plurality of unit transistors, a dielectric layer on a surface of the lower electrode, an upper material layer on the dielectric layer, and a metal plate layer on the upper material layer; an interlayer insulating layer located above the metal plate layer in the memory cell region and above the peripheral circuit transistor in the peripheral circuit region; a first etch stop pattern located in the interlayer insulating layer at a boundary portion of the memory cell region and the peripheral circuit region, the first etch stop pattern being spaced apart from a sidewall of the metal plate layer in a first direction parallel to an upper surface of the substrate and extending in a second direction perpendicular to the first direction; as well as A second etch stop pattern is located on the interlayer insulating layer in the memory cell region, the second etch stop pattern being spaced apart from an uppermost surface of the metal plate layer in the second direction and extending in the first direction.

12. The integrated circuit device according to claim 11, in, The first etch stop pattern and the second etch stop pattern are spaced apart from each other in the second direction, In the first direction, a sidewall of the first etch stop pattern faces a sidewall of the metal plate layer, and In the second direction, a lower surface of the second etch stop pattern faces an uppermost surface of the metal plate layer.

13. The integrated circuit device according to claim 11, further comprising: include: a metal contact extending through the second etch stop pattern and the interlayer insulating layer in the memory cell region in the second direction and electrically connected to the metal plate layer; as well as A peripheral circuit contact extends through the interlayer insulating layer in the second direction in the peripheral circuit region and is electrically connected to the peripheral circuit transistor.

14. The integrated circuit device according to claim 13, in, A sidewall of the metal contact contacts the second etch stop pattern and the interlayer insulating layer, and A sidewall of the peripheral circuit contact contacts the interlayer insulating layer, and a sidewall of the peripheral circuit contact does not contact the second etch stop pattern.

15. The integrated circuit device according to claim 11, in, The interlayer insulating layer includes silicon oxide, and The first etch stop pattern and the second etch stop pattern include the same material as each other, and Each of the first etch stop pattern and the second etch stop pattern includes at least one of amorphous silicon, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon germanium.

16. An integrated circuit device, include: a substrate including a memory cell region and a peripheral circuit region located on at least one side of the memory cell region; a plurality of cell transistors located in the memory cell region; a peripheral circuit transistor located in the peripheral circuit region; a capacitor structure comprising a lower electrode on the plurality of unit transistors, a dielectric layer on a surface of the lower electrode, an upper material layer on the dielectric layer, and a metal plate layer on the upper material layer; an interlayer insulating layer located above the metal plate layer in the memory cell region and above the peripheral circuit transistor in the peripheral circuit region; a first etch stop pattern located in the interlayer insulating layer at a boundary portion of the memory cell region and the peripheral circuit region, the first etch stop pattern being spaced apart from a sidewall of the metal plate layer in a first direction parallel to an upper surface of the substrate and extending in a second direction perpendicular to the first direction; a metal contact extending through the interlayer insulating layer in the second direction in the memory cell region and electrically connected to the metal plate layer; as well as a peripheral circuit contact extending through the interlayer insulating layer in the second direction in the peripheral circuit region and electrically connected to the peripheral circuit transistor, The first etching stop pattern includes a material having an etching selectivity relative to the interlayer insulating layer.

17. The integrated circuit device according to claim 16, in, With respect to the upper surface of the substrate, a first level of the uppermost surface of the metal plate layer is lower than a second level of the uppermost surface of the first etch stop pattern, A third level of the lowermost surface of the metal contact is lower than the first level relative to the upper surface of the substrate, and With respect to the upper surface of the substrate, a fourth level of a lowermost surface of the peripheral circuit contact is lower than a fifth level of a lowermost surface of the first etch stop pattern.

18. The integrated circuit device according to claim 16, further comprising a second etch stop pattern located on the interlayer insulating layer in the memory cell region, the second etch stop pattern being spaced apart from an uppermost surface of the metal plate layer in the second direction and extending in the first direction, in, The second etch stop pattern and the first etch stop pattern include the same material as each other.

19. The integrated circuit device according to claim 18, in, The first etch stop pattern is completely surrounded by the interlayer insulating layer, and The second etch stop pattern is located on the interlayer insulating layer.

20. The integrated circuit device according to claim 18, in, The upper material layer includes a silicon germanium layer, The metal plate layer includes tungsten, The interlayer insulating layer includes silicon oxide, and Each of the second etch stop pattern and the first etch stop pattern includes at least one of amorphous silicon, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon germanium.

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