Nord flash memory manufacturing method
By utilizing anti-reflective coating and etching technology with different thicknesses in Nord flash manufacturing, the problem of polycrystalline silicon being overetched in flash manufacturing is solved, ensuring the protection of silicon oxide layer in the cell region and improving the accuracy of the manufacturing process Sex and stability.
Patent Information
- Application Number
- CN202411149723.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-21
- Publication Date
- 2024-12-13
AI Technical Summary
During Nord flash memory manufacturing, the surface is uneven due to the difference in the height of the oxide layer and the polysilicon after the word line polysilicon planarization, and the difference in the height of the flash memory cell region and logic region leads to poor uniformity of the photoresist layer before etching, which can easily lead to the The cell region control gate polysilicon and peripheral logic regions are damaged by overetching.
Coat the bottom anti-reflective coating on the semiconductor device to ensure that the thickness of the anti-reflective coating in the cell region exceeds the logic region, form an etching window and perform etching, and use the high etching selection ratio conditions of polysilicon vs. silicon oxide, and gradually The anti-reflective coating and silicon oxide of the logic region are removed to ensure that the drain region of the cell region is fully opened without damaging the polysilicon gate stack structure.
By using anti-reflective coatings and etching techniques with different thicknesses in Nord flash manufacturing, the silicon oxide layer in the cell region is protected from overetch damage to the polycrystalline silicon gate stacking structure in subsequent steps, improving the accuracy of the manufacturing process Sex and stability.
Smart Images
Figure CN119136551A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a method for manufacturing a Nord flash memory. Background Art
[0002] During the Nord flash memory manufacturing process, the surface is uneven due to the height difference between the oxide layer and the polysilicon layer after the word line polysilicon is planarized. In addition, the height difference between the flash memory cell area and the logic area leads to poor uniformity of the photoresist layer before etching, which can easily cause the cell area control gate polysilicon and the peripheral logic area to be damaged by over-etching. Summary of the invention
[0003] The present application provides a Nord flash memory manufacturing method, which can solve the problem in the related art that polysilicon is easily damaged by over-etching.
[0004] In order to solve the technical problem in the background technology, the present application provides a Nord flash memory manufacturing method, the Nord flash memory manufacturing method comprising the following steps:
[0005] Coating a bottom anti-reflection coating on the semiconductor device, wherein the bottom anti-reflection coating covers the bottom anti-reflection coating located on the peripheral logic area and has a smaller first thickness than the bottom anti-reflection coating located on the cell area;
[0006] Forming a photoresist layer with an etching window on the bottom anti-reflective coating, wherein the drain region of the cell region flash memory and the peripheral logic region are exposed from the position of the etching window;
[0007] Etching the bottom anti-reflection coating exposed from the etching window position, the bottom anti-reflection coating on the peripheral logic area is completely etched away, and the bottom anti-reflection coating on the drain region of the flash memory in the cell area remains with a second thickness;
[0008] Etching and pushing the semiconductor device exposed from the etching window position so that the thickness of silicon oxide on the polysilicon gate stack structure in the peripheral logic region is less than the thickness of silicon oxide on the polysilicon gate stack structure in the drain region of the cell region;
[0009] The semiconductor device exposed at the etching window position is etched using an etching condition in which polysilicon has a high etching selectivity ratio relative to silicon oxide, thereby completely opening the drain region of the cell region flash memory.
[0010] Optionally, the step of coating a bottom anti-reflective coating on the semiconductor device, wherein the bottom anti-reflective coating covers a cell region and a peripheral logic region of the flash memory; and the bottom anti-reflective coating on the peripheral logic region is less than a first thickness of the bottom anti-reflective coating on the cell region, comprises:
[0011] A bottom anti-reflective coating is coated on the semiconductor device, and the bottom anti-reflective coating covers the cell area and the peripheral logic area of the flash memory; the bottom anti-reflective coating located on the peripheral logic area is less than the first thickness of the bottom anti-reflective layer 100A to 200A located on the cell area.
[0012] Optionally, the step of etching the bottom anti-reflective coating exposed from the etching window position, wherein the bottom anti-reflective coating on the peripheral logic area is completely etched away, and the bottom anti-reflective coating on the drain region of the flash memory in the cell area remains with a second thickness, comprises:
[0013] The bottom anti-reflective coating exposed from the etching window position is etched, the bottom anti-reflective coating on the peripheral logic area is completely etched away, and the bottom anti-reflective coating on the drain area of the flash memory in the cell area remains with a second thickness of 100A to 200A.
[0014] Optionally, the step of etching the bottom anti-reflective coating exposed from the etching window position, wherein the bottom anti-reflective coating on the peripheral logic area is completely etched away, and the bottom anti-reflective coating on the drain region of the flash memory in the cell area remains with a second thickness, comprises:
[0015] The bottom anti-reflective coating exposed from the etching window position is etched under etching conditions having a high etching selectivity ratio for the bottom anti-reflective coating over silicon oxide, the bottom anti-reflective coating on the peripheral logic area is completely etched away, and the bottom anti-reflective coating on the drain region of the flash memory in the cell area remains with a second thickness.
[0016] Optionally, the step of etching and pushing the semiconductor device exposed from the etching window position so that the thickness of silicon oxide on the polysilicon gate stack structure in the peripheral logic region is less than the thickness of silicon oxide on the polysilicon gate stack structure in the drain region of the cell region includes:
[0017] The semiconductor device exposed from the etching window position is etched and pushed with the same etching selectivity ratio for silicon oxide and polysilicon, so that the silicon oxide thickness on the polysilicon gate stack structure in the peripheral logic area is less than the silicon oxide thickness on the polysilicon gate stack structure in the drain region of the cell area.
[0018] Optionally, after the step of etching and pushing the semiconductor device exposed from the etching window position so that the silicon oxide thickness on the polysilicon gate stack structure in the peripheral logic area is less than the silicon oxide thickness on the polysilicon gate stack structure in the drain region of the cell area is completed, the silicon oxide thickness on the polysilicon gate stack structure in the peripheral logic area is 100A to 200A, and the silicon oxide thickness on the polysilicon gate stack structure in the drain region of the cell area is 400A.
[0019] Optionally, the step of etching the semiconductor device exposed from the etching window position using an etching condition with a high etching selectivity ratio of polysilicon to silicon oxide to completely open the drain region of the cell region flash memory includes:
[0020] Using etching conditions with a high etching selectivity ratio of polysilicon to silicon oxide, the polysilicon exposed at the etching window position is etched away to completely open the drain region of the cell region flash memory.
[0021] The technical solution of the present application includes at least the following advantages: the thicker silicon oxide in the cell region can protect the polysilicon gate stack structure from being damaged by over-etching in subsequent steps. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0023] Figure 1 A schematic cross-sectional structure diagram of the semiconductor device provided in step S1 is shown;
[0024] Figure 2 A schematic diagram of a cross-sectional structure of the device after step S1 is completed is shown;
[0025] Figure 3 A schematic diagram of the cross-sectional structure of the device after step S2 is completed is shown;
[0026] Figure 4 A schematic diagram of the cross-sectional structure of the device after step S3 is completed is shown;
[0027] Figure 5 A schematic diagram of the cross-sectional structure of the device after step S4 is completed is shown;
[0028] Figure 6 A schematic diagram of the cross-sectional structure of the device after step S5 is completed is shown;
[0029] Figure 7 A flow chart of a method for manufacturing a Nord flash memory provided in an embodiment of the present application is shown. DETAILED DESCRIPTION
[0030] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0031] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0032] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0033] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0034] Figure 7 A flowchart of a method for manufacturing a Nord flash memory provided by an embodiment of the present application is shown. Figure 7 As can be seen, the Nord flash memory manufacturing method includes the following steps:
[0035] Step S1: coating a bottom anti-reflection layer on the semiconductor device, the bottom anti-reflection layer covering the cell area and the peripheral logic area of the flash memory. The thickness of the bottom anti-reflection layer on the peripheral logic area is less than the thickness of the bottom anti-reflection coating on the cell area, and the bottom anti-reflection layer on the peripheral logic area is less than the first thickness of the bottom anti-reflection coating on the cell area.
[0036] Figure 1The schematic cross-sectional structure diagram of the semiconductor device provided in step S1 is shown. Figure 1 It can be seen that the semiconductor device includes a cell region 110 and a peripheral logic region 120 of a flash memory. The semiconductor device includes a semiconductor substrate 100, a first oxide layer 101 is formed on the semiconductor substrate 100 of the cell region 110, and a second oxide layer 102 is formed on the semiconductor substrate 100 of the peripheral logic region 120, and the thickness of the second oxide layer 102 is greater than the thickness of the first oxide layer 101. A polysilicon gate stack structure 210 is formed on the first oxide layer 101, a source polysilicon 220 is formed at the source region between two adjacent polysilicon gate stack structures 210, and a drain polysilicon 230 is formed at the drain region on both sides of the two adjacent polysilicon gate stack structures 210. The polysilicon gate stack structure 210 includes a floating gate polysilicon layer, an inter-polysilicon dielectric layer, and a control gate polysilicon layer stacked sequentially from bottom to top. The upper parts of the drain polysilicon 230 and the source polysilicon 220 exceed the top of the control gate polysilicon layer, forming a space between the drain polysilicon 230 and the upper parts of the source polysilicon 220, and the third silicon oxide layer 103 fills the space between the drain polysilicon 230 and the source polysilicon 220, and the third silicon oxide layer 103 covers the control gate polysilicon layer.
[0037] Figure 2 The schematic diagram of the cross-sectional structure of the device after step S1 is completed is shown. Figure 2 It can be seen that Figure 1 The semiconductor device shown is coated with a bottom anti-reflection coating 300, which covers the cell area 110 and the peripheral logic area 120 of the flash memory, and the thickness of the bottom anti-reflection coating 300 located in the peripheral logic area 120 is less than the thickness of the bottom anti-reflection coating 300 located in the cell area 110 by a first thickness. Exemplarily, the first thickness may be 100A to 200A.
[0038] Step S2: forming a photoresist layer with an etching window on the bottom anti-reflective coating, wherein the drain region of the cell area flash memory and the peripheral logic region are exposed from the position of the etching window.
[0039] Reference Figure 3 , which shows a schematic diagram of the cross-sectional structure of the device after step S2 is completed, from Figure 3 As can be seen in the figure, a photoresist layer 400 with an etching window 410 is formed on the bottom anti-reflective coating 300 , the drain region of the cell area 110 flash memory is exposed from the 102 , and the peripheral logic area 120 is exposed from the position of the etching window 410 .
[0040] The drain region includes the area where the drain polysilicon 230 is located and a portion of the polysilicon gate stack structure 210 on both sides of the drain polysilicon 230 .
[0041] Step S3: etching the bottom anti-reflection coating exposed from the etching window position, the bottom anti-reflection coating on the peripheral logic area is completely etched away, and the bottom anti-reflection coating on the drain area of the flash memory in the cell area remains with a second thickness.
[0042] Reference Figure 4 , which shows a schematic diagram of the cross-sectional structure of the device after step S3 is completed. Figure 4 As can be seen from the figure, the bottom anti-reflective coating 300 exposed at the etching window 410 is etched, wherein the bottom anti-reflective coating 300 on the peripheral logic area is completely etched away. The bottom anti-reflective coating 300 on the drain region of the flash memory in the cell area 110 remains with a second thickness. Exemplarily, the second thickness is 100A to 200A.
[0043] Since the height of the peripheral logic region 120 is lower than that of the cell region 110, after the bottom anti-reflection coating 300 is applied, the thickness of the bottom anti-reflection coating 300 located on the peripheral logic region 120 is less than the thickness of the bottom anti-reflection coating 300 located on the cell region 110 by a first thickness. Then, after the bottom anti-reflection coating 30 exposed from the etching window 410 is integrally etched, the bottom anti-reflection coating 300 on the peripheral logic region is completely etched away, while the bottom anti-reflection coating 300 on the drain region of the flash memory in the cell region 110 remains with a second thickness.
[0044] Exemplarily, the bottom anti-reflective coating exposed from the etching window position can be etched under an etching condition having a high etching selectivity ratio for the bottom anti-reflective coating over silicon oxide, the bottom anti-reflective coating on the peripheral logic region is completely etched away, and the bottom anti-reflective coating on the drain region of the flash memory in the cell region remains with a second thickness. Under the etching condition, the bottom anti-reflective coating has a high etching selectivity ratio over silicon oxide, so that the etching rate of the bottom anti-reflective coating is greater than the etching rate of silicon oxide, so that after the bottom anti-reflective coating on the peripheral logic region is completely etched away, less etching is done on the first oxide layer located on the semiconductor substrate.
[0045] Step S4: Etching and pushing the semiconductor device exposed from the etching window position so that the silicon oxide thickness on the polysilicon gate stack structure in the peripheral logic area is less than the silicon oxide thickness on the polysilicon gate stack structure in the drain region of the cell area.
[0046] Exemplarily, the semiconductor device exposed from the etching window position can be etched and pushed with the same etching selectivity ratio for silicon oxide and polysilicon, so that the silicon oxide thickness on the polysilicon gate stack structure in the peripheral logic area is less than the silicon oxide thickness on the polysilicon gate stack structure in the drain region of the cell area.
[0047] Reference Figure 5 , which shows a schematic diagram of the cross-sectional structure of the device after step S4 is completed. Figure 5 It can be seen that the semiconductor device exposed from the etching window 410 is pushed flat, so that the polysilicon and silicon oxide exposed from the etching window 410 are etched and removed at the same etching rate, including the drain polysilicon 230 at the drain region and the silicon oxide on the polysilicon gate stack structure 210 exposed from the etching window 410, as well as the drain polysilicon of the peripheral logic area 120 and the silicon oxide on the polysilicon gate stack structure.
[0048] Since the bottom anti-reflective coating 300 on the peripheral logic region is completely etched away, while the bottom anti-reflective coating 300 on the drain region of the flash memory in the cell region 110 has a second thickness remaining, after etching and pushing the semiconductor device exposed from the etching window position, the silicon oxide thickness on the polysilicon gate stack structure in the peripheral logic region 120 is smaller than the silicon oxide thickness on the polysilicon gate stack structure in the drain region of the cell region 100. Therefore, the thicker silicon oxide in the cell region 100 can protect the polysilicon gate stack structure from being damaged by over-etching in subsequent steps.
[0049] Step S5: etching the semiconductor device exposed from the etching window position using an etching condition with a high etching selectivity ratio of polysilicon to silicon oxide, and completely opening the drain region of the cell region flash memory.
[0050] After step S4 is completed, the height of the semiconductor device located on the peripheral logic area 120 is smaller than the height of the semiconductor device located on the cell area 110. Therefore, after the semiconductor device exposed from the etching window position is etched under the etching condition that polysilicon has a high etching selectivity ratio with respect to silicon oxide, the remaining drain polysilicon is completely etched and removed, and the control gate polysilicon layer of the polysilicon gate stack structure will not be damaged.
[0051] Reference Figure 6 , which shows a schematic diagram of the cross-sectional structure of the device after step S5 is completed. Figure 6 It can be seen from the figure that the drain polysilicon in the drain region of the cell area 110 flash memory is completely etched away, and the drain polysilicon in the drain region of the cell area flash memory is completely etched away.
[0052] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A method for manufacturing Nord flash memory, It is characterized in that The Nord flash memory manufacturing method comprises the following steps: Coating a bottom anti-reflection coating on the semiconductor device, wherein the bottom anti-reflection coating covers the bottom anti-reflection coating located on the peripheral logic area and has a smaller first thickness than the bottom anti-reflection coating located on the cell area; Forming a photoresist layer with an etching window on the bottom anti-reflective coating, wherein the drain region of the cell region flash memory and the peripheral logic region are exposed from the position of the etching window; Etching the bottom anti-reflection coating exposed from the etching window position, the bottom anti-reflection coating on the peripheral logic area is completely etched away, and the bottom anti-reflection coating on the drain region of the flash memory in the cell area remains with a second thickness; Etching and pushing the semiconductor device exposed from the etching window position so that the thickness of silicon oxide on the polysilicon gate stack structure in the peripheral logic region is less than the thickness of silicon oxide on the polysilicon gate stack structure in the drain region of the cell region; The semiconductor device exposed at the etching window position is etched using an etching condition in which polysilicon has a high etching selectivity ratio relative to silicon oxide, thereby completely opening the drain region of the cell region flash memory.
2. The method for manufacturing a Nord flash memory according to claim 1, It is characterized in that The bottom anti-reflection coating is coated on the semiconductor device, and the bottom anti-reflection coating covers the cell area and the peripheral logic area of the flash memory; The step of providing a bottom anti-reflection coating layer on the peripheral logic region with a thickness less than a first thickness of the bottom anti-reflection coating layer on the cell region comprises: Coating a bottom anti-reflective coating on the semiconductor device, wherein the bottom anti-reflective coating covers a cell region and a peripheral logic region of the flash memory; The bottom anti-reflection coating layer on the peripheral logic region is smaller than the first thickness of the bottom anti-reflection layers 100A to 200A on the cell region.
3. The method for manufacturing a Nord flash memory according to claim 1, It is characterized in that The step of etching the bottom anti-reflective coating exposed from the etching window position, wherein the bottom anti-reflective coating on the peripheral logic area is completely etched away, and the bottom anti-reflective coating on the drain region of the flash memory in the cell area remains with a second thickness, comprises: The bottom anti-reflective coating exposed from the etching window position is etched, the bottom anti-reflective coating on the peripheral logic area is completely etched away, and the bottom anti-reflective coating on the drain area of the flash memory in the cell area remains with a second thickness of 100A to 200A.
4. The method for manufacturing a Nord flash memory according to claim 1, It is characterized in that The step of etching the bottom anti-reflective coating exposed from the etching window position, wherein the bottom anti-reflective coating on the peripheral logic area is completely etched away, and the bottom anti-reflective coating on the drain region of the flash memory in the cell area remains with a second thickness, comprises: The bottom anti-reflective coating exposed from the etching window position is etched under etching conditions having a high etching selectivity ratio for the bottom anti-reflective coating over silicon oxide, the bottom anti-reflective coating on the peripheral logic area is completely etched away, and the bottom anti-reflective coating on the drain region of the flash memory in the cell area remains with a second thickness.
5. The method for manufacturing a Nord flash memory according to claim 1, It is characterized in that The step of etching and pushing the semiconductor device exposed from the etching window position so that the thickness of silicon oxide on the polysilicon gate stack structure in the peripheral logic region is less than the thickness of silicon oxide on the polysilicon gate stack structure in the drain region of the cell region comprises: The semiconductor device exposed from the etching window position is etched and pushed with the same etching selectivity ratio for silicon oxide and polysilicon, so that the silicon oxide thickness on the polysilicon gate stack structure in the peripheral logic area is less than the silicon oxide thickness on the polysilicon gate stack structure in the drain region of the cell area.
6. The method for manufacturing a Nord flash memory according to claim 1, It is characterized in that After the step of etching and pushing the semiconductor device exposed from the etching window position so that the silicon oxide thickness on the polysilicon gate stack structure in the peripheral logic area is less than the silicon oxide thickness on the polysilicon gate stack structure in the drain region of the cell area is completed, the silicon oxide thickness on the polysilicon gate stack structure in the peripheral logic area is 100A to 200A, and the silicon oxide thickness on the polysilicon gate stack structure in the drain region of the cell area is 400A.
7. The method for manufacturing a Nord flash memory according to claim 1, It is characterized in that The step of etching the semiconductor device exposed from the etching window position using an etching condition with a high etching selectivity ratio of polysilicon to silicon oxide to completely open the drain region of the cell region flash memory comprises: Using etching conditions with a high etching selectivity ratio of polysilicon to silicon oxide, the polysilicon exposed at the etching window position is etched away to completely open the drain region of the cell region flash memory.