SOT-MRAM structure, full-electric-control write-in device and preparation method

Abstract

The invention relates to an SOT-MRAM structure, a full-electric-control write-in device and a preparation method, belongs to the technical field of semiconductor devices, and solves the problems of high energy consumption and incapability of high-density integration caused by the fact that an existing MRAM with a PMA needs an external magnetic field to realize deterministic SOT magnetic field overturning. The SOT-MRAM structure comprises a magnetic tunnel junction, a magnetic layer used for providing a horizontal magnetic field for the magnetic tunnel junction is arranged in the magnetic tunnel junction, and the magnetic tunnel junction comprises a bottom electrode layer, a free layer, a tunneling layer, a reference layer, a middle layer, a first pinning layer, a protective layer, a magnetic layer and a hard mask layer which are sequentially arranged from bottom to top.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a SOT-MRAM structure, a fully electrically controlled writing device and a preparation method thereof. Background Art

[0002] Magnetic random access memory (MRAM) is a new type of non-volatile memory that stores information by the magnetization direction of two ferromagnetic layers. In recent years, the spin orbit torque (SOT) effect driven by in-plane current has become a key technology for the next generation of MRAM writing. The main structure of the SOT-MRAM device consists of a four-layer magnetic tunnel junction (MTJ), namely: free layer, reference layer, tunneling oxide and bottom electrode layer.

[0003] SOT is generated by applying an in-plane current of a non-magnetic / magnetic double layer, and MRAM with perpendicular magnetic anisotropy (PMA) provides good thermal stability and scalability. However, MRAM with PMA usually requires an additional magnetic field to achieve deterministic SOT magnetic field switching, which results in huge energy consumption.

[0004] The existing technology solves the problem of high energy consumption by setting a magnetic layer outside the tunnel junction. However, since the magnetic layer outside the tunnel junction is far away from the free layer inside the tunnel junction, on the one hand, the energy consumption is still very high, greater than 100 picojoules; on the other hand, in order to provide a sufficiently strong magnetic field, a very thick magnetic layer (usually tens of nanometers thick) is required, resulting in a large device size and therefore cannot be integrated at a high density. Summary of the invention

[0005] In view of the above analysis, the present invention aims to provide a SOT-MRAM structure, a fully electrically controlled writing device and a preparation method, so as to solve the problem that the existing MRAM with PMA requires an external magnetic field to achieve deterministic SOT magnetic field switching, resulting in high energy consumption and inability to be integrated with high density.

[0006] The purpose of the present invention is mainly achieved through the following technical solutions:

[0007] In a first aspect, the present invention provides a SOT-MRAM structure, including a magnetic tunnel junction, wherein a magnetic layer for providing a horizontal magnetic field for the magnetic tunnel junction is provided inside the magnetic tunnel junction, and the magnetic tunnel junction includes a bottom electrode layer, a free layer, a tunneling layer, a reference layer, an intermediate layer, a first pinned layer, a protective layer, a magnetic layer and a hard mask layer arranged in sequence from bottom to top.

[0008] Furthermore, it also includes a second pinning layer, which is used to pin the magnetic layer to a fixed direction; the second pinning layer is arranged between the magnetic layer and the hard mask layer.

[0009] Furthermore, it also includes a second pinning layer, which is used to pin the magnetic layer to a fixed direction; the second pinning layer is arranged between the magnetic layer and the protective layer.

[0010] Furthermore, the thickness of the second pinning layer is 7-15 nm.

[0011] Furthermore, the material of the second pinning layer is PtMn or IrMn.

[0012] Furthermore, the material of the magnetic layer is FeCo alloy.

[0013] Furthermore, the material of the tunneling layer is MgO, and the thickness is 0.5-3 nm.

[0014] In a second aspect, the present invention provides a SOT-MRAM fully electrically controlled writing device, comprising the above-mentioned SOT-MRAM structure.

[0015] Furthermore, the energy consumption of the SOT-MRAM fully electrically controlled write device is less than 10 picojoules per bit.

[0016] In a third aspect, the present invention further provides a method for preparing a magnetic tunnel junction in the above-mentioned SOT-MRAM structure, comprising the following steps:

[0017] Step 1: depositing a bottom electrode layer, a free layer, a tunneling layer, a reference layer, an intermediate layer, a first pinning layer, a protective layer, a magnetic layer, a second pinning layer and a hard mask layer on a Si wafer or a circuit wafer in sequence to obtain a tunnel junction;

[0018] Step 2: annealing the tunnel junction obtained in step 1 under a horizontal magnetic field;

[0019] Step 3: Processing tunnel junction;

[0020] Step 4: Protect the processed tunnel junction deposited dielectric;

[0021] Step 5: Processing the top electrode and the bottom electrode;

[0022] Step 6: Perform metal interconnection to obtain a SOT-MRAM structure.

[0023] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0024] (1) The present invention grows a magnetic layer inside the tunnel junction, and the magnetic moment M of the magnetic layer is in a horizontal direction and is pinned to a fixed direction by a pinning layer. The leakage magnetic field of the magnetic layer provides a horizontal magnetic field H to the tunnel junction, and no additional magnetic field is required to achieve a deterministic SOT magnetic field reversal, thus helping to reduce device energy consumption.

[0025] (2) Since the magnetic layer of the present invention is disposed inside the tunnel junction and is very close to the free layer in the tunnel junction, on the one hand, the energy consumption of the device can be further reduced (the energy consumption is less than 10 pJ / bit); on the other hand, a very strong magnetic field can be provided when the thickness of the magnetic layer is very thin, which is conducive to reducing the thickness of the magnetic layer. Specifically, the thickness of the magnetic layer of the present invention is only a few nanometers or a dozen nanometers. Since the thickness of the magnetic layer is very thin, the volume of the tunnel junction can be reduced, and then the volume of the device can be reduced, which is convenient for high-density integration of the device.

[0026] (3) The present invention adopts a [W / Ta] multilayer film structure composed of three materials, W, T and W3Ta, as the bottom electrode layer, so that the bottom electrode has a higher spin Hall conversion rate and a lower resistivity, which can further reduce energy consumption. In addition, the bottom electrode of the [W / Ta] multilayer film structure with W3Ta as the component at the interface still has stable performance in high-temperature annealing at 400°C and has very good perpendicular magnetic anisotropy (Ku~10 7 erg / cc).

[0027] (4) The present invention is compatible with CMOS technology and does not require the development of new technology, which is beneficial to reducing production costs.

[0028] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can be obvious from the description or understood by practicing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings are only for the purpose of illustrating specific embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0030] Figure 1 A schematic diagram of a SOT-MRAM structure according to an embodiment of the present invention;

[0031] Figure 2 A schematic diagram of a SOT-MRAM structure according to another embodiment of the present invention;

[0032] Figure 3 A schematic diagram of the structure of the bottom electrode of the [W / Ta] multilayer film structure deposited by the present invention;

[0033] Figure 4It is a schematic diagram of the structure of the bottom electrode after annealing of the [W / Ta] multilayer film structure of the present invention. DETAILED DESCRIPTION

[0034] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of the present invention and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0035] In a first aspect, the present invention provides a SOT-MRAM structure, such as Figure 1 and Figure 2 As shown, it includes a magnetic tunnel junction, and a magnetic layer for providing a horizontal magnetic field for the magnetic tunnel junction is provided inside the magnetic tunnel junction. The magnetic tunnel junction includes a bottom electrode layer, a free layer, a tunneling layer, a reference layer, an intermediate layer, a first pinned layer, a protective layer, a magnetic layer and a hard mask layer arranged in sequence from bottom to top, that is, the free layer is arranged on the bottom electrode layer, the tunneling layer is arranged on the free layer, the reference layer is arranged on the tunneling layer, the intermediate layer is arranged on the reference layer, the first pinned layer is arranged on the intermediate layer, the protective layer is arranged on the first pinned layer, the magnetic layer is arranged on the protective layer, and the hard mask layer is arranged on the magnetic layer.

[0036] Specifically, the material of the bottom electrode layer is W, Ta, etc., and the thickness is 5-10 nm, for example, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm.

[0037] In a preferred embodiment, Figure 3 As shown, the material of the bottom electrode layer is not a single W or Ta, but a [W / Ta] multilayer film structure.

[0038] It should be noted that in the [W / Ta] multilayer film structure, the first layer (the bottom layer) can be either W or Ta, and the top layer (close to the free layer side) must be a W layer. This is because: compared with the top layer being a Ta layer, the perpendicular magnetic anisotropy of the device with the top layer being a W layer is better. Preferably, the bottom electrode layer is 5 layers, that is, three layers of W and two layers of Ta are arranged alternately.

[0039] In addition, the total thickness of the multiple W layers is 4 times the total thickness of the multiple Ta layers. After annealing, the composition at the interface between the W layer and the Ta layer is W3Ta (see Figure 4 ). Specifically, the thickness of the W layer is 1-3 nm, and the thickness of the Ta layer is 0.5-1 nm.

[0040] The present invention controls the total thickness of multiple W layers and multiple Ta layers to a specific ratio (4:1) so that the bottom electrode layer has a higher spin Hall conversion rate. Specifically, when the material of the bottom electrode layer is a single W or Ta, the spin Hall conversion rate of the bottom electrode is only 10%-30%, while the spin Hall conversion rate of the bottom electrode of the [W / Ta] multilayer film structure with W3Ta as the component at the interface is 50%.

[0041] In a preferred embodiment, both W and Ta are not single phases, but a mixture of α and β phases, that is, the W layer is a mixture of α and β phases, and the Ta layer is a mixture of α and β phases. The present invention can provide low resistivity and reduce the resistivity of the bottom electrode layer by using a mixture of α and β phases for the W layer and the Ta layer. Specifically, when the material of the bottom electrode layer is a single W or Ta, the resistivity of the bottom electrode is 200μΩ·cm, while the resistivity of the bottom electrode of the [W / Ta] multilayer film structure with the composition of W3Ta at the interface is 90μΩ·cm.

[0042] Compared with the existing bottom electrode layer, which is made of a single W or Ta material, the bottom electrode of the [W / Ta] multilayer film structure, which is a combination of three materials (W, T and W3Ta), has a higher spin Hall conversion rate, lower resistivity, and can greatly reduce energy consumption. In addition, when the material of the bottom electrode layer is a single W or Ta, the performance stability is poor during the subsequent high-temperature annealing (350-400°C), and the perpendicular magnetic anisotropy of the device is poor. However, the bottom electrode of the [W / Ta] multilayer film structure, whose component at the interface is W3Ta, still has stable performance during the high-temperature annealing at 400°C, and has very good perpendicular magnetic anisotropy (Ku~10 7 erg / cc).

[0043] The material of the free layer is CoFeB, and the thickness is 0.5-3 nm, for example, 0.5 nm, 0.7 nm, 0.9 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm.

[0044] The material of the tunneling layer is MgO, and the thickness is 0.5-3 nm, for example, 0.5 nm, 0.7 nm, 0.9 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm.

[0045] The material of the reference layer is CoFeB and the thickness of the reference layer is about 1 nm.

[0046] The material of the intermediate layer is a non-magnetic material, such as W. The thickness of the intermediate layer is 0.6-0.8 nm, for example, 0.6 nm, 0.7 nm, 0.8 nm.

[0047] It should be noted that the first pinning layer is used to pin the reference layer to a fixed direction, and its material is a CoPt multilayer film with a thickness of 10-15 nm, for example, 10 nm, 12 nm, 14 nm, 15 nm.

[0048] The function of the protective layer is to protect the MRAM structure from the external environment and prevent oxidation and other chemical reactions. The material of the protective layer is Ru, and the thickness is 4nm, for example, 2nm, 3nm, 4nm.

[0049] The material of the magnetic layer is FeCo alloy, and the thickness is 8 to 16 nm, for example, 8 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, and 16 nm.

[0050] The material of the hard mask layer is TiN or Ta, and the thickness is 80-110 nm, for example, 80 nm, 90 nm, 95 nm, 100 nm, 105 nm, or 110 nm.

[0051] It should be noted that the SOT-MRAM structure of the present invention further includes a second pinning layer for pinning the magnetic layer to a fixed direction, such as Figure 1 and Figure 2 As shown, the second pinning layer is disposed between the magnetic layer and the hard mask layer, or between the magnetic layer and the protective layer.

[0052] Specifically, the thickness of the second pinning layer is 7-15 nm, for example, 7 nm, 9 nm, 10 nm, 12 nm, 14 nm, 15 nm. The material of the second pinning layer is PtMn or IrMn.

[0053] In a second aspect, the present invention further provides a method for preparing a SOT-MRAM structure, which is used to prepare the above-mentioned SOT-MRAM structure, comprising the following steps:

[0054] Step 1: depositing a bottom electrode layer, a free layer, a tunneling layer, a reference layer, an intermediate layer, a first pinning layer, a protective layer, a magnetic layer, a second pinning layer and a hard mask layer on a Si wafer or a circuit wafer in sequence to obtain a tunnel junction;

[0055] Step 2: annealing the tunnel junction obtained in step 1 under a horizontal magnetic field;

[0056] Step 3: Processing tunnel junction;

[0057] Step 4: Protect the processed tunnel junction deposited dielectric;

[0058] Step 5: Processing the top electrode and the bottom electrode;

[0059] Step 6: Perform metal interconnection to obtain a SOT-MRAM structure.

[0060] Specifically, in step 1, depositing the bottom electrode layer includes: depositing a W layer, a Ta layer, a W layer, a Ta layer, a W layer, a Ta layer, a W layer, a Ta layer and a W layer in sequence on a Si wafer or a circuit wafer.

[0061] Specifically, the effects of annealing in step 2 are: first, fixing the magnetic moment direction of the magnetic layer; second, enhancing the atomic diffusion at the interface between W and Ta to form a W / W3Ta / Ta multilayer film alloy.

[0062] The annealing temperature is 350-400°C, for example, 350°C, 360°C, 370°C, 380°C, 390°C, 400°C.

[0063] The annealing time is 0.5-3h, for example, 0.5h, 1h, 1.5h, 2, 2.5h, 3h.

[0064] Specifically, step 3 includes: etching the tunnel junction, the etching stops at the tunnel layer or the bottom electrode layer; then, etching the hard mask using a reaction gas; and then etching the tunnel junction using the hard mask in an Ar atmosphere.

[0065] Specifically, in step 4, the deposited medium is SiN, and the thickness is 30-60 nm, for example, 30 nm, 40 nm, 50 nm, 60 nm.

[0066] Specifically, in step 5, the top electrode and the bottom electrode are exposed by using a CMP method.

[0067] It should be pointed out that, unless otherwise specified, the processes and process parameters involved in the preparation method of the present invention all adopt the existing technology.

[0068] In a third aspect, the present invention further provides a SOT-MRAM fully electrically controlled writing device, comprising the above-mentioned SOT-MRAM structure. The device has an energy consumption of less than 10 pJ / bit, a small size, and is convenient for high-density integration of the device.

[0069] Example 1

[0070] Step 1: deposit a bottom electrode layer (W, 5 nm), a free layer (CoFeB, 0.5 nm), a tunneling layer (MgO, 0.5 nm), a reference layer (CoFeB, 1 nm), an intermediate layer (W, 0.6 nm), a first pinning layer (CoPt multilayer film, 10 nm), a protective layer (Ru, 2 nm), a magnetic layer (FeCo, 8 nm), a second pinning layer (PtMn, 7 nm) and a hard mask layer (TiN, 80 nm) on a Si wafer in sequence to obtain a tunnel junction;

[0071] Step 2: Anneal the tunnel junction obtained in step 1 in a horizontal magnetic field (0.5 T) (350° C., 3 h);

[0072] Step 3: Etching the tunnel junction, where the etching stops at the tunnel layer; then, etching the hard mask using the reaction gas; and then etching the tunnel junction using the hard mask in an Ar atmosphere;

[0073] Step 4: depositing SiN dielectric (30 nm thick) on the processed tunnel junction;

[0074] Step 5: CMP method leaks out the top electrode and the bottom electrode;

[0075] Step 6: Perform metal interconnection to obtain a SOT-MRAM structure.

[0076] Example 2

[0077] Step 1: depositing a bottom electrode layer (Ta, 10nm), a free layer (CoFeB, 3nm), a tunneling layer (MgO, 3nm), a reference layer (CoFeB, 1nm), an intermediate layer (W, 0.8nm), a first pinning layer (CoPt multilayer film, 15nm), a protective layer (Ru, 4nm), a magnetic layer (FeCo, 16nm), a second pinning layer (IrMn, 15nm) and a hard mask layer (Ta, 110nm) on the circuit chip in sequence to obtain a tunnel junction;

[0078] Step 2: annealing the tunnel junction obtained in step 1 in a horizontal magnetic field (0.5 T) (400° C., 0.5 h);

[0079] Step 3: Etching the tunnel junction, the etching stops at the bottom electrode layer; then, etching the hard mask using the reaction gas; then etching the tunnel junction using the hard mask in an Ar atmosphere;

[0080] Step 4: depositing SiN dielectric (thickness 60 nm) on the processed tunnel junction;

[0081] Step 5: CMP method leaks out the top electrode and the bottom electrode;

[0082] Step 6: Perform metal interconnection to obtain a SOT-MRAM structure.

[0083] Example 3

[0084] Step 1: Deposit the bottom electrode layer (W, 7nm), free layer (CoFeB, 1nm), tunneling layer (MgO, 1nm), reference layer (CoFeB, 1nm), intermediate layer (W, 0.7nm), first pinning layer (CoPt multilayer, 12nm), protective layer (Ru, 3nm), magnetic layer (FeCo, 10nm), second pinning layer (PtMn, 10nm) and hard mask layer (TiN, 100nm) on the Si wafer in sequence to obtain a tunnel junction;

[0085] Step 2: annealing the tunnel junction obtained in step 1 in a horizontal magnetic field (0.5 T) (370° C., 1 h);

[0086] Step 3: Etching the tunnel junction, where the etching stops at the tunnel layer; then, etching the hard mask using the reaction gas; and then etching the tunnel junction using the hard mask in an Ar atmosphere;

[0087] Step 4: depositing SiN dielectric (thickness 45 nm) on the processed tunnel junction;

[0088] Step 5: CMP method leaks out the top electrode and the bottom electrode;

[0089] Step 6: Perform metal interconnection to obtain a SOT-MRAM structure.

[0090] Example 4

[0091] This embodiment is basically the same as the embodiment 1, except that the second pinning layer is located between the protection layer and the magnetic layer.

[0092] Example 5

[0093] This embodiment is basically the same as Embodiment 1, except that the bottom electrode layer deposited in Step 1 is a multilayer film structure of W (1.25nm), Ta (0.5nm), W (1.25nm), Ta (0.5nm), and W (1.5nm).

[0094] In addition, the present invention also tests the spin Hall conversion rate and resistivity of the bottom electrode materials in Examples 1-5 and the energy consumption of the devices, and the results are listed in Table 1.

[0095] Table 1 Spin Hall conversion efficiency, resistivity and device energy consumption of the bottom electrode

[0096]

[0097] It can be seen from Table 1 that the spin Hall conversion rate of the bottom electrode using a [W / Ta] multilayer film structure (Example 5) is significantly higher than that of the bottom electrode using a single W or Ta (Examples 1-4), while the resistivity is significantly lower than that of the bottom electrode using a single W or Ta, thereby making the energy consumption of the device significantly lower than that of the device using a single W or Ta bottom electrode.

[0098] In addition, it can be seen from Table 1 that the energy consumption of the devices in the embodiments of the present invention is less than 10 pJ / bit, while the energy consumption of the device in the prior art after the magnetic layer is set outside the tunnel junction is greater than 100 pJ, which proves that the structural design of growing the magnetic layer inside the tunnel junction can reduce the energy consumption of the device.

[0099] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A SOT-MRAM structure, characterized in that: It includes a magnetic tunnel junction, a magnetic layer for providing a horizontal magnetic field for the magnetic tunnel junction is provided inside the magnetic tunnel junction, and the magnetic tunnel junction includes a bottom electrode layer, a free layer, a tunnel layer, a reference layer, an intermediate layer, a first pinned layer, a protective layer, a magnetic layer and a hard mask layer arranged in sequence from bottom to top.

2. The SOT-MRAM structure according to claim 1, wherein: Also included is a second pinning layer, the second pinning layer being used to pin the magnetic layer to a fixed direction; The second pinning layer is disposed between the magnetic layer and the hard mask layer.

3. The SOT-MRAM structure according to claim 1, wherein: Also included is a second pinning layer, the second pinning layer being used to pin the magnetic layer to a fixed direction; The second pinning layer is disposed between the magnetic layer and the protection layer.

4. The SOT-MRAM structure according to claim 2, wherein: The thickness of the second pinning layer is 7-15 nm.

5. The SOT-MRAM structure according to claim 4, wherein: The material of the second pinning layer is PtMn or IrMn.

6. The SOT-MRAM structure according to claim 1, wherein: The material of the magnetic layer is FeCo alloy.

7. The SOT-MRAM structure according to claim 1, wherein: The tunneling layer is made of MgO and has a thickness of 0.5-3 nm.

8. A SOT-MRAM fully electrically controlled write device, characterized in that: The SOT-MRAM structure comprises the SOT-MRAM structure according to any one of claims 1 to 7.

9. The fully electrically controlled writing device according to claim 8, characterized in that: Its energy consumption is less than 10 picojoules per bit.

10. A method for preparing a magnetic tunnel junction in a SOT-MRAM structure according to any one of claims 1 to 7, characterized in that: The following steps are involved: Step 1: Deposit a bottom electrode layer, a free layer, a tunneling layer, a reference layer, an intermediate layer, a first pinning layer, a protective layer, a magnetic layer, a second pinning layer and a hard mask layer on a Si wafer or a circuit chip in sequence to obtain a tunnel junction; Step 2: Annealing the tunnel junction obtained in step 1 under a horizontal magnetic field; Step 3: Processing tunnel junction; Step 4: Protect the deposited dielectric of the processed tunnel junction; Step 5: Processing the top electrode and the bottom electrode; Step 6: Perform metal interconnection to obtain the SOT-MRAM structure.

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