Data processing method and device for multiplication, electronic equipment and medium

Abstract

The invention provides a data processing method and device for multiplication, electronic equipment and a medium. The data processing method comprises the steps that the bit width and the preset bit width of an operation operand to be subjected to multiplication are determined; processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and a preset bit width; and carrying out multiplication operation by using the operation operands after bit width processing. By the adoption of the technical scheme, the problem that a large number of resources are consumed during multiplication is solved.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a data processing method, device, electronic equipment and medium for multiplication operation. Background Art

[0002] In the fields of image processing, speech coding, and artificial intelligence (AI) accelerators, accumulative multiplication operations are often performed. In the hardware implementation process, it is often the case that the bit width of the operation operand is too large and the target bit width is insufficient to meet the bit width of the operation operand. In this case, the operation result will be saturated and truncated. However, in this process, a large amount of resources will be consumed when the operation operand is multiplied.

[0003] In view of the problem in the prior art that a large amount of resources are wasted when performing multiplication operations on operands, no effective solution has been proposed so far. Summary of the invention

[0004] The present invention provides a data processing method, device, electronic device and medium for multiplication operation, which are used to solve the problem in the prior art that a large amount of resources will be consumed when performing multiplication operation on operation operands, and the loss of resources during the multiplication operation is reduced by performing bit width processing on the operation operands in advance.

[0005] In a first aspect, the present invention provides a data processing method for multiplication operation, comprising: Determining the bit width of the operation operand to be multiplied and the preset bit width; Processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width; Perform multiplication using the bit-width processed operands.

[0006] Optionally, processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: When the bit width of the operation operand is greater than the maximum boundary value of the preset bit width or less than the minimum boundary value of the preset bit width, the bit width of the operation operand is processed according to the size relationship between the bit width of the operation operand and the preset bit width.

[0007] Optionally, processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first operation operand and a second operation operand; exist When both the first and second operands are signed data, the bit width of the first operand is reduced to , reducing the bit width of the second operand to ; exist When both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand is reduced to , reducing the bit width of the second operand to ; in, is the bit width of the first operation operand, is the bit width of the second operation operand, The preset width.

[0008] Optionally, processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first operation operand and a second operation operand; exist When both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand is reduced to , reducing the bit width of the second operand to ; exist When both the first and second operands are signed data, the bit width of the first operand is reduced to , reducing the bit width of the second operand to ; exist When both the first and second operands are signed data, the bit width of the first operand is reduced to , reducing the bit width of the second operation to ; exist When both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand is reduced to ; exist When both the first and second operands are signed data, the bit width of the first operand is reduced to ; in, is the bit width of the first operation operand, is the bit width of the second operation operand, The preset width.

[0009] Optionally, processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first operation operand and a second operation operand; exist When both the first and second operands are signed data, the bit width of the first operand is reduced to , reducing the bit width of the second operand to ; exist When both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand is reduced to , reducing the bit width of the second operand to ; in, is the bit width of the first operation operand, is the bit width of the second operation operand, The preset width.

[0010] Optionally, the method further comprises: The operation operands include a first operation operand and a second operation operand; exist When both the first operation operand and the second operation operand are signed data, the bit widths of the first operation operand and the second operation operand remain unchanged; exist When both the first operation operand and the second operation operand are unsigned data, the bit widths of the first operation operand and the second operation operand remain unchanged; exist When both the first operation operand and the second operation operand are signed data, the bit widths of the first operation operand and the second operation operand remain unchanged; in, is the bit width of the first operation operand, is the bit width of the second operation operand, The preset width.

[0011] In a second aspect, the present invention provides a data processing device for multiplication operation, comprising: A determination module, used to determine the bit width of the operation operand to be multiplied and the preset bit width; A first processing module, used for processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width; The second processing module is used to perform a multiplication operation using the operation operands after bit width processing.

[0012] In a third aspect, the present invention further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the processor implements any of the above-mentioned data processing methods for multiplication operations.

[0013] In a fourth aspect, the present invention further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements any of the above-mentioned data processing methods for multiplication operations.

[0014] In a fifth aspect, the present invention further provides a computer program product, comprising a computer program, which, when executed by a processor, implements any of the above-mentioned data processing methods for multiplication operations.

[0015] The data processing method, device, electronic device and medium for multiplication operation provided by the present invention process the bit width of the operation operand to be multiplied by determining the size relationship between the bit width of the operation operand to be multiplied and the preset bit width, and use the operation operand after the bit width processing to perform the multiplication operation. The problem that the operation operand in the prior art consumes a lot of resources when performing the multiplication operation is solved, and the loss of resources in the multiplication operation process is reduced by performing the bit width processing on the operation operand in advance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 It is a flow chart of a data processing method for multiplication operation provided by the present invention.

[0018] Figure 2 It is a schematic diagram of the working principle of the multiplier provided by the present invention.

[0019] Figure 3 This is one of the flowcharts of bit width reduction provided by the present invention.

[0020] Figure 4 This is the second schematic diagram of the process of bit width reduction provided by the present invention.

[0021] Figure 5 This is the third schematic diagram of the process of bit width reduction provided by the present invention.

[0022] Figure 6 It is a structural schematic diagram of a data processing device for multiplication operation provided by the present invention.

[0023] Figure 7 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0024] In the present invention, the term "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0025] In the present invention, the term "plurality" refers to two or more than two, and other quantifiers are similar to them.

[0026] In the present invention, the terms "first", "second", etc. are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0027] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] Figure 1 is a flow chart of a data processing method for multiplication operation provided by the present invention, such as Figure 1 As shown, the method includes the following steps S101-S103: Step S101: Determine the bit width of the operation operand to be multiplied and the preset bit width.

[0029] It should be noted that the preset bit width can be the bit width of the multiplier, or the bit width of any multiplication function module, or the actual required bit width in the process of data operation and other processing (such as image data processing). The preset bit width here can also be understood as the bit width of the hardware device related to image processing when the result of the multiplication operation is the input of the hardware device related to image processing. Since the bit width of the hardware device related to the image processing is limited (some hardware devices cannot handle too large a bit width), it is necessary to reduce the bit width of the operation operand before the multiplication operation to avoid the problem of operation failure due to exceeding the processing capacity of the hardware device related to image processing. The specific type of preset bit width is not further limited in the present invention. The embodiment of the present invention is not further limited in this. Based on this, the present invention can be directly applied in a multiplier, and can also be used in a device with a multiplication function module in the field of image processing, and the embodiment of the present invention is not further limited in this. The preset bit width can be flexibly set according to the application scenario and device hardware support.

[0030] It should be noted that, in combination with the properties of the multiplication operation, the number of operation operands is at least two. In actual application, the present invention does not further limit the specific number of operation operands.

[0031] For ease of explanation, the present invention is further explained below in a scenario of a multiplier operation with two operation operands.

[0032] As an optional embodiment, Figure 2 As shown in the figure, the first operation operand is Input1, the second operation operand is Input2, the bit width of the first operation operand is m, the bit width of the second operation operand is n, and the preset bit width of the multiplier is r.

[0033] In an exemplary embodiment, when the bit width of an operation operand is greater than a maximum boundary value of a preset bit width or less than a minimum boundary value of a preset bit width, the bit width of the operation operand is processed according to the size relationship between the bit width of the operation operand and the preset bit width.

[0034] As an optional embodiment, the preset bit width can be a preset bit width of a multiplier. The preset bit width of the multiplier is 8-16 bits, the bit width of the first operation operand is 20 bits, and the bit width of the second operation operand is 4 bits. At this time, the bit width of the first operation operand is greater than the maximum boundary value of the preset bit width, and the bit width of the second operation operand is less than the minimum boundary value of the preset bit width, so it is necessary to process the bit width of the operation operand.

[0035] In the above embodiments, the bit width processing can be bit width reduction or bit width unchanged. Bit width reduction can reduce the storage requirements of data. A smaller bit width means that fewer bits are needed to represent a numerical value, thereby reducing the storage capacity required for storage. By determining the relationship between the bit width of the operation operand and the preset bit width, the problem of boundary relationship change caused by changing the bit width of the operation operand can be avoided.

[0036] Step S102: processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width.

[0037] It should be noted that, taking the simplest two operation operands as an example, the bit width processing of the operation operands includes the following three cases: (1) Only the first operand is reduced in bit width.

[0038] (2) Only the second operand is reduced in bit width.

[0039] (3) The bit width of both the first operation operand and the second operation operand is reduced.

[0040] It should be noted that when the bit width of the operation result is greater than the preset bit width of the multiplier, the operation result will be saturated and truncated. In other words, when the original operation result does not undergo saturation truncation, the bit width of the first operation operand and the second operation operand will not be reduced. Correspondingly, when the original operation result will undergo saturation truncation, the bit width of the first operation operand and / or the second operation operand needs to be reduced in advance.

[0041] It should be further explained that saturation truncation means that when the result value of the operation is outside the range of the storage bit width, it needs to be regarded as the boundary value of the storage bit width. For example, 5×8=40, the storage bit width is 4 bits ([0, 15]), so 40 will be saturated and truncated to 15 for storage.

[0042] It should be noted that since saturation truncation itself will bring data errors, the actual operation results are not important when the bit width of Input1 and Input2 is reduced. The main discussion is whether Input1×Input2 is outside the maximum boundary value or the minimum boundary value of the multiplier (Output). This ensures that the calculation error introduced by the bit width processing of the operation operands in advance will be covered by the error caused by the saturation truncation of the original operation result.

[0043] Step S103: Perform a multiplication operation using the bit-width processed operation operands.

[0044] Specifically, since there are three different situations when performing bit width processing, correspondingly, step S103 also includes three situations: (1) The first operation operand with reduced bit width and the original second operation operand are input to the multiplier.

[0045] (2) The original first operation operand and the second operation operand with reduced bit width are input to the multiplier.

[0046] (3) The first operation operand after the bit width reduction and the second operation operand after the bit width reduction are input to the multiplier.

[0047] It should be noted that since the operation operands with reduced bit width are input to the multiplier, the bit width of the operands is reduced regardless of the above-mentioned situation. Based on the adaptive principle of the multiplier, the multiplier can call on fewer resources than before the bit width reduction to complete the multiplication operation, thereby achieving the purpose of saving hardware resources.

[0048] In combination with the above, as an embodiment in an exemplary embodiment, the method of the present invention can also be: determining the bit width of the first operation operand to be input into the multiplier, the bit width of the second operation operand to be input into the multiplier, and the preset bit width of the multiplier. According to the size relationship between the bit width of the first operation operand, the bit width of the second operation operand, and the preset bit width, the first operation operand and / or the second operation operand are bit-width reduced. The first operation operand after the bit width reduction and / or the second operation operand after the bit width reduction are input into the multiplier.

[0049] In the above steps S101-S103, by determining the size relationship between the bit width of the operation operand to be multiplied and the preset bit width, the bit width of the operation operand is processed, and the operation operand after the bit width processing is used to perform the multiplication operation. The problem that a large amount of resources will be consumed when performing the multiplication operation of the operation operand in the prior art is solved, and the loss of resources in the multiplication operation process is reduced by performing the bit width processing on the operation operand in advance. The situation of operation failure caused by the bit width limitation of the image processing hardware device is avoided.

[0050] In an exemplary embodiment, processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first operation operand and a second operation operand; exist When both the first and second operands are signed data, the bit width of the first operand is reduced to , reducing the bit width of the second operand to ; It should be noted that, in the above embodiment, after the bit width of the operation operand is reduced, due to the adaptive capability of the multiplier, it is equivalent to optimizing the multiplier into a × The multiplier.

[0051] exist When both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand is reduced to , reducing the bit width of the second operand to ; It should be noted that, in the above embodiment, after the bit width of the operation operand is reduced, it is equivalent to optimizing the multiplier into a × The multiplier.

[0052] in, is the bit width of the first operation operand, is the bit width of the second operation operand, The preset width.

[0053] As an example, in an exemplary embodiment, the first operation operand of the multiplier is Input1, the second operation operand is Input2, the multiplier output is Output, the preset bit width is r, and for In this case, it is necessary to and and Specifically, when both the first and second operands are unsigned data, and The bit width is compared. When both the first and second operands are signed data, and For comparison, at this time, only the smallest bit width value is considered for optimization. When Optimized , because the multiplication bit width always satisfies In order to match the data bit width, the operands with larger absolute values ​​need to be placed in the optimized large bit width, and the operands with smaller absolute values ​​need to be placed in the optimized small bit width. Optimized to If the operand is saturated and truncated, the final result Output will be saturated and truncated. The same is true for signed data, which will not be explained here.

[0054] In the above embodiment, by reducing the bit width of the operation operands, the computational complexity of the data is reduced, ensuring that the sign data still maintains the correct sign relationship after the bit width is reduced, saving the computing resources of the multiplier while improving the computing efficiency of the multiplier.

[0055] In an exemplary embodiment, processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first operation operand and a second operation operand.

[0056] exist When both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand is reduced to , reducing the bit width of the second operand to ; It should be noted that, in the above embodiment, after the bit width of the operation operand is reduced, it is equivalent to optimizing the multiplier into a × The multiplier.

[0057] exist When both the first and second operands are signed data, the bit width of the first operand is reduced to , reducing the bit width of the second operand to ; It should be noted that, in the above embodiment, after the bit width of the operation operand is reduced, it is equivalent to optimizing the multiplier into a × The multiplier.

[0058] exist When both the first and second operands are signed data, the bit width of the first operand is reduced to , reducing the bit width of the second operation to ; It should be noted that, in the above embodiment, after the bit width of the operation operand is reduced, it is equivalent to optimizing the multiplier into a × The multiplier.

[0059] exist When both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand is reduced to ; It should be noted that in When both the first and second operands are unsigned data, only the bit width of the first operand is reduced to r, and the bit width of the second operand remains unchanged, that is, the bit width of the second operand is still n. This is equivalent to optimizing the multiplier into an r×n multiplier.

[0060] exist When both the first and second operands are signed data, the bit width of the first operand is reduced to ; It should be noted that in the above embodiment, the bit width of the first operation operand is reduced to , the bit width of the second operation operand is not processed, that is, the bit width of the second operation operand is still n, which is equivalent to optimizing the multiplier into a × The multiplier.

[0061] in, is the bit width of the first operation operand, is the bit width of the second operation operand, The preset width.

[0062] As an optional embodiment, for In the case of multiplication, the absolute value of the operand must be less than or equal to the absolute value of the result (excluding the value of 0). However, for signed data, the value range is not symmetrical about the 0 point. If the bit width of an operand is processed to the positive boundary in advance, it may cause errors in the result. Therefore, it is considered to expand 1 bit to offset the error. Therefore, the bit width of the first operand needs to be processed to or , optimize the bit width of the second operation operand to or .

[0063] In the above embodiment, by reducing the bit width of the operand in advance, the data can be limited to a reasonable range, avoiding overflow or truncation problems in the subsequent calculation process, and ensuring the calculation accuracy and stability of the system. After the bit width is reduced, the bit width of the operand to be processed is reduced, which can significantly reduce the complexity of the hardware multiplier, reduce the number of required logic units, and simplify the circuit design. Especially in chip design, it is helpful to reduce chip area and power consumption.

[0064] In an exemplary embodiment, processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first operation operand and a second operation operand.

[0065] exist When both the first and second operands are signed data, the bit width of the first operand is reduced to , reducing the bit width of the second operand to ; It should be noted that, in the above embodiment, after the bit width of the operation operand is reduced, it is equivalent to optimizing the multiplier into a × The multiplier.

[0066] exist When both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand is reduced to , reducing the bit width of the second operand to ; It should be noted that, in the above embodiment, after the bit width of the operation operand is reduced, it is equivalent to optimizing the multiplier into a × The multiplier.

[0067] in, is the bit width of the first operation operand, is the bit width of the second operation operand, The preset width.

[0068] It should be noted that, in order to match the bit width of the operation operands, the operation operands with larger absolute values ​​need to be placed in the optimized large bit width, and the operation operands with smaller absolute values ​​need to be placed in the optimized small bit width.

[0069] In the above embodiment, although the bit width reduction will affect the accuracy of the result to a certain extent, by reducing the bit width in the embodiment, the error can be minimized while ensuring sufficient accuracy, thereby improving the overall calculation accuracy.

[0070] In an exemplary embodiment, When both the first operation operand and the second operation operand are signed data, the bit widths of the first operation operand and the second operation operand remain unchanged; exist When both the first operation operand and the second operation operand are unsigned data, the bit widths of the first operation operand and the second operation operand remain unchanged; exist When both the first operation operand and the second operation operand are signed data, the bit widths of the first operation operand and the second operation operand remain unchanged; in, is the bit width of the first operation operand, is the bit width of the second operation operand, The preset width.

[0071] It should be noted that, in the above case, if the bit width is reduced, the boundary value between Input1×Input2 and Output will change, so the bit width is not reduced. That is, under the conditions in the above embodiment, the multiplier cannot be further optimized.

[0072] In an exemplary embodiment, the bit width m of the first operation operand is 12, the bit width n of the second operation operand is 8, the preset bit width r is 16, and the bit width of the first operation operand and the second operation operand are not reduced.

[0073] In the above embodiment, an advance judgment is made based on the size relationship between the bit width of the operation operand and the preset bit width, thereby avoiding the problem of boundary conditions being changed after the operation operands after the bit width reduction are input into the multiplier, thereby causing calculation errors. The bit width reduction is skipped and the multiplication operation is directly performed, which reduces the processing time and improves the calculation efficiency. In application scenarios with high computational intensity such as image processing or signal processing, the response speed of the system can be effectively improved.

[0074] The executor of each step in the above method can be a data processing device for multiplication operation, which can be implemented by software and / or hardware. The device can be integrated in an electronic device. The electronic device can be a terminal device (such as a smart phone, a personal computer, etc.), or a server (such as a local server or a cloud server, or a server cluster, etc.), or a processor, or a chip, etc.

[0075] Obviously, the above-described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. In order to better understand the above method, the above process is described below in conjunction with the embodiments, but the technical solutions of the embodiments of the present invention are not limited. Specifically: like Figure 2 As shown, the schematic diagram of the working principle of the multiplier provided by the present invention is shown. Among them, Input1 (corresponding to the first operation operand in the above embodiment), Input2 (corresponding to the second operation operand in the above embodiment) and Output are all integer types, and Input1, Input2 and Output must all be signed numbers at the same time, or unsigned numbers at the same time.

[0076] The core principle of the present invention is that when the original operation result does not undergo saturation truncation, the operation operand will not undergo saturation truncation either. This can ensure that the calculation error introduced by reducing the bit width of the operation operand in advance will be masked by the error caused by the saturation truncation of the original operation result.

[0077] Combining Input1[m-1:0]×Input2[n-1:0]——Output[r-1:0] for analysis, the bit width of Input1 is r, the bit width of Input2 is n, and the bit width of Output is r.

[0078] (1) For Because when Input1[m-1:0] is optimized to Input1[r-1:0] or Input2[n-1:0] is optimized to Input1[r-1:0], saturation truncation will occur in the original expression (the absolute value of the multiplication of the operands must be less than or equal to the absolute value of the result, ignoring the value of 0). However, for signed data, its value range is not symmetrical about the 0 point. Truncating an operand value to the positive boundary in advance may cause an error in its product with -1 (for example, the bit width is 5bit×5bit——4bit, and the value is 8×(-1), which may become 7×(-1)). Therefore, you can consider expanding 1bit to offset the error. Later, you can also make the bit width of one of the operands lower; (2) For In this case, it is necessary to and , (When the operation operand is unsigned data, When the operation operand has data, At this time, only the smallest bit width value is considered for optimization. , optimization is not possible. When Optimized . Because the multiplication bit width always satisfies In order to match the data bit width, the operands with larger absolute values ​​need to be placed in the optimized large bit width, and the operands with smaller absolute values ​​need to be placed in the optimized small bit width. Optimized to When the operation operand is saturated and truncated, the final result Output will be saturated and truncated. The same is true for signed data, which will not be described here. (3) For In the case of , m (i.e., the bit width of Input1) can be optimized to r or (r+1), and n (i.e., the bit width of Input2) can be optimized to or Or no bit width reduction is performed.

[0079] 1. When When Figure 3 To process, Figure 3 This is one of the flow charts of bit width reduction provided by the present invention. Figure 3 : (1) When the operands are all signed data and When , the bit width of Input1 is reduced to , reducing the bit width of Input2 to ; (2) When the operands are all unsigned data and When , the bit width of Input1 is reduced to , reducing the bit width of Input2 to ; It should be noted that when the operands are all signed data and When , the bit width of the operation operands is not reduced; It should be noted that when the operands are all unsigned data and When , no bit width reduction is performed on the operation operands.

[0080] 2. When When Figure 4 To process, Figure 4 This is the second schematic diagram of the process of reducing the bit width provided by the present invention. Figure 4 As shown: (1) When the operands are all signed data and and When , the bit width of Input1 is reduced to , reducing the bit width of Input2 to ; (2) When the operands are all signed data and and , reducing the bit width of Input1 to , reducing the bit width of the second operation to ; (3) When the operands are all signed data and and When , the bit width of Input1 is reduced to , the bit width of Input2 is not reduced, that is, the bit width of Input2 remains unchanged and is still n; (4) When the operands are all unsigned data and When , the bit width of Input1 is reduced to , reducing the bit width of Input2 to ; (5) When the operands are all unsigned data and When , the bit width of Input1 is reduced to . The bit width of Input2 is not reduced, that is, the bit width of Input2 remains unchanged and is still n; It should be noted that when the operands are all signed data and and When , no bit width reduction is performed on the operation operands.

[0081] 3. When When Figure 5 To process, Figure 5 This is the third schematic diagram of the process of reducing the bit width provided by the present invention. Figure 5 As shown: (1) When all operands are signed data, the bit width of Input1 is reduced to , reducing the bit width of Input2 to ; (2) When all operands are unsigned data, the bit width of Input1 is reduced to , reducing the bit width of Input2 to ; It should be noted that after the bit width is reduced, the values ​​with larger absolute values ​​in Input1 and Input2 should be placed in the larger bit width, and the values ​​with smaller absolute values ​​should be placed in the smaller bit width.

[0082] In the scenario of signed data, if Input1 or Input2 is greater than Output, after optimization, it is necessary to consider that the signed value is not symmetric about 0, so one of the multiplier bit widths will be optimized to (r+1). Of course, it can also be directly optimized to r and then removed by adding a logical structure.

[0083] In combination with the specific embodiment, Input1[7:0]×Input2[7:0]——Output[7:0], wherein Input1, Input2 and Output are all signed numbers.

[0084] Step 1: If the bit width of Input1 and Input2 is greater than the bit width of Output, both Input1 and Input2 can be reduced to the bit width of Output.

[0085] Step 2: If the bit width of Input1 and Input2 is less than or equal to Output, only one of the operands (Input1 and Input2) can be reduced. The smaller value of Input1 or Input2 can be placed in 5 bits. The only principle to be noted is: when 8 bits ([-128, 127]) - 5 bits ([-16, 15]), if saturation truncation occurs (that is, the original 8-bit value exceeds the 5-bit range, it will be converted to the boundary value corresponding to 5 bits, such as -125-16, 18-15), then Input1×Input2-Output will also be saturated and truncated.

[0086] The optimization to 5 bits is because the smaller 8-bit value is saturated and truncated to 5 bits to ensure that the principle is true. If it is optimized to 4 bits ([-8, 7]) or smaller, there will be violations of the principle (for example, 9×9, 9 must exceed the 4-bit range, but 81 is still within the 9-bit value range. So the whole process will become 9×7 (9——7), which will cause errors).

[0087] Therefore, Input1[7:0]×Input2[7:0]——Output[8:0] can be optimized to: 8bit×5bit.

[0088] The data processing device for multiplication operation provided by the present invention is described below. The data processing device for multiplication operation described below and the data processing method for multiplication operation described above can be referred to each other.

[0089] Figure 6 Schematic diagram of the structure of the data processing device for multiplication operation provided by the present invention. Figure 6 As shown, the device comprises: The determination module 601 is used to determine the bit width of the operation operand to be multiplied and the preset bit width.

[0090] The first processing module 602 is used to process the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width.

[0091] The second processing module 603 is used to perform a multiplication operation using the operation operands after the bit width processing.

[0092] By using the data processing device for multiplication operation, the bit width of the operation operand to be multiplied is processed by determining the size relationship between the bit width of the operation operand to be multiplied and the preset bit width, and the operation operand after the bit width processing is used to perform the multiplication operation. The problem that a large amount of resources will be consumed when performing multiplication operation on the operation operand in the prior art is solved, and the loss of resources in the multiplication operation process is reduced by performing bit width processing on the operation operand in advance.

[0093] Optionally, the first processing module 602 is further used to process the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width when the bit width of the operation operand is greater than the maximum boundary value of the preset bit width or less than the minimum boundary value of the preset bit width.

[0094] Optionally, the first processing module 602 is further configured to: When both the first and second operands are signed data, the bit width of the first operand is reduced to , reducing the bit width of the second operand to .exist When both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand is reduced to , reducing the bit width of the second operand to .in, is the bit width of the first operation operand, is the bit width of the second operation operand, The operation operands include a first operation operand and a second operation operand.

[0095] Optionally, the first processing module 602 is further configured to: When both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand is reduced to , reducing the bit width of the second operand to .exist When both the first and second operands are signed data, the bit width of the first operand is reduced to , reducing the bit width of the second operand to .exist When both the first and second operands are signed data, the bit width of the first operand is reduced to , reducing the bit width of the second operation to .exist When both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand is reduced to .exist When both the first and second operands are signed data, the bit width of the first operand is reduced to .in, is the bit width of the first operation operand, is the bit width of the second operation operand, The operation operands include a first operation operand and a second operation operand.

[0096] Optionally, the first processing module 602 is further configured to: When both the first and second operands are signed data, the bit width of the first operand is reduced to , reducing the bit width of the second operand to .exist When both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand is reduced to , reducing the bit width of the second operand to .in, is the bit width of the first operation operand, is the bit width of the second operation operand, The operation operands include a first operation operand and a second operation operand.

[0097] Optionally, the device further includes a third processing module for When both the first operation operand and the second operation operand are signed data, the bit width of the first operation operand and the second operation operand is not reduced. When both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand and the second operation operand is not reduced. When both the first operation operand and the second operation operand are signed data, the bit width of the first operation operand and the second operation operand is not reduced. is the bit width of the first operation operand, is the bit width of the second operation operand, The operation operands include a first operation operand and a second operation operand.

[0098] Figure 7 A schematic diagram of the structure of an electronic device provided by the present invention, such as Figure 7As shown, the electronic device may include: a processor 710, a communication interface 720, a memory 730 and a communication bus 740, wherein the processor 710, the communication interface 720 and the memory 730 communicate with each other through the communication bus 740. The processor 710 may call the logic instructions in the memory 730 to execute any of the data processing methods for multiplication operations provided in the above embodiments, and the method includes: The bit width of the operation operand to be multiplied and the preset bit width are determined.

[0099] The bit width of the operation operand is processed according to the size relationship between the bit width of the operation operand and the preset bit width.

[0100] Perform multiplication using the bit-width processed operands.

[0101] In addition, the logic instructions in the above-mentioned memory 730 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0102] On the other hand, the present invention further provides a computer program product, the computer program product includes a computer program, the computer program can be stored in a non-transitory computer-readable storage medium, when the computer program is executed by a processor, the computer can execute the data processing method for multiplication operation provided by the above methods, the method includes: The bit width of the operation operand to be multiplied and the preset bit width are determined.

[0103] The bit width of the operation operand is processed according to the size relationship between the bit width of the operation operand and the preset bit width.

[0104] Perform multiplication using the bit-width processed operands.

[0105] In another aspect, the present invention further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the computer program can implement any of the data processing methods for multiplication operations provided in the above embodiments, the method comprising: The bit width of the operation operand to be multiplied and the preset bit width are determined.

[0106] The bit width of the operation operand is processed according to the size relationship between the bit width of the operation operand and the preset bit width.

[0107] Perform multiplication using the bit-width processed operands.

[0108] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, i.e., they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative effort.

[0109] Through the description of the above implementation modes, those skilled in the art can clearly understand that each implementation mode can be implemented by means of software plus a necessary general hardware platform, or of course by hardware. Based on such an understanding, the above technical solution can essentially or in other words be embodied in the form of a software product that contributes to the prior art. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods of each embodiment or some parts of the embodiment.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Although the present invention has been described in detail with reference to the above embodiments, a person skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data processing method for multiplication operation, characterized in that: include: Determining the bit width of the operation operand to be multiplied and the preset bit width; Processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width; Perform multiplication using the bit-width processed operands.

2. The data processing method for multiplication operation according to claim 1, characterized in that: The processing of the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: When the bit width of the operation operand is greater than the maximum boundary value of the preset bit width or less than the minimum boundary value of the preset bit width, the bit width of the operation operand is processed according to the size relationship between the bit width of the operation operand and the preset bit width.

3. The data processing method for multiplication operation according to claim 1 or 2, characterized in that: The processing of the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first operation operand and a second operation operand; exist When both the first operation operand and the second operation operand are signed data, the bit width of the first operation operand is reduced to , reducing the bit width of the second operation operand to ; exist When both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand is reduced to , reducing the bit width of the second operation operand to ; in, is the bit width of the first operation operand, is the bit width of the second operation operand, is the preset bit width.

4. The data processing method for multiplication operation according to claim 1 or 2, characterized in that: The processing of the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first operation operand and a second operation operand; exist When both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand is reduced to , reducing the bit width of the second operation operand to ; exist When both the first operation operand and the second operation operand are signed data, the bit width of the first operation operand is reduced to , reducing the bit width of the second operation operand to ; exist When both the first operation operand and the second operation operand are signed data, the bit width of the first operation operand is reduced to , reducing the bit width of the second operation to ; exist When both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand is reduced to ; exist When both the first operation operand and the second operation operand are signed data, the bit width of the first operation operand is reduced to ; in, is the bit width of the first operation operand, is the bit width of the second operation operand, is the preset bit width.

5. The data processing method for multiplication operation according to claim 1 or 2, characterized in that: The processing of the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first operation operand and a second operation operand; exist When both the first operation operand and the second operation operand are signed data, the bit width of the first operation operand is reduced to , reducing the bit width of the second operation operand to ; exist When both the first operation operand and the second operation operand are unsigned data, the bit width of the first operation operand is reduced to , reducing the bit width of the second operation operand to ; in, is the bit width of the first operation operand, is the bit width of the second operation operand, is the preset bit width.

6. The data processing method for multiplication operation according to claim 2, characterized in that: The method further comprises: The operation operands include a first operation operand and a second operation operand; exist When both the first operation operand and the second operation operand are signed data, the bit widths of the first operation operand and the second operation operand remain unchanged; exist When both the first operation operand and the second operation operand are unsigned data, the bit widths of the first operation operand and the second operation operand remain unchanged; exist When both the first operation operand and the second operation operand are signed data, the bit widths of the first operation operand and the second operation operand remain unchanged; in, is the bit width of the first operation operand, is the bit width of the second operation operand, is the preset bit width.

7. A data processing device for multiplication operation, characterized in that: include: A determination module, used to determine the bit width of the operation operand to be multiplied and the preset bit width; A first processing module, configured to process the bit width of the operation operand according to a size relationship between the bit width of the operation operand and the preset bit width; The second processing module is used to perform a multiplication operation using the operation operands after bit width processing.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the data processing method for multiplication operation according to any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the data processing method for multiplication operation according to any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the data processing method for multiplication operation according to any one of claims 1 to 6 is implemented.

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