Data processing method and device for multiply-add operation, electronic equipment and medium

Abstract

The invention provides a data processing method and device for multiplication and addition operation, electronic equipment and a medium. The method comprises the steps that the bit width and the preset bit width of an operation operand to be subjected to multiplication and addition operation are determined; processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and a preset bit width; and carrying out multiplication and addition operation by using the operation operands after bit width processing. According to the invention, the problem that a large amount of resources are consumed during multiplication and addition operation is solved.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a data processing method, device, electronic equipment and medium for multiplication and addition operations. Background Art

[0002] Multiplication and addition operations are often performed in fields such as image processing, speech coding, and artificial intelligence (AI) accelerators. In the hardware implementation process, it is common that the bit width of the operation operand is too large and the target bit width is insufficient to meet the bit width of the operation operand. In this case, the operation result is usually saturated and truncated. However, in this process, a large amount of resources will still be consumed when performing multiplication and addition operations on the operation operands.

[0003] In view of the problem in the prior art that a large amount of resources are wasted when performing multiplication and addition operations on operands, no effective solution has been proposed so far. Summary of the invention

[0004] The present invention provides a data processing method, device, electronic device and medium for multiplication and addition operations, which are used to solve the problem in the prior art that a large amount of resources will be consumed when performing multiplication and addition operations on operation operands. The bit width of the operation operands is processed in advance to reduce the loss of resources during the multiplication and addition operations.

[0005] In a first aspect, the present invention provides a data processing method for multiplication and addition operations, comprising: Determine the bit width of the operation operands to be multiplied and added and the preset bit width; Processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width; Perform multiplication and addition operations using the bit-width processed operands.

[0006] In a second aspect, the present invention provides a data processing device for multiplication and addition operations, comprising: The determination module is used to determine the bit width of the operation operands to be multiplied and added and the preset bit width.

[0007] The first processing module is used to process the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width.

[0008] The second processing module is used to perform multiplication and addition operations using the operation operands after bit width processing.

[0009] In a third aspect, the present invention further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the processor implements any of the above-mentioned data processing methods for multiplication and addition operations.

[0010] In a fourth aspect, the present invention further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements any of the above-mentioned data processing methods for multiplication and addition operations.

[0011] The data processing method, device, electronic device and medium for multiplication and addition operations provided by the present invention process the bit width of the operation operands to be multiplied and added by determining the bit width of the operation operands to be multiplied and added and the size relationship of the preset bit width, and use the operation operands after bit width processing to perform multiplication and addition operations. The problem that a large amount of resources will be consumed when performing multiplication and addition operations on the operation operands in the prior art is solved, and the loss of resources in the multiplication and addition process is reduced by performing bit width processing on the operation operands in advance. The situation of operation failure caused by the bit width limitation of the hardware device is avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0013] Figure 1 It is a flow chart of a data processing method for multiplication and addition operations provided by the present invention.

[0014] Figure 2 It is a schematic diagram of the working principle of the multiplier-accumulator provided by the present invention.

[0015] Figure 3 This is one of the flowcharts of bit width reduction provided by the present invention.

[0016] Figure 4 This is the second schematic diagram of the process of bit width reduction provided by the present invention.

[0017] Figure 5 This is the third schematic diagram of the process of bit width reduction provided by the present invention.

[0018] Figure 6 This is the fourth schematic diagram of the process of bit width reduction provided by the present invention.

[0019] Figure 7 It is a structural schematic diagram of a data processing device for multiplication and addition operations provided by the present invention.

[0020] Figure 8 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] Figure 1 is a flow chart of a data processing method for multiplication and addition operations provided by the present invention, such as Figure 1 As shown, the method includes the following steps S101-S103: Step S101: Determine the bit width of the operation operands to be multiplied and added and the preset bit width.

[0023] It should be noted that the preset bit width can be the bit width of the multiplier-adder, or the bit width of any multiplication-addition function module, or the actual required bit width in the process of data operation and other processing (such as image data processing). The preset bit width here can also be understood as the bit width of the hardware device related to image processing when the result of the multiplication-addition operation is the input of the hardware device related to image processing. Since the bit width of the hardware device related to the image processing is limited (some hardware devices cannot handle too large a bit width), it is necessary to reduce the bit width of the operation operand before the multiplication-addition operation is performed to avoid the problem of operation failure due to exceeding the processing capacity of the hardware device related to image processing. The specific type of preset bit width is not further limited by the present invention. The embodiment of the present invention is not further limited to this. Based on this, the present invention can be used in a multiplier-adder, and can also be used in a device with a multiplication-addition function module in the field of image processing, and the embodiment of the present invention is not further limited to this.

[0024] As an optional embodiment, Figure 2It is a schematic diagram of the working principle of the multiplier and adder provided by the present invention. As shown in the figure, the first multiplication operand is Input1, the second multiplication operand is Input1, the addition operand is Input3, Input1 and Input1 are used to perform multiplication, Output' is the result of the multiplication, the bit width of Output' is m+n, the bit width of the first multiplication operand is m, the bit width of the second multiplication operand is n, the bit width of the addition operand is q, and the preset bit width of the multiplier and adder is r (it can also be understood that the bit width of Output is r). In other words, the multiplication and addition operation can be understood as performing multiplication operation first and then performing addition operation. To complete the multiplication and addition operation, at least three operation operands are required. In the actual application process, the number of specific operation operands is not further limited by the present invention.

[0025] For ease of understanding, the present invention is further explained in a multiplier-accumulator operation scenario with three operation operands.

[0026] In an exemplary embodiment, when the bit width of an operation operand is greater than a maximum boundary value of a preset bit width or less than a minimum boundary value of a preset bit width, the bit width of the operation operand is processed according to the size relationship between the bit width of the operation operand and the preset bit width.

[0027] As an optional embodiment, since both addition and multiplication can reduce the operand bit width by early truncation when saturation truncation occurs, resource loss can be reduced. For multiplication and addition operations, the bit width optimization of multiplication and addition operations can be completed by optimizing addition first and then optimizing multiplication.

[0028] It should be noted that the premise of bit width processing is that the original operation result will be saturated and truncated. That is to say, if the original operation result is not saturated and truncated, the bit width of the operation operand will not be reduced.

[0029] It should be noted that saturation truncation means that when a value exceeds the range that the data can represent (i.e., when overflow occurs), the part that exceeds the range is not directly discarded or moduloed, but it is limited to the maximum or minimum value that the data can represent. In other words, when the calculation result exceeds the maximum representable range, it is set to the maximum value. When the calculation result is less than the minimum representable range, it is set to the minimum value. This method can avoid data distortion or unreasonable results caused by overflow.

[0030] Step S102: processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width.

[0031] As an optional embodiment, the present invention first determines the optimized bit widths of Output' and Input3 according to Output, and then determines the bit widths of Input1 and Input2 according to the optimized bit width of Output'. That is, the addition optimization is performed first, and then the multiplication optimization is performed. That is, the bit width of Input3 is processed first, and then the bit widths of Input1 and Input2 are processed.

[0032] That is, the bit widths of Output' and Input3 are processed first, and then based on the size relationship between the bit width of Output' and the bit widths of Input1 and Input2, the bit widths of Input1 and Input2 are processed.

[0033] As an optional embodiment, the bit width of the multiplication result and / or the bit width of the addition operand are processed by the size relationship among the bit width of the multiplication result, the bit width of the addition operand, and the preset bit width; the bit width of the first multiplication operand and / or the bit width of the second multiplication operand are processed by the size relationship among the bit width of the first multiplication operand, the bit width of the second multiplication operand, and the bit width of the reduced multiplication result, and the multiplication result is obtained based on the first multiplication operand and the second multiplication operand.

[0034] Step S103: Perform multiplication and addition operations using the bit-width processed operation operands.

[0035] It should be noted that, since the operation operands after bit width processing are input into the multiplier-adder, combined with the adaptive principle of the multiplier-adder, the multiplier-adder can call fewer resources than before the bit width reduction to implement the multiplication and addition operation, thereby achieving the purpose of saving hardware resources.

[0036] In combination with the above, as an optional embodiment, the method of the present invention may also be: determining the bit width of a first multiplication operand to be input into the multiplier, the bit width of a second multiplication operand to be input into the multiplier, the bit width of an addition operand to be input into the multiplier, and a preset bit width of the multiplier; reducing the bit width of the first multiplication operand and / or the second multiplication operand and / or the addition operand according to the size relationship among the bit width of the first multiplication operand, the bit width of the second multiplication operand, the bit width of the addition operand, and the preset bit width; and inputting the first multiplication operand after the bit width reduction and / or the second multiplication operand after the bit width reduction and / or the addition operand after the bit width reduction into the multiplier.

[0037] In the above steps S101-S103, by determining the size relationship between the bit width of the operation operand to be multiplied and added and the preset bit width, the bit width of the operation operand is processed, and the operation operand after the bit width processing is used to perform the multiplication and addition operation. The problem that the operation operand in the prior art consumes a lot of resources when performing multiplication and addition operations is solved, and the loss of resources in the multiplication and addition operation process is reduced by performing bit width processing on the operation operand in advance. The situation of operation failure caused by the bit width limitation of the image processing hardware device is avoided.

[0038] In an exemplary embodiment, processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first multiplication operation operand, a second multiplication operation operand, and an addition operation operand.

[0039] exist , the bit width of Output' is optimized to r, and the bit width of the addition operand remains q.

[0040] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to .

[0041] It should be noted that, in the above embodiment, only the bit widths of the first multiplication operand and the second multiplication operand are reduced, and the bit width of the addition operand remains unchanged, that is, the bit width of the addition operand is still q.

[0042] It should be further explained that the above embodiment is equivalent to optimizing the bit width of Output' to r. Specifically, the multiplier is optimized to a × The multiplier.

[0043] For addition operations, if the original operation result is not saturated and truncated, Output'[m+n-1:0]+Input3[q-1:0]=Output[r-1:0] holds. , you can transform Output'[m+n-1:0]+Input3[q-1:0]=Output[r-1:0] into Output'[m+n-1:0]=Output[r-1:0]-Input3[q-1:0]. To match the bit widths on both sides of the equation, you need to change and The size of is discussed below. At this time, it is necessary to pay attention to the symbol type of Output' and Input3.

[0044] For multiplication operations, we analyze Input1[m-1:0]×Input2[n-1:0]--Output'[r-1:0]. When the operands are saturated and truncated in advance, it is necessary to ensure that the original result will also be saturated and truncated. Therefore, we need to discuss m, n and relationship, because when By reducing the bit width , the original expression will definitely be saturated and truncated.

[0045] It should be noted that the bit width of Output' is m+n, that is, the bit width of the result of multiplying the first multiplication operand and the second multiplication operand is m+n. Assuming that m is 8, n is 10, r is 12, and the operation operands are all unsigned data, the bit width of the first multiplication operand is reduced to 10, and the bit width of the second multiplication operand is reduced to 6. At this time, the bit width of the addition operand remains unchanged.

[0046] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to .

[0047] It should be noted that is the bit width of the first multiplication operand (i.e. Input1), is the bit width of the second multiplication operand (i.e. Input2), is the bit width of the addition operand (i.e. Input3), The preset width.

[0048] It should be noted that in the above embodiment, only the bit widths of the first multiplication operand and the second multiplication operand are reduced, and the bit width of the addition operand remains unchanged, that is, the bit width of the addition operand is still q. At this time, it is equivalent to optimizing the bit width of Output' to r. Specifically, the multiplier is optimized into a × The multiplier.

[0049] As an optional embodiment, m is 8, n is 6, r is 8, q is 14 and the operation operands are all unsigned data, then the optimized m is 8, and the optimized bit width n of the second multiplication operation operand is 4. At this time, the bit width of the addition operation operand remains unchanged.

[0050] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to .

[0051] It should be noted that is the bit width of the first multiplication operand (i.e. Input1), is the bit width of the second multiplication operand (i.e. Input2), is the bit width of the addition operand (i.e. Input3), The preset width.

[0052] It should be noted that in the above embodiment, only the bit width of the first multiplication operand is reduced to r, and the bit widths of the second multiplication operand and the addition operand remain unchanged, which is equivalent to optimizing the bit width of Output' to r. Specifically, the multiplier is optimized into a The multiplier.

[0053] As an optional embodiment, m is 10, n is 4, r is 8, q is 14, and the operation operands are all unsigned data, then the bit width m of the optimized first multiplication operation operand is 8, and the bit width n of the optimized second multiplication operation operand is 4. At this time, the bit width of the addition operation operand remains unchanged.

[0054] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to .

[0055] It should be noted that, in the above embodiment, the bit width of the first multiplication operand is reduced to r, and the bit width of the second multiplication operand is reduced to , the bit width of the addition operand remains unchanged, which is equivalent to optimizing the bit width of Output' to r. Specifically, the multiplier is optimized into a The multiplier.

[0056] As an optional embodiment, m is 10, n is 12, r is 8, q is 14, and the operation operands are all unsigned data, then the bit width m of the optimized first multiplication operation operand is 8, and the bit width n of the optimized second multiplication operation operand is 4. At this time, the bit width of the addition operation operand remains unchanged.

[0057] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to .

[0058] It should be noted that, in the above embodiment, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , the bit width of the addition operand remains unchanged, which is equivalent to optimizing the bit width of Output' to (r+1). Specifically, the multiplier is optimized into a The multiplier.

[0059] It should be noted that is the bit width of the first multiplication operand (i.e. Input1), is the bit width of the second multiplication operand (i.e. Input2), is the bit width of the addition operand (i.e. Input3), The preset width.

[0060] As an optional embodiment, m is 10, n is 8, r is 12, q is 14, and the operation operands are all signed data, then the bit width m of the optimized first multiplication operation operand is 10, and the bit width n of the optimized second multiplication operation operand is 7. At this time, the bit width of the addition operation operand remains unchanged.

[0061] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to .

[0062] It should be noted that is the bit width of the first multiplication operand (i.e. Input1), is the bit width of the second multiplication operand (i.e. Input2), is the bit width of the addition operand (i.e. Input3), The preset width.

[0063] It should be noted that, in the above embodiment, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , the bit width of the addition operand remains unchanged, which is equivalent to optimizing the bit width of Output' to (r+1). Specifically, the multiplier is optimized into a )× The multiplier.

[0064] As an optional embodiment, m is 14, n is 8, r is 12, q is 14, and the operation operands are all signed data, then the bit width m of the optimized first multiplication operation operand is 14, and the bit width n of the optimized second multiplication operation operand is 7. At this time, the bit width of the addition operation operand remains unchanged.

[0065] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to .

[0066] It should be noted that is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0067] It should be noted that, in the above embodiment, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , the bit width of the addition operand remains unchanged, which is equivalent to optimizing the bit width of Output' to (r+1). Specifically, the multiplier is optimized into a )× The multiplier.

[0068] As an optional embodiment, m is 13, n is 8, r is 12, q is 14, and the operation operands are all signed data, then the bit width m of the optimized first multiplication operation operand is 13, and the bit width n of the optimized second multiplication operation operand is 7. At this time, the bit width of the addition operation operand remains unchanged.

[0069] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to .

[0070] It should be noted that, in the above embodiment, the bit width of the first multiplication operand is reduced to , the bit widths of the second multiplication operand and the addition operand remain unchanged, which is equivalent to optimizing the bit width of Output' to (r+1). Specifically, the multiplier is optimized into a )× The multiplier.

[0071] It should be noted that is the bit width of the first multiplication operand (i.e. Input1), is the bit width of the second multiplication operand (i.e. Input2), is the bit width of the addition operand (i.e. Input3), The preset width.

[0072] As an optional embodiment, m is 14, n is 6, r is 12, q is 14 and the operation operands are all signed data, then the bit width m of the optimized first multiplication operation operand is 14. At this time, the bit widths of the second multiplication operation operand and the addition operation operand remain unchanged.

[0073] exist When the second multiplication operand and the addition operand are both signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to .

[0074] It should be noted that, in the above embodiment, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , the bit width of the addition operand remains unchanged, which is equivalent to optimizing the bit width of Output' to (r+1). Specifically, the multiplier is optimized into a )× The multiplier.

[0075] It should be noted that is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0076] As an optional embodiment, m is 14, n is 16, r is 12, q is 14 and the operation operands are all signed data, then the bit width m of the optimized first multiplication operation operand is 14, and the bit width of the second multiplication operation operand is 7. At this time, the bit width of the addition operation operand remains unchanged.

[0077] As an optional embodiment, the processing logic of the above embodiment can refer to Figure 3 To process, Figure 3 This is one of the flowcharts of bit width reduction provided by the present invention.

[0078] In the above embodiment, the use of operation operands with reduced bit width shortens the calculation path of the multiplier and the adder, speeds up the operation, greatly improves the speed of image processing, enables the system to process large quantities of data more quickly, and improves the performance of real-time processing.

[0079] In an exemplary embodiment, processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first multiplication operation operand, a second multiplication operation operand, and an addition operation operand.

[0080] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to r.

[0081] It should be noted that, in the above embodiment, the multiplier is optimized into a × The multiplier is optimized to r + r, and the adder is optimized to r + r, that is, Input3 and Output' are both optimized to r.

[0082] It should be noted that is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0083] As an optional embodiment, m is 12, n is 12, r is 16, q is 24 and the operation operands are all unsigned data, then the bit width m of the optimized first multiplication operation operand is 12, the bit width of the second multiplication operation operand is 8, and the bit width of the addition operation operand is 16.

[0084] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to .

[0085] It should be noted that, in the above embodiment, the multiplier is optimized into a × The multiplier is optimized to r + r, and the adder is optimized to r + r, that is, Input3 and Output' are both optimized to r.

[0086] It should be noted that is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0087] As an optional embodiment, m is 12, n is 10, r is 12, q is 22 and the operation operands are all unsigned data, then the bit width of the optimized first multiplication operation operand is 12, the bit width of the second multiplication operation operand is 6, and the bit width of the addition operation operand is 12.

[0088] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the addition operand to r.

[0089] It should be noted that, in the above embodiment, the bit width of the first multiplication operation operand is reduced to , reducing the bit width of the addition operand to r. At this time, the bit width of the second multiplication operand remains unchanged, which is equivalent to optimizing the multiplier into a × The multiplier is optimized to r + r, and the adder is optimized to r + r, that is, Input3 and Output' are both optimized to r.

[0090] It should be noted that is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0091] As an optional embodiment, m is 12, n is 4, r is 12, q is 16, and the operation operands are all unsigned data, then the bit width of the optimized first multiplication operation operand is 12, and the bit width of the addition operation operand is 12. At this time, the bit width of the second multiplication operation operand remains unchanged.

[0092] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to r.

[0093] It should be noted that, in the above embodiment, the multiplier is optimized into a × The multiplier is optimized to r + r, and the adder is optimized to r + r, that is, Input3 and Output' are both optimized to r.

[0094] It should be noted that is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0095] As an optional embodiment, m is 12, n is 10, r is 8, q is 22 and the operation operands are all unsigned data, then the bit width of the optimized first multiplication operation operand is 8, the bit width of the second multiplication operation operand is 4, and the bit width of the addition operation operand is 8.

[0096] As an optional embodiment, the processing logic of the above embodiment can refer to Figure 4 To process, Figure 4 This is the second schematic diagram of the process of bit width reduction provided by the present invention.

[0097] In an exemplary embodiment, processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first multiplication operation operand, a second multiplication operation operand, and an addition operation operand.

[0098] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to r.

[0099] It should be noted that in the above embodiment, the adder is optimized to an r + r adder, that is, Input3 and Output' are both optimized to r. The multiplier is optimized to a × The multiplier.

[0100] It should be noted that is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0101] As an optional embodiment, m is 6, n is 6, r is 8, q is 10 and the operation operands are all unsigned data, then the bit width of the optimized first multiplication operation operand is 6, the bit width of the second multiplication operation operand is 4, and the bit width of the addition operation operand is 8.

[0102] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to .

[0103] It should be noted that in the above embodiment, the adder is optimized to an r + r adder, that is, Input3 and Output' are both optimized to r. The multiplier is optimized to a × The multiplier.

[0104] It should be noted that is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0105] As an optional embodiment, m is 10, n is 6, r is 8, q is 10 and the operation operands are all unsigned data, then the bit width of the optimized first multiplication operation operand is 8, the bit width of the second multiplication operation operand is 4, and the bit width of the addition operation operand is 8.

[0106] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the addition operand to r.

[0107] It should be noted that in the above embodiment, only the bit widths of the first multiplication operand and the addition operand are reduced, and the bit width of the second multiplication operand remains unchanged, which is equivalent to optimizing the adder into an r + r adder, that is, Input3 and Output' are both optimized to r. The multiplier is optimized into an × The multiplier.

[0108] It should be noted that is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0109] As an optional embodiment, m is 10, n is 4, r is 8, q is 10, and the operation operands are all unsigned data, then the bit width of the optimized first multiplication operation operand is 8, and the bit width of the addition operation operand is 8. At this time, the bit width of the second multiplication operation operand is not processed.

[0110] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to r.

[0111] It should be noted that in the above embodiment, the adder is optimized to an r + r adder, that is, Input3 and Output' are both optimized to r. The multiplier is optimized to a × The multiplier.

[0112] It should be noted that is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0113] As an optional embodiment, m is 10, n is 10, r is 8, q is 10 and the operation operands are all unsigned data, then the bit width of the optimized first multiplication operation operand is 8, the bit width of the second multiplication operation operand is 4, and the bit width of the addition operation operand is 8.

[0114] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the addition operand is reduced to .

[0115] It should be noted that, in the above embodiment, only the bit width of the addition operand is reduced to , the bit widths of the first and second multiplication operands remain unchanged, which is equivalent to optimizing the adder into a +1) The adder of Output' is considered as +1), the multiplier is equivalent to an m×n multiplier.

[0116] It should be noted that is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0117] As an optional embodiment, m is 6, n is 4, r is 8, q is 12 and the operation operands are all signed data, then the bit width of the optimized addition operation operand is 10. At this time, the first multiplication operation operand and the second multiplication operation operand are not processed.

[0118] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to .

[0119] It should be noted that the above embodiment is equivalent to optimizing the adder into a +1) The adder of Output' is considered as +1), the multiplier is equivalent to a × The multiplier.

[0120] It should be noted that is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0121] As an optional embodiment, m is 8, n is 12, r is 12, q is 14 and the operation operands are all signed data, then the bit width of the optimized first multiplication operation operand is 12, the bit width of the second multiplication operation operand is 7, and the bit width of the addition operation operand is 14.

[0122] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to .

[0123] It should be noted that the above embodiment is equivalent to optimizing the adder into a +1) The adder of Output' is considered as +1), the multiplier is equivalent to a ( )× The multiplier.

[0124] It should be noted that is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0125] As an optional embodiment, m is 13, n is 12, r is 12, q is 14 and the operation operands are all signed data, then the bit width of the optimized first multiplication operation operand is 13, the bit width of the second multiplication operation operand is 7, and the bit width of the addition operation operand is 14.

[0126] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the addition operand to .

[0127] It should be noted that, in the above embodiment, only the bit widths of the first multiplication operand and the addition operand are reduced, and the bit width of the second multiplication operand remains unchanged, which is equivalent to optimizing the adder into an +1) The adder of Output' is considered as +1), the multiplier is equivalent to a ( )× The multiplier.

[0128] As an optional embodiment, m is 18, n is 6, r is 12, q is 14, and the operation operands are all signed data, then the bit width of the optimized first multiplication operation operand is 20, and the bit width of the addition operation operand is 14. At this time, the bit width of the second multiplication operation operand is not processed.

[0129] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the addition operand is reduced to .

[0130] It should be noted that, in the above embodiment, only the bit width of the addition operand is reduced, and the bit widths of the first multiplication operand and the second multiplication operand remain unchanged, which is equivalent to optimizing the adder into a +1) The adder of Output' is considered as +1), the multiplier is equivalent to an m× The multiplier.

[0131] It should be noted that is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0132] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to .

[0133] It should be noted that the above embodiment is equivalent to optimizing the adder into a +1) The adder of Output' is considered as +1), the multiplier is equivalent to a ( )× The multiplier.

[0134] It should be noted that is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0135] As an optional embodiment, the processing logic of the above embodiment can refer to Figure 5 To process, Figure 5 This is the third schematic diagram of the process of bit width reduction provided by the present invention.

[0136] In the above embodiment, the number of operation operands after the bit width is reduced reduces the number of signal lines and logic units in the multiplier and adder, thereby reducing the power consumption of the circuit. In the field of image processing, common operations such as convolution and filtering involve a large number of multiplication and addition operations. The complexity of the operation is effectively reduced by reducing the bit width. In scenarios where the accuracy requirements are not high, the bit width reduction significantly reduces the computational burden of the multiplier and adder, thereby improving the data processing efficiency.

[0137] In an exemplary embodiment, processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first multiplication operation operand, a second multiplication operation operand, and an addition operation operand.

[0138] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the addition operand is reduced to .

[0139] It should be noted that in the above embodiment, only the bit width of the addition operand is reduced, and the bit widths of the first multiplication operand and the second multiplication operand are not processed, that is, the bit width of Output' cannot be optimized.

[0140] It should be noted that, at this time, the bit widths of the first multiplication operand and the second multiplication operand are not processed.

[0141] It should be noted that is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0142] exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the addition operand is reduced to .

[0143] It should be noted that in the above embodiment, only the bit width of the addition operand is reduced, and the bit widths of the first multiplication operand and the second multiplication operand are not processed, that is, the bit width of Output' cannot be optimized.

[0144] It should be noted that, at this time, the bit widths of the first multiplication operand and the second multiplication operand are not processed.

[0145] It should be noted that is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0146] As an optional embodiment, the processing logic of the above embodiment can refer to Figure 6 To process, Figure 6 This is the fourth schematic diagram of the process of bit width reduction provided by the present invention.

[0147] In the above embodiments, a large amount of data needs to be transmitted between different modules in the field of image processing, such as transferring feature maps and filter applications between convolutional layers. By reducing the bit width, the storage requirements and transmission bandwidth of the data can be reduced, and the number of accesses to the data storage can be reduced, thereby improving system performance and reducing the storage power consumption of the system. In addition, the method of the present invention does not cause excessive errors and does not have a significant impact on the quality of the image in the field of image processing.

[0148] In an exemplary embodiment, the method further includes: The operation operands include a first multiplication operation operand, a second multiplication operation operand, and an addition operation operand.

[0149] exist In the case of , the bit widths of the first multiplication operand, the second multiplication operand, and the addition operand remain unchanged.

[0150] exist When the first multiplication operand, the second multiplication operand and the addition operand are all unsigned data, the bit widths of the first multiplication operand, the second multiplication operand and the addition operand remain unchanged.

[0151] exist When the first multiplication operand, the second multiplication operand and the addition operand are all signed data, the bit widths of the first multiplication operand, the second multiplication operand and the addition operand remain unchanged.

[0152] exist When the first multiplication operand, the second multiplication operand and the addition operand are all signed data, the bit widths of the first multiplication operand, the second multiplication operand and the addition operand remain unchanged.

[0153] exist When the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit widths of the first multiplication operand, the second multiplication operand, and the addition operand remain unchanged.

[0154] exist When the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit widths of the first multiplication operand, the second multiplication operand, and the addition operand remain unchanged.

[0155] exist When the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit widths of the first multiplication operand, the second multiplication operand, and the addition operand remain unchanged.

[0156] in, is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0157] In order to further explain the above embodiment, Input1[7:0]×Input2[7:0]+Input3[7:0]--Output3[7:0] is used for further description. From the above formula, it can be known that Output'[15:0].

[0158] Assume that both Input and Output are signed numbers.

[0159] Step 1: First optimize Output'[15:0]+input3[7:0]--Output[7:0]

[0160] The value range of 16bit is [-32768, 32767], and the value range of 8bit is [-128, 127]. Therefore, the above formula can be regarded as 16bit+8bit--8bit. The limit case without addition truncation is 9bit+8bit--8bit (9bit value range is [-256, 255]), because the 9bit bit width can just cover the input 8bit value range and the output 8bit value range. Therefore, the value of Output' can be put into 9bit, and the value of Input3 can be put into 8bit. Therefore, 16bit+8bit can be optimized to 9bit+8bit.

[0161] Step 2: Optimize Input1[7:0]×Input2[7:0]--Output'[8:0]

[0162] Step 1: If the bit width of Input1 and Input2 is greater than the bit width of Output', both Input1 and Input2 can be reduced to the bit width of Output'. Step 2: If the bit width of Input1 and Input2 is less than or equal to Output', only one of the operands (Input1 or Input2) can be reduced.

[0163] The smaller value of Input1 or Input2 can be placed in 5 bits. The only principle to be noted is: when 8 bits ([-128, 127]) -- 5 bits ([-16, 15]), if saturation occurs (that is, the original 8-bit value exceeds the 5-bit range, it will be converted to the boundary value corresponding to 5 bits, such as -125---16, 18—>15), then Input1×Input2--Output' will also be saturated and truncated.

[0164] The optimization to 5 bits is because the smaller 8-bit value is saturated and truncated to 5 bits to ensure that the principle is true. If it is optimized to 4 bits ([-8, 7]) or smaller, there will be violations of the principle (for example, 9×9, 9 must exceed the 4-bit range, but 81 is within the 9-bit value range. So the whole process becomes 9×7 (9--7), which produces an error).

[0165] Therefore, Input1[7:0]×Input2[7:0]--Output'[8:0] can be optimized to: 8bit×5bit.

[0166] So in the end, the original 8bit×8bit multiplier and a 16bit+8bit adder are optimized into an 8bit×5bit multiplier and a 9bit+8bit adder.

[0167] The data processing device for multiplication and addition operations provided by the present invention is described below. The data processing device for multiplication and addition operations described below and the data processing method for multiplication and addition operations described above can be referenced to each other.

[0168] Figure 7 Schematic diagram of the structure of the data processing device for multiplication and addition operation provided by the present invention. Figure 7 As shown, the device comprises: The determination module 701 is used to determine the bit width of the operation operands to be multiplied and added and the preset bit width.

[0169] The first processing module 702 is used to process the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width.

[0170] The second processing module 703 is used to perform multiplication and addition operations using the operation operands after bit width processing.

[0171] The above device processes the bit width of the operation operand to be multiplied and added by determining the size relationship between the bit width of the operation operand to be multiplied and added and the preset bit width, and uses the operation operand after the bit width processing to perform the multiplication and addition operation. The problem that a large amount of resources will be consumed when performing multiplication and addition operations on the operation operands in the prior art is solved, and the loss of resources in the multiplication and addition operation process is reduced by performing bit width processing on the operation operands in advance.

[0172] Optionally, the first processing module 702 is further used to process the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width when the bit width of the operation operand is greater than the maximum boundary value of the preset bit width or less than the minimum boundary value of the preset bit width.

[0173] Optionally, the first processing module 702 is further configured to: If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to ;exist If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to ;exist If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to ;exist If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to ;exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to ;exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to ;exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to ;exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to ;exist When the second multiplication operand and the addition operand are both signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to ;in, is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0174] Optionally, the first processing module 702 is further configured to: If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to r; If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to ;exist If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the addition operand to r; exist If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to r; where, is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0175] Optionally, the first processing module 702 is further configured to: If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to r; If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to ;exist If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the addition operand to r; If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to r; exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the addition operand is reduced to ;exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to ;exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to ;exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the addition operand to ;exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the addition operand is reduced to ;exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to ;in, is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0176] Optionally, the first processing module 702 is further configured to: If the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit width of the addition operand is reduced to ;exist If the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit width of the addition operand is reduced to ;in, is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0177] Optionally, the device further comprises a third processing module for In the case of , the bit widths of the first multiplication operand, the second multiplication operand, and the addition operand remain unchanged; in When the first multiplication operand, the second multiplication operand and the addition operand are all unsigned data, the bit widths of the first multiplication operand, the second multiplication operand and the addition operand remain unchanged; When the first multiplication operand, the second multiplication operand and the addition operand are all signed data, the bit widths of the first multiplication operand, the second multiplication operand and the addition operand remain unchanged; When the first multiplication operand, the second multiplication operand and the addition operand are all signed data, the bit widths of the first multiplication operand, the second multiplication operand and the addition operand remain unchanged; When the first multiplication operand, the second multiplication operand, and the addition operand are all unsigned data, the bit widths of the first multiplication operand, the second multiplication operand, and the addition operand remain unchanged; When the first multiplication operand, the second multiplication operand, and the addition operand are all signed data, the bit widths of the first multiplication operand, the second multiplication operand, and the addition operand remain unchanged; When the first multiplication operand, the second multiplication operand and the addition operand are all unsigned data, the bit widths of the first multiplication operand, the second multiplication operand and the addition operand remain unchanged; wherein, is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, The preset width.

[0178] Figure 8 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 8As shown, the electronic device may include: a processor 810, a communication interface 820, a memory 830 and a communication bus 840, wherein the processor 810, the communication interface 820 and the memory 830 communicate with each other through the communication bus 840. The processor 810 may call the logic instructions in the memory 830 to execute a data processing method for multiplication and addition operations, the method comprising: The bit width of the operation operand to be subjected to the multiplication and addition operation and the preset bit width are determined.

[0179] The bit width of the operation operand is processed according to the size relationship between the bit width of the operation operand and the preset bit width.

[0180] Perform multiplication and addition operations using the bit-width processed operands.

[0181] In addition, the logic instructions in the above-mentioned memory 830 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0182] On the other hand, the present invention further provides a computer-readable storage medium having a computer program stored thereon, the computer program being used by a processor to execute the data processing method for multiplication and addition operations provided by the above methods, the method comprising: The bit width of the operation operand to be subjected to the multiplication and addition operation and the preset bit width are determined.

[0183] The bit width of the operation operand is processed according to the size relationship between the bit width of the operation operand and the preset bit width.

[0184] Perform multiplication and addition operations using the bit-width processed operands.

[0185] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, i.e., they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative effort.

[0186] Through the description of the above implementation modes, those skilled in the art can clearly understand that each implementation mode can be implemented by means of software plus a necessary general hardware platform, or of course by hardware. Based on such an understanding, the above technical solution can essentially or in other words be embodied in the form of a software product that contributes to the prior art. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods of each embodiment or some parts of the embodiment.

[0187] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Although the present invention has been described in detail with reference to the above embodiments, a person skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data processing method for multiplication and addition operations, It is characterized in that include: Determine the bit width of the operation operands to be multiplied and added and the preset bit width; Processing the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width; Perform multiplication and addition operations using the bit-width processed operands.

2. The data processing method for multiplication and addition operation according to claim 1, It is characterized in that The processing of the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: When the bit width of the operation operand is greater than the maximum boundary value of the preset bit width or less than the minimum boundary value of the preset bit width, the bit width of the operation operand is processed according to the size relationship between the bit width of the operation operand and the preset bit width.

3. The data processing method for multiplication and addition operation according to claim 1 or 2, It is characterized in that The processing of the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first multiplication operation operand, a second multiplication operation operand and an addition operation operand; exist If the first multiplication operand, the second multiplication operand and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to ; exist When the first multiplication operand, the second multiplication operand and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to ; exist When the first multiplication operand, the second multiplication operand and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to ; exist When the first multiplication operand, the second multiplication operand and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to ; exist When the first multiplication operand, the second multiplication operand and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to ; exist When the first multiplication operand, the second multiplication operand and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to ; exist When the first multiplication operand, the second multiplication operand and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to ; exist When the first multiplication operand, the second multiplication operand and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to ; exist When both the second multiplication operand and the addition operand are signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to ; in, is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, is the preset bit width.

4. The data processing method for multiplication and addition operation according to claim 1 or 2, It is characterized in that The processing of the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first multiplication operation operand, a second multiplication operation operand and an addition operation operand; exist If the first multiplication operand, the second multiplication operand and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operation operand to r; exist If the first multiplication operand, the second multiplication operand and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to ; exist If the first multiplication operand, the second multiplication operand and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the addition operation operand to r; exist If the first multiplication operand, the second multiplication operand and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operation operand to r; in, is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, is the preset bit width.

5. The data processing method for multiplication and addition operation according to claim 1 or 2, It is characterized in that The processing of the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first multiplication operation operand, a second multiplication operation operand and an addition operation operand; exist If the first multiplication operand, the second multiplication operand and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operation operand to r; exist If the first multiplication operand, the second multiplication operand and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to ; exist If the first multiplication operand, the second multiplication operand and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the addition operation operand to r; exist If the first multiplication operand, the second multiplication operand and the addition operand are all unsigned data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operation operand to r; exist When the first multiplication operand, the second multiplication operand and the addition operand are all signed data, the bit width of the addition operand is reduced to ; exist When the first multiplication operand, the second multiplication operand and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to ; exist When the first multiplication operand, the second multiplication operand and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to ; exist When the first multiplication operand, the second multiplication operand and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the addition operand to ; exist When the first multiplication operand, the second multiplication operand and the addition operand are all signed data, the bit width of the addition operand is reduced to ; exist When the first multiplication operand, the second multiplication operand and the addition operand are all signed data, the bit width of the first multiplication operand is reduced to , reducing the bit width of the second multiplication operand to , reducing the bit width of the addition operand to ; in, is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, is the preset bit width.

6. The data processing method for multiplication and addition operation according to claim 1 or 2, It is characterized in that The processing of the bit width of the operation operand according to the size relationship between the bit width of the operation operand and the preset bit width includes: The operation operands include a first multiplication operation operand, a second multiplication operation operand and an addition operation operand; exist When the first multiplication operand, the second multiplication operand and the addition operand are all unsigned data, the bit width of the addition operand is reduced to ; exist When the first multiplication operand, the second multiplication operand and the addition operand are all signed data, the bit width of the addition operand is reduced to ; in, is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, is the preset bit width.

7. The data processing method for multiplication and addition operation according to claim 2, It is characterized in that The method further comprises: The operation operands include a first multiplication operation operand, a second multiplication operation operand and an addition operation operand; exist In the case of , the bit widths of the first multiplication operand, the second multiplication operand and the addition operand remain unchanged; exist When the first multiplication operand, the second multiplication operand and the addition operand are all unsigned data, the bit widths of the first multiplication operand, the second multiplication operand and the addition operand remain unchanged; exist When the first multiplication operand, the second multiplication operand and the addition operand are all signed data, the bit widths of the first multiplication operand, the second multiplication operand and the addition operand remain unchanged; exist When the first multiplication operand, the second multiplication operand and the addition operand are all signed data, the bit widths of the first multiplication operand, the second multiplication operand and the addition operand remain unchanged; exist When the first multiplication operand, the second multiplication operand and the addition operand are all unsigned data, the bit widths of the first multiplication operand, the second multiplication operand and the addition operand remain unchanged; exist When the first multiplication operand, the second multiplication operand and the addition operand are all signed data, the bit widths of the first multiplication operand, the second multiplication operand and the addition operand remain unchanged; exist When the first multiplication operand, the second multiplication operand and the addition operand are all unsigned data, the bit widths of the first multiplication operand, the second multiplication operand and the addition operand remain unchanged; in, is the bit width of the first multiplication operand, is the bit width of the second multiplication operand, is the bit width of the addition operand, is the preset bit width.

8. A data processing device for multiplication and addition operations, It is characterized in that include: A determination module, used to determine the bit width of the operation operands to be multiplied and added and the preset bit width; A first processing module, configured to process the bit width of the operation operand according to a size relationship between the bit width of the operation operand and the preset bit width; The second processing module is used to perform multiplication and addition operations using the operation operands after bit width processing.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, It is characterized in that When the processor executes the computer program, the data processing method for multiplication and addition operations according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, It is characterized in that When the computer program is executed by a processor, the data processing method for multiplication and addition operations according to any one of claims 1 to 7 is implemented.

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