An electronic product and a memory firmware updating method thereof

Abstract

The present invention provides an electronic product and a method for updating the firmware of a memory thereof, comprising: a data transmission interface for receiving a firmware update data packet burned by a host end; a connection circuit, an input end of which is electrically connected to the data transmission interface; a central controller for powering on the memory; the memory, comprising a main control module and a flash memory module; a channel configuration circuit, when the firmware in the memory is updated, the channel configuration circuit controls the connection between the data transmission interface and the memory, and the data transmission interface sends the firmware update data packet to the memory; the main control module is used to process the firmware update data packet, generate target format data, perform verification processing on the target format data, generate verified qualified target format data, and perform update processing on the firmware in the flash memory module according to the verified qualified target format data. The present invention can effectively improve the firmware update efficiency of the memory in the electronic product.

Description

Technical Field

[0001] The present invention relates to the field of electronic storage technology, and in particular to an electronic product and a method for updating memory firmware thereof. Background Art

[0002] Embedded Multi Media Card (eMMC) and Universal Flash Storage (UFS) are widely used in electronic products such as televisions, set-top boxes, tablets, and mobile phones. eMMC is composed of an ARM CPU as a controller and a flash memory block (NAND Flash), in which the ARM CPU runs the controller software, usually called firmware. The premise of the online upgrade technology of eMMC of electronic products is that the electronic products themselves can operate normally and there is no data damage. However, during the actual repair process of customers, electronic products are usually unable to start, that is, the central controller inside the electronic products cannot start and control normally, and the memory inside the electronic products usually has a card lock problem.

[0003] The existing methods to solve the problem of memory card lock in electronic products are to replace the memory chips in the memory or to force update the firmware through the serial communication protocol. The former has a long maintenance cycle and seriously reduces the user experience. The latter can only update the firmware for electronic products with HDMI (High-Definition Multimedia Interface) interfaces, and is not applicable to electronic products with only Type C interfaces. Therefore, there is room for improvement. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an electronic product and a memory firmware update method thereof, which solves the problem of low firmware update efficiency of electronic products only provided with a Type C interface.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides an electronic product, comprising:

[0007] A data transmission interface, connected to the host end for receiving a firmware update data packet burned by the host end;

[0008] A connecting circuit, the input end of which is electrically connected to the data transmission interface;

[0009] A central controller is electrically connected to the output end of the connection circuit, and the central controller is communicatively connected to the memory to power on the memory;

[0010] a memory, which is communicatively connected to the data transmission interface via a serial communication protocol and receives a firmware update data packet via the data transmission interface, wherein the memory includes a main control module and a flash memory module; and

[0011] A channel configuration circuit is electrically connected between the data transmission interface and the memory, and when the firmware in the memory is updated, the channel configuration circuit controls the connection between the data transmission interface and the memory;

[0012] Wherein, when the firmware in the memory is updated, the data transmission interface sends the firmware update data packet to the memory;

[0013] The main control module is used to process the firmware update data packet to generate target format data;

[0014] The main control module is also used to perform verification processing on the target format data to generate target format data that passes the verification;

[0015] The main control module is also used to update the firmware in the flash memory module according to the verified qualified target format data.

[0016] In one embodiment of the present invention, the channel configuration circuit includes:

[0017] a plurality of voltage comparison modules, whose input ends are electrically connected to the data transmission interface, and are used to output an initial high potential signal when the voltage output by the data transmission interface is within a preset interval; and

[0018] A logic judgment module, whose input end is electrically connected to the output end of the voltage comparison module and whose output end is electrically connected to the memory, is used to output a target high potential signal when the voltage comparison module outputs the initial high potential signal.

[0019] In one embodiment of the present invention, the voltage comparison module includes:

[0020] A first comparison unit, whose input end is electrically connected to the data transmission interface, and whose output end is electrically connected to the logic judgment module, is used to output a first initial high potential signal when the voltage output by the data transmission interface is greater than the minimum value of the preset interval; and

[0021] A second comparison unit, whose input end is electrically connected to the data transmission interface, and whose output end is electrically connected to the logic judgment module, is used to output a second initial high potential signal when the voltage output by the data transmission interface is less than the maximum value of the preset interval;

[0022] The logic judgment module is used to output the target high potential signal when receiving the first initial high potential signal and the second initial high potential signal.

[0023] In one embodiment of the present invention, the main control module includes:

[0024] A serial communication switch, for communicating with the data transmission interface and receiving the firmware update data packet when receiving a target high potential signal;

[0025] a serial parsing unit, configured to perform logic parsing processing on the firmware update data packet upon receiving the firmware update data packet, and generate corresponding parsing data, wherein the parsing data includes a start address, a device address, a logic block address, a data length, an update data, a write command sequence number, and a write command parameter; and

[0026] The format parsing unit is used to perform format conversion processing on the parsed data when receiving the parsed data to generate the target format data.

[0027] In one embodiment of the present invention, the main control module further includes:

[0028] A verification unit, configured to verify the target format data when receiving the target format data, and send the target format data that passes the verification to the format conversion unit;

[0029] A cache unit, used for receiving the updated data in the target format data that has passed the verification and is sent by the format conversion unit;

[0030] The command parsing unit is used to receive the write command sequence number and write command parameters sent by the format conversion unit.

[0031] In one embodiment of the present invention, the format conversion unit is further configured to generate write reply information when all write command sequence numbers and write command parameters are sent to the command parsing unit, and send the information to the host via a serial communication protocol.

[0032] In one embodiment of the present invention, the main control module also includes a flash memory control unit, and the command parsing unit is also used to perform command parsing processing on the write command sequence number and the write command parameters to generate a write control command, and the flash memory control unit controls the flash memory module to obtain the updated data in the cache unit according to the write control command.

[0033] In one embodiment of the present invention, the main control module includes a register modification unit and a register unit, and the parsed data includes a register address and a register modification value;

[0034] The register modification unit is used to receive the register address and the register modification value in the target format data that has passed the verification sent by the format conversion unit, and perform register value modification processing on the register unit according to the register address and the register modification value.

[0035] The present invention also provides a method for updating memory firmware of an electronic product, comprising:

[0036] Power on the memory;

[0037] The channel configuration circuit controls the communication between the data transmission interface and the memory, and the data transmission interface sends the firmware update data packet to the memory;

[0038] The memory processes the firmware update data packet to generate target format data;

[0039] The memory performs verification processing on the target format data to generate verified target format data;

[0040] The memory updates the firmware in the flash memory module according to the verified qualified target format data.

[0041] In one embodiment of the present invention, the step of the memory updating the firmware in the flash memory module according to the verified qualified target format data comprises:

[0042] The format conversion unit writes the updated data in the verified qualified target format data into the cache unit;

[0043] When all the update data are written into the cache unit, the format conversion unit sends the write command sequence number and the write command parameters to the command parsing unit in sequence;

[0044] The command parsing unit performs command parsing processing on the write command sequence number and the write command parameter to generate a write control command;

[0045] The flash memory control unit controls the flash memory module to obtain the update data in the cache unit according to the write control command, so as to update the firmware in the flash memory module.

[0046] As described above, the present invention provides an electronic product and a method for updating the firmware of its memory. When an electronic product only provided with a Type C interface cannot be turned on normally and a card lock problem occurs in its internal memory, the connection between the memory and the data transmission interface can be controlled by a channel configuration circuit, so that the firmware update data packet is sent to the memory through an independent serial communication protocol to realize a forced update of the memory firmware. This can effectively improve the firmware update efficiency of the memory in the electronic product, reduce the maintenance cost and cycle of the electronic product, and improve the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0048] Figure 1 It is a structural schematic diagram of an electronic product of the present invention;

[0049] Figure 2 for Figure 1 Schematic diagram of the local structure in;

[0050] Figure 3 for Figure 1 Another partial structural schematic diagram in FIG.

[0051] Figure 4 for Figure 1 Schematic diagram of the pin structure of the data transmission interface;

[0052] Figure 5 A schematic diagram of a flow chart of a method for updating memory firmware of an electronic product of the present invention;

[0053] Figure 6 for Figure 5 Schematic diagram of the process of step S30;

[0054] Figure 7 for Figure 5 Schematic diagram of the process of step S50.

[0055] Component number description:

[0056] 10. Electronic products; 11. Data transmission interface;

[0057] 12. Central controller; 13. Connection circuit;

[0058] 14. Memory; 141. Main control module; 1411. Serial communication switch; 1412. Serial parsing unit; 1413. Format conversion unit; 1414. Verification unit; 1415. Cache unit; 1416. Command parsing unit; 1417. Flash memory control unit; 1418. Register modification unit; 1419. Register unit;

[0059] 142. Flash memory module; 143. Storage interface;

[0060] 15. Channel configuration circuit; 151. Voltage comparison module; 1511. First comparison unit; 1512. Second comparison unit;

[0061] 152. Logic judgment module; 1521. Logic subunit. DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0063] See also Figure 1 The present invention provides an electronic product, which can be provided with only a Type C interface, so as to forcibly update the firmware of its internal memory to clear the memory lock card, restore a new memory state, and improve the online upgrade efficiency of the memory in the electronic product.

[0064] See also Figure 1 , Figure 2 and Figure 3 In one embodiment of the present invention, the electronic product 10 may be a product whose internal memory needs to be updated with firmware, and the type of the electronic product 10 may be multiple, and the electronic product 10 may only be provided with a TypeC interface. For example, the electronic product 10 may be a mobile phone, or a tablet, etc. In addition, when it is necessary to update the memory firmware in the electronic product 10, at least one corresponding serial communication burner may be connected to the TypeC interface of the electronic product 10, and at least one host terminal may be connected to one end of the serial communication burner to burn the corresponding firmware update data packet to the electronic product 10.

[0065] Furthermore, in order to realize the sequential communication connection between the host end, the serial communication burner and the Type C interface, a data transmission line (USB) can be provided between the host end and the serial communication burner. Because the Type C interface of the electronic product 10 is a female connector, a Type C data line with a male connector can be used to communicate with the Type C interface of the electronic product 10.

[0066] Furthermore, when it is necessary to update the firmware of the memories in multiple electronic products 10, a corresponding serial communication burner can be connected to the Type C interface of each electronic product 10, and multiple serial communication burners can be connected to the same host end, so that the firmware update of the memories in multiple electronic products 10 can be achieved through one host end, thereby improving the firmware update efficiency of the memories in multiple electronic products 10.

[0067] See also Figure 1 , Figure 2 and Figure 3 In one embodiment of the present invention, the electronic product 10 may include but is not limited to a data transmission interface 11, a central controller 12, a connection circuit 13, a memory 14, and a channel configuration circuit 15. Among them, the data transmission interface 11 is a Type C interface, and the data transmission interface 11 can be connected to the host end for communication to receive the firmware update data packet burned by the host end. The Type-C interface is a physical specification of a universal serial bus (USB) interface, and its plug is symmetrical and can be plugged in and out from both sides. The Type-C interface supports the latest USB 3.1 and USB 4 standards, and the theoretical maximum transmission speed can reach 10 Gbps and 40 Gbps respectively, making data transmission faster and particularly suitable for the transmission of large files. By using an adapter, the Type-C interface can support a variety of different signal transmissions, including but not limited to USB data, Ethernet data, audio / video signals (such as HDMI, DisplayPort), and can even directly transmit data through the Thunderbolt 3 protocol.

[0068] For further information, please refer to the pin structure of the Type-C interface. Figure 4 As shown, the Type-C interface may include a pair of CC pins (Channel Configuration pins), namely, CC1 pin (Channel Configuration pin 1) and CC2 pin (Channel Configuration pin 2), and CC1 and CC2 may be centrally symmetrically arranged with the horizontal central axis of the Type-C interface as the symmetry center. Among them, the CC1 pin and the CC2 pin may be used to detect the insertion direction of the plug.

[0069] Since the Type-C interface is reversible, the device needs to be able to identify the direction of the plug in order to correctly configure the mapping relationship between the data line and the power line. The CC pin also participates in the communication of the USB Power Delivery (PD) protocol to negotiate power supply. The device and charger communicate on the CC pin to determine the maximum power that can be provided and received, thereby achieving efficient and safe charging.

[0070] See also Figure 1 In one embodiment of the present invention, the serial communication writer may be provided with at least one data transmission interface 11 for communication connection with the electronic product 10. The serial communication writer may be a data cable having a Type-C male connector at one end that can be connected to the Type-C interface for communication, and a data interface (Universal Serial Bus, USB) at the other end that can be connected to the host for communication.

[0071] Among them, since the electronic product 10 is a downstream device, its internal pull-down resistor (Pull-down Resistor, Rd) can be 5.1k, and the pull-up resistor (Pull-up Resistor, Ra) can be 1k. As an upstream device, the serial communication burner can detect the range of Rd and Ra of the electronic product 10 within the voltage range of 3.3V to 5V. Specifically, when the serial communication burner pulls up to 3.3V, the corresponding maximum voltage range of the electronic product 10 is 1.93V and the minimum is 0.29V.

[0072] The host end can be communicatively connected to the serial communication burner to supply power to the electronic product 10 , and build a corresponding update environment according to the type of the electronic product 10 to select a corresponding firmware update data packet for burning.

[0073] See also Figure 1 In one embodiment of the present invention, the central controller 12 may be a System on Chip (SoC chip), which is a chip that integrates all or most components of a computer or other electronic system into a single chip. SoC chips usually integrate a variety of functional modules including a central processing unit (CPU), a graphics processing unit (GPU), a memory interface, an input / output interface, and a communication module (Wi-Fi, Bluetooth). Among them, a connection circuit 13 may be provided between the central controller 12 and the data transmission interface 11, and the central controller 12 and the data transmission interface 11 are communicatively connected via the connection circuit 13 to power on the memory 14.

[0074] Further, the input end of the connection circuit 13 can be electrically connected to the data transmission interface 11, and the output end of the connection circuit 13 is electrically connected to the central controller 12, so as to realize the control of the central controller 12 through the data transmission interface 11. In addition, the central controller 12 is also communicatively connected with the memory 14, so as to facilitate the power-on processing and startup control of the memory 14.

[0075] See also Figure 1 , Figure 2 and Figure 3 In one embodiment of the present invention, the memory 14 may be connected to the data transmission interface 11 through a serial communication protocol (Inter-Integrated Circuit, I2C). Specifically, the connection circuit 13 may include but is not limited to a circuit that electrically connects a pair of sideband use pins (SBU) on the data transmission interface 11 to the central controller 12. The memory 14 may be electrically connected to a pair of SBU pins on the connection circuit 13 to achieve serial communication with the data transmission interface 11.

[0076] Furthermore, the channel configuration circuit 15 can be electrically connected between the data transmission interface 11 and the memory 14, and the output end of the channel configuration circuit 15 is electrically connected to the memory 14, so that when the firmware in the memory 14 is updated, the channel configuration circuit 15 controls the connection between the data transmission interface 11 and the memory 14. When the firmware in the memory 14 is updated, the data transmission interface 11 sends the firmware update data packet to the memory 14.

[0077] Since the eMMC memory is an embedded memory, it has multiple pins for power supply, data transmission, control signals, etc. Some of these pins may be marked as No Connect (NC) in a specific design, indicating that these pins are not assigned specific uses in the standard eMMC functions and are therefore not usually connected.

[0078] For example, see Figure 1 and Figure 4 , you can first pull a line from the SBU1 pin connection line of the connection circuit 13 to the serial clock line (I2C SCL pin) reserved for the eMMC memory, and pull a line from the SBU2 pin connection line of the connection circuit 13 to the serial data line (I2C SDA pin) reserved for the eMMC memory to achieve communication connection between the memory 14 and the data transmission interface 11. Then, a pair of CC pins of the data transmission interface 11 are electrically connected to the input end of the channel configuration circuit 15, and the output end of the channel configuration circuit 15 is electrically connected to the memory 14.

[0079] Furthermore, in order to avoid the identification error between the normal operating condition and the firmware upgrade condition inside the electronic product 10, the pull-up resistor of the CC pin connected to the serial communication burner and the data transmission interface 11 can be set to 2K, and the pull-up voltage can be set to 3V, so that the detection voltage value of the data transmission interface 11 inside the electronic product 10 is 2.37v, and the connection method between the CC1 pin and the CC2 pin on the data transmission interface 11 and the serial communication burner is the same. According to the TypeC interface protocol, when the CC1 pin and the CC2 pin detect a voltage of 2.37v at the same time, it means that the TypeC interface is in the firmware upgrade condition at this time, so as to distinguish the normal operating condition and the firmware upgrade condition of the TypeC interface.

[0080] See also Figure 1 and Figure 2 , the memory 14 may include but is not limited to a main control module 141 and a flash memory module 142. The main control module 141 is used to process the firmware update data packet and generate target format data. The main control module 141 is also used to verify the target format data, generate target format data that passes the verification, and update the firmware in the flash memory module 142 according to the target format data that passes the verification, thereby solving the card lock problem in the memory 14. The flash memory module 142 may be a NAND Flash, which uses a NAND gate circuit to complete data storage, which means that the data can be retained even in the event of a power outage.

[0081] See also Figure 1 and Figure 3 The channel configuration circuit 15 may include but is not limited to multiple voltage comparison modules 151 and a logic judgment module 152, and the input end of the voltage comparison module 151 may be electrically connected to the data transmission interface 11, and its output end may be electrically connected to the input end of the logic judgment module 152. The voltage comparison module 151 can be used to output an initial high potential signal when the voltage output by the data transmission interface 11 is within a preset range.

[0082] The output terminal of the logic judgment module 152 can be electrically connected to the memory 14 to output a target high potential signal when the voltage comparison module 151 outputs an initial high potential signal. The preset voltage range can be 2.2V to 2.5V.

[0083] Further, the voltage comparison module 151 may include but is not limited to a first comparison unit 1511 and a second comparison unit 1512. The input end of the first comparison unit 1511 may be electrically connected to the data transmission interface 11, and the output end thereof may be electrically connected to the logic judgment module 152, so as to output a first initial high potential signal when the voltage output by the data transmission interface 11 is greater than the minimum value of the preset interval.

[0084] The input end of the second comparison unit 1512 can be electrically connected to the data transmission interface 11, the output end of the second comparison unit 1512 can be electrically connected to the logic judgment module 152, and the second comparison unit 1512 is used to output a second initial high potential signal when the voltage output by the data transmission interface 11 is less than the maximum value of the preset interval. The logic judgment module 152 can be used to output a target high potential signal when receiving the first initial high potential signal and the second initial high potential signal to control the conduction between the data transmission interface 11 and the memory 14.

[0085] For example, see Figure 3 , the channel configuration circuit 15 may include two voltage comparison modules 151 and a logic judgment module 152. The voltage comparison module 151 is provided with a first comparison unit 1511 and a second comparison unit 1512, and the input end of the first voltage comparison module 151 is electrically connected to the CC1 pin on the data transmission interface 11, and the input end of the second voltage comparison module 151 is electrically connected to the CC2 pin on the data transmission interface 11, so as to respectively judge whether the voltages on the CC1 pin and the CC2 pin are within the preset interval of 2.2V-2.5V.

[0086] Furthermore, since the judgment logic of the comparison unit is that when the right input voltage is greater than the left input voltage, a high potential signal is output. Therefore, the left pin of the first comparison unit 1511 can be set to 2.2V, and the right pin is electrically connected to the CC1 pin, so that when the voltage of the CC1 pin is greater than 2.2V, the first comparison unit 1511 outputs a first initial high potential signal. The left pin of the second comparison unit 1512 can be electrically connected to the CC1 pin, and the right pin is set to 2.5V, so that when the voltage of the CC1 pin is less than 2.5V, the second comparison unit 1512 outputs a second initial high potential signal. The connection relationship between the CC2 pin and the first comparison unit 1511 and the second comparison unit 1512 in the second voltage comparison module 151 is the same as the connection relationship between the CC1 pin and the first comparison unit 1511 and the second comparison unit 1512 in the first voltage comparison module 151.

[0087] Furthermore, the logic judgment module 152 may include three logic subunits 1521, and the logic subunits 1521 may be AND gate judgment units. The first logic subunit 1521 may be electrically connected to the first comparison unit 1511 and the second comparison unit 1512 in the first voltage comparison module 151, respectively, so that when the first comparison unit 1511 outputs the first initial high potential signal and the second comparison unit 1512 outputs the second initial high potential signal, it outputs the first intermediate high potential signal. Similarly, the second logic subunit 1521 may be electrically connected to the first comparison unit 1511 and the second comparison unit 1512 in the second voltage comparison module 151, respectively, so that when the first comparison unit 1511 outputs the first initial high potential signal and the second comparison unit 1512 outputs the second initial high potential signal, it outputs the second intermediate high potential signal. The input end of the third logic subunit 1521 can be electrically connected to the first logic subunit 1521 and the second logic subunit 1521 respectively, so that when the first logic subunit 1521 outputs the first initial high potential signal and the second logic subunit 1521 outputs the second initial high potential signal, it outputs the target high potential signal.

[0088] See also Figure 1 , Figure 2 and Figure 3 The main control module 141 may include but is not limited to a serial communication switch 1411, a serial parsing unit 1412 and a format conversion unit 1413. The input end of the serial communication switch 1411 may be communicatively connected to the logic judgment module 152, and the output end thereof may be communicatively connected to the serial parsing unit 1412, so that when it determines that a target high potential signal is received, it may be connected to the data transmission interface 11, thereby receiving a firmware update data packet.

[0089] It should be noted that the serial communication switch 1411 may include a plurality of sub-switches, and the input end of the sub-switch is communicatively connected to the logic judgment module 152, and the output end thereof is communicatively connected to the memory 14. For example, the serial communication switch 1411 may include a first sub-switch and a second sub-switch, and both the first sub-switch and the second sub-switch are N-type metal oxide semiconductor transistors (NMOS transistors).

[0090] Among them, the NMOS transistor may include a source, a drain, and a gate. The source of the first sub-switch may be connected to the SDA pin on the data transmission interface 11, the drain of the first sub-switch may be connected to the corresponding SDA pin on the memory 14, and the gate of the first sub-switch may be connected to the logic judgment module 152. Similarly, the source of the second sub-switch may be connected to the SCL pin on the data transmission interface 11, the drain of the second sub-switch may be connected to the corresponding SCL pin on the memory 14, and the gate of the first sub-switch may be connected to the logic judgment module 152, so that when the gates of the first sub-switch and the second sub-switch both receive the target high potential signal, the serial communication switch 1411 is turned on, and the memory 14 obtains the firmware update data packet.

[0091] See also Figure 1 , Figure 2 and Figure 3 The serial parsing unit 1412 can be used to perform logic parsing on the firmware update data packet received by the serial communication switch 1411 to generate corresponding parsing data. The parsing data may include but is not limited to a start address, a device address, a logic block address, a data length, an update data, a write command sequence number, and a write command parameter. For example, the parsing data may also include a cyclic redundancy check code (CRC) and an end address.

[0092] See also Figure 1 , Figure 2 and Figure 3 The format conversion unit 1413 is used to perform format conversion processing on the parsed data when receiving the parsed data to generate target format data. The format conversion processing refers to converting the parsed data obtained by the serial communication interface into target format data that can be stored in the eMMC memory.

[0093] See also Figure 1 , Figure 2 and Figure 3 Furthermore, the main control module 141 also includes a verification unit 1414, a cache unit 1415 and a command parsing unit 1416. When receiving the target format data, the verification unit 1414 verifies the target format data and sends the target format data that has passed the verification to the format conversion unit 1413. When receiving the target format data that has passed the verification, the format conversion unit 1413 writes the updated data in the target format data that has passed the verification into the cache unit 1415. In other words, the cache unit 1415 is used to receive the updated data in the target format data that has passed the verification sent by the format conversion unit 1413.

[0094] However, the format conversion unit 1413 is not limited thereto, and is further configured to determine whether all the update data are written into the cache unit 1415. If all the update data are written into the cache unit 1415, the write command sequence number and the write command parameters are sequentially sent to the command parsing unit 1416. If all the update data are not written into the cache unit 1415, the update data continues to be written into the cache unit 1415, and the determination is repeated until all the update data are written into the cache unit 1415. That is, the command parsing unit 1416 can be configured to receive the write command sequence number and the write command parameters sent by the format conversion unit 1413.

[0095] The verification unit 1414 verifies the target format data by judging whether the cyclic redundancy check code CRC in the target format data is normal. If the CRC is normal, the target format data is judged to be qualified. Otherwise, it is necessary to re-acquire the firmware update data packet, perform parsing processing, format conversion processing and verification processing on it, until the target format data is qualified.

[0096] It should be noted that the cache unit 1415 (data buffer) is a temporary flash memory unit located in the memory 14, which is used to temporarily store the data before sending the data to the flash memory module 142. The existence of the cache unit 1415 can help deal with problems caused by mismatched data transmission rates or differences in processing speeds, and improve the efficiency and stability of data processing.

[0097] See also Figure 1 , Figure 2 and Figure 3 In one embodiment of the present invention, for example, the length of the parsed data can be 8 bits, and each unit is 512 bytes. In addition, the preset write address can be set to 0x55, and the serial parsing unit 1412 needs to determine whether the device address obtained after the logical parsing process is 0x55. If the device address is 0x55, the logical block address (Logical Block Addressing, LBA) needs to be written into the logical block address register unit, and the data length needs to be written into the corresponding data length register unit. In addition, the update data also needs to be written into the cache unit 1415.

[0098] It is worth further explaining that, when the format conversion unit 1413 determines that all the update data are written into the cache unit 1415, it needs to send the write command sequence number (Command, CMD) and the write command parameter (Argument, Arg) in sequence to the command parsing unit 1416. The format conversion unit 1413 is also used to generate write reply information when it is determined that the write command sequence number and the write command parameter are all sent to the command parsing unit 1416, and send it to the host end through the serial communication protocol.

[0099] See also Figure 1 , Figure 2 and Figure 3 Furthermore, the main control module 141 also includes a flash memory control unit 1417, and the flash memory control unit 1417 is in communication with the command parsing unit 1416. The command parsing unit 1416 is also used to perform command parsing processing on the write command sequence number and the write command parameter to generate a write control command. The flash memory control unit 1417 is used to control the flash memory module 142 to obtain the update data in the cache unit 1415 through the flash memory input interface in the main control module 141 according to the write control command, so as to update the firmware in the flash memory module 142.

[0100] It is worth further explaining that the host side can determine whether the write reply information is the same as the normal write information / abnormal write information. If the write reply information is the same as the normal write information, the update is assumed to be successful, and after waiting for a preset time, the next firmware update data packet is selected for burning until all firmware updates are completed. If the write reply information is the same as the abnormal write information, the update is abnormal, and it is necessary to repeatedly select the corresponding firmware update data packet for burning after waiting for a preset time, generate a firmware update data packet, and send the firmware update data packet to the corresponding memory 14 to repeat the firmware update process until the acquired write reply information is the same as the normal write information. Among them, the preset time can be 100 milliseconds, 200 milliseconds, or other cycles.

[0101] See also Figure 1 and Figure 2 For example, the normal write information can be set to 0x00, and the abnormal write information can be set to 0xFF. That is, when the write reply information is 0x00, it can be judged by default that the firmware update is successful, and the host side can continue to select the next firmware update data packet for burning after waiting for 100 milliseconds until the firmware is fully updated. When the write reply information is 0xFF, it can be judged that the firmware update is abnormal, and the host side needs to repeatedly select the corresponding firmware update data packet for burning after waiting for 100 milliseconds, generate a firmware update data packet, and send the firmware update data packet to the corresponding memory 14 to repeat the firmware update process until the acquired write reply information is 0x00.

[0102] The main control module 141 may also include a register modification unit 1418 and a register unit 1419, and the register modification unit 1418 is respectively connected to the format conversion unit 1413 and the register unit 1419 for communication. The parsed data may include a start address, a device address, a logic block address, a data length, an update data, a register address, and a register modification value. When the format conversion unit 1413 receives the parsed data, it still performs format conversion processing on the parsed data to generate target format data. When the verification unit 1414 receives the target format data, it still performs verification processing on the target format data, and sends the verified target format data to the format conversion unit 1413.

[0103] It should be noted that, unlike the command parsing unit 1416 and the flash control unit 1417 provided in the main control module 141, when the format conversion unit 1413 receives the target format data that has passed the verification, it needs to send the register address and the register modification value in the target format data to the register modification unit 1418. The register modification unit 1418 is used to modify the register value of the register unit 1419 according to the register address and the register modification value, and generate a new register value to solve the compatibility problem of the memory 14 caused by the register value, reduce the maintenance cost and cycle of electronic products, and improve the user experience.

[0104] The main control module 141 also includes a storage interface 143, whose input end is connected to the central controller 12 for communication, and supports data transmission between the central controller 12 and the memory 14 when the memory 14 is operating normally. The output end of the storage interface 143 can be connected to the command parsing unit 1416 for communication, and is used to send the read and write instructions sent by the central controller 12 to the command parsing unit 1416 for parsing and processing, so that the subsequent data can be stored in the flash memory module 142.

[0105] See also Figure 5 The present invention also provides a memory firmware update method for an electronic product, which can be applied to the above electronic product to perform a memory firmware update process on the electronic product provided with a Type-C interface. The update method corresponds one-to-one to the electronic product in the above embodiment, and the memory firmware update method may include the following steps.

[0106] Step S10: Power on the memory.

[0107] Step S20: The channel configuration circuit controls the connection between the data transmission interface and the memory, and the data transmission interface sends the firmware update data packet to the memory.

[0108] Step S30: The memory processes the firmware update data packet to generate target format data.

[0109] Step S40: The memory performs verification processing on the target format data to generate target format data that passes the verification.

[0110] Step S50: The memory updates the firmware in the flash memory module according to the verified qualified target format data.

[0111] See also Figure 6 In one embodiment of the present invention, when executing step S30, specifically, step S30 may include the following steps.

[0112] Step S31, performing logic analysis on the firmware update data packet to generate corresponding analysis data, wherein the analysis data includes a start address, a device address, a logic block address, a data length, update data, a write command sequence number, and write command parameters.

[0113] Step S32: Perform format conversion on the parsed data to generate target format data.

[0114] See also Figure 7 In one embodiment of the present invention, when executing step S50, specifically, step S50 may include the following steps.

[0115] Step S51: The format conversion unit writes the updated data in the verified qualified target format data into the cache unit.

[0116] Step S52: When all the update data are written into the cache unit, the format conversion unit sends the write command sequence number and the write command parameters to the command parsing unit in sequence.

[0117] Step S53: The command parsing unit performs command parsing processing on the write command sequence number and the write command parameters to generate a write control command.

[0118] Step S54: The flash memory control unit controls the flash memory module to obtain the update data in the cache unit according to the write control command, so as to update the firmware in the flash memory module.

[0119] It can be seen that in the above scheme, when an electronic product only equipped with a Type C interface cannot be turned on normally and a card lock problem occurs in its internal memory, the connection between the memory and the data transmission interface can be controlled by the channel configuration circuit, so that the firmware update data packet can be sent to the memory through an independent serial communication protocol to realize a forced update of the memory firmware. This can effectively improve the firmware update efficiency of the memory in the electronic product, reduce the maintenance cost and cycle of the electronic product, and improve the user experience.

[0120] Furthermore, by setting a register modification unit based on the above-mentioned memory, the register value of the register unit is modified according to the register address and the register modification value to generate a new register value, so as to solve the compatibility problem of the memory caused by the register value, reduce the maintenance cost and cycle of electronic products, and further improve the user experience.

[0121] In the description of this specification, the description with reference to the terms "this embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0122] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to specific implementation methods. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. An electronic product, characterized in that: include: A data transmission interface, which is connected to the host end for receiving a firmware update data packet burned by the host end, and the data transmission interface is a Type C interface; A connecting circuit, the input end of which is electrically connected to the data transmission interface; A central controller is electrically connected to the output end of the connection circuit, and the central controller is communicatively connected to the memory to power on the memory; A memory, which is communicatively connected to the data transmission interface via a serial communication protocol and receives a firmware update data packet via the data transmission interface, wherein the memory includes a main control module and a flash memory module; as well as A channel configuration circuit is electrically connected between the data transmission interface and the memory, and when the firmware in the memory is updated, the channel configuration circuit controls the connection between the data transmission interface and the memory; Wherein, the channel configuration circuit comprises: a plurality of voltage comparison modules, whose input ends are electrically connected to the data transmission interface, and are used to output an initial high potential signal when the voltage output by the data transmission interface is within a preset interval; and a logic judgment module, whose input end is electrically connected to the output end of the voltage comparison module, and whose output end is electrically connected to the memory, for outputting a target high potential signal when the voltage comparison module outputs the initial high potential signal; The main control module comprises: a serial communication switch, for disconnecting from the data transmission interface when the target high potential signal is not received, and for connecting to the data transmission interface when the target high potential signal is received to receive the firmware update data packet; When the firmware in the memory is updated, the data transmission interface sends the firmware update data packet to the memory; The main control module is used to process the firmware update data packet to generate target format data; The main control module is also used to perform verification processing on the target format data to generate target format data that passes the verification; The main control module is also used to update the firmware in the flash memory module according to the verified qualified target format data.

2. The electronic product according to claim 1, characterized in that: The voltage comparison module comprises: A first comparison unit, whose input end is electrically connected to the data transmission interface, and whose output end is electrically connected to the logic judgment module, is used to output a first initial high potential signal when the voltage output by the data transmission interface is greater than the minimum value of the preset interval; and A second comparison unit, whose input end is electrically connected to the data transmission interface, and whose output end is electrically connected to the logic judgment module, is used to output a second initial high potential signal when the voltage output by the data transmission interface is less than the maximum value of the preset interval; The logic judgment module is used to output the target high potential signal when receiving the first initial high potential signal and the second initial high potential signal.

3. The electronic product according to claim 1, characterized in that: The main control module also includes: a serial parsing unit, configured to perform logic parsing processing on the firmware update data packet upon receiving the firmware update data packet, and generate corresponding parsing data, wherein the parsing data includes a start address, a device address, a logic block address, a data length, an update data, a write command sequence number, and a write command parameter; and The format parsing unit is used to perform format conversion processing on the parsed data when receiving the parsed data to generate the target format data.

4. The electronic product according to claim 1, characterized in that: The main control module also includes: A verification unit, configured to verify the target format data when receiving the target format data, and send the target format data that passes the verification to the format conversion unit; A cache unit, used for receiving the updated data in the target format data that has passed the verification and is sent by the format conversion unit; The command parsing unit is used to receive the write command sequence number and write command parameters sent by the format conversion unit.

5. The electronic product according to claim 4, characterized in that: The format conversion unit is also used to generate write reply information when the write command sequence number and write command parameters are all sent to the command parsing unit, and send it to the host end through the serial communication protocol.

6. The electronic product according to claim 4, characterized in that: The main control module also includes a flash memory control unit, and the command parsing unit is also used to perform command parsing processing on the write command sequence number and the write command parameters to generate a write control command. The flash memory control unit controls the flash memory module to obtain the updated data in the cache unit according to the write control command.

7. The electronic product according to claim 1, characterized in that: The main control module includes a register modification unit and a register unit, and the parsed data includes a register address and a register modification value; The register modification unit is used to receive the register address and the register modification value in the target format data that has passed the verification sent by the format conversion unit, and perform register value modification processing on the register unit according to the register address and the register modification value.

8. A method for updating memory firmware of an electronic product, characterized in that: include: Power on the memory; The channel configuration circuit controls the connection between the data transmission interface and the memory, and the data transmission interface sends the firmware update data packet to the memory, wherein the data transmission interface is a Type C interface; The memory processes the firmware update data packet to generate target format data; The memory performs verification processing on the target format data to generate verified target format data; The memory updates the firmware in the flash memory module according to the verified qualified target format data; Wherein, the channel configuration circuit comprises: a plurality of voltage comparison modules, whose input ends are electrically connected to the data transmission interface, and are used to output an initial high potential signal when the voltage output by the data transmission interface is within a preset interval; and a logic judgment module, whose input end is electrically connected to the output end of the voltage comparison module, and whose output end is electrically connected to the memory, for outputting a target high potential signal when the voltage comparison module outputs the initial high potential signal; The memory includes a main control module and a flash memory module, and the main control module includes: The serial communication switch is used to disconnect from the data transmission interface when the target high-voltage signal is not received, and to connect to the data transmission interface when the target high-voltage signal is received to receive the firmware update data packet.

9. The memory firmware updating method of an electronic product according to claim 8, characterized in that: The step of the memory updating the firmware in the flash memory module according to the verified qualified target format data comprises: The format conversion unit writes the updated data in the verified qualified target format data into the cache unit; When all the update data are written into the cache unit, the format conversion unit sends the write command sequence number and the write command parameters to the command parsing unit in sequence; The command parsing unit performs command parsing processing on the write command sequence number and the write command parameter to generate a write control command; The flash memory control unit controls the flash memory module to obtain the update data in the cache unit according to the write control command, so as to update the firmware in the flash memory module.

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