RISC-V vector register release method and device

Abstract

The invention relates to the technical field of computers, and particularly discloses an RISC-V vector register release method and device.The method comprises the steps that in response to a vector instruction, multiple pieces of vector target register mapping information of the vector instruction are stored in a preset circular cache list in a reordering cache; and reordering caching is assisted through the circular cache list, and a vector target register corresponding to the vector target register mapping information is released by taking a register identified by a register decommissioning item in the circular cache list as granularity. Therefore, hardware resources required by each ROB item do not need to be greatly increased, and the vector register is released into the FRL as soon as possible, so that the utilization efficiency of the vector physical register is improved. According to the scheme, on the basis of an original ROB, the following changes aiming at the vector instruction are provided.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a RISC-V vector register release method and device. Background Art

[0002] Many CPU cores implement register renaming, which maps an architectural register to a physical register in the core to avoid false register dependencies such as write-after-read and write-after-write, and to improve the parallelism (ILP) and performance of CPU instruction processing. For such CPU cores that implement register renaming, masked instructions need to copy unmasked fields from the old target physical register A to the new target physical register B mapped by the same architectural register to ensure that the values ​​of these fields do not change. At this time, a masked instruction needs to read four different physical register values: 2 sources, 1 mask, and a currently mapped target physical register. Register renaming is usually completed through the following hardware buffers: Speculative rename table (SRT): Saves the latest (but possibly incorrect, flushed) mapping relationship between architectural registers and physical registers. Architectural rename table (ART): Saves the mapping relationship between architectural registers and physical registers in the architectural state. Free register list (FRL): Generally implemented as a bit list, with one bit for each physical register. A bit value of 1 indicates that the physical register is not currently in use. Reorder buffer (ROB): ROB is a first-in-first-out (FIFO) circular buffer used to maintain the order relationship between instructions in an out-of-order CPU core.

[0003] When an instruction performs register renaming, the renaming unit performs the following operations: query the SRT to find the currently mapped physical register for each source architectural register. When the instruction is subsequently inserted into the ROB at the Dispatch pipeline stage, the renaming information of its target register is also saved in the corresponding ROB entry. For each target architectural register, select a physical register with a corresponding FRL bit of 1, write the mapping into the SRT entry corresponding to the target architectural register, and set the FRL bit to 0. In subsequent executions, the instruction (or its corresponding one or more microinstructions) reads and writes these physical registers.

[0004] At the Retire pipeline stage, if the oldest instruction (i.e., at the head of the ROB) has been executed and no exception has occurred, it can be retired, that is, the hardware resources used by these instructions, including the physical registers mapped by them, are released. At this time, the mapping relationship between the target architectural register and the physical register will be written into the architectural renaming table ART. The physical register replaced in the ART will have its FRL bit set to 1, and can be reused in a new register mapping in the next clock cycle. Another function of the ART is to restore the SRT when a pipeline flush caused by a branch prediction error occurs. When a pipeline flush caused by a branch prediction error occurs, the branch prediction instruction that triggers the flush is not necessarily the oldest instruction in the pipeline. At this time, the following operations are required to restore the SRT content up to that instruction: Clear and temporarily suspend the CPU pipeline. Clear all instruction items in the ROB that are younger than the branch instruction. Write each item of the ART into the corresponding item of the SRT. Starting from the first item of the ROB, write its target register mapping content into the SRT. The CPU pipeline resumes operation and starts fetching and executing instructions from the correct instruction address after the corrected branch instruction.

[0005] Both scalar and vector instructions may have exceptions. Exception handling is performed when the instruction is the oldest instruction in the pipeline. When RISC-V handles vector instruction exceptions, it first saves the location of the field where the exception occurred in the target register (group) in the vstart CSR register, writes all field data of the instruction with an index less than the exception index into the target register, and then performs exception handling. After the exception is handled, the vector instruction is re-executed, and the instruction will read the vstart value. The masks of all fields with an index less than the vstart value are set to 0, that is, their results will not be written to the corresponding positions in the target register.

[0006] The solution of simply extending the existing scalar ROB to support RISC-V vector instructions is that the physical register release is still performed at the instruction granularity. However, this solution will face the following problems when extended to RISC-V vector instructions: each ROB item needs to save the mapping information of all target architectures to physical registers. A RISC-V vector instruction can have up to 8 target registers, and these register mapping information needs to be saved in the ROB item, which greatly increases the hardware resources required for each ROB item. However, RISC-V scalar instructions only have 0 or 1 target registers, and most of the register mapping fields in the ROB items of these instructions are not used, resulting in excessive ROB items and wasting hardware resources. A RISC-V vector instruction can have up to 8 target registers. If these target registers can only be released after the instruction is ready, it is possible to delay the release time of these physical registers, thereby reducing the frequency of these physical registers being reused, reducing the utilization efficiency of the vector physical register file, affecting performance or increasing the area of ​​the vector physical register file.

[0007] In the above solution, all register mapping information is stored in the ROB, and physical register release is performed at the instruction granularity. This solution will cause the ROB items to have too many fields that are often not used, and the use cycle of physical vector registers is too long. These two problems will increase the hardware resources required for the ROB and cause performance loss due to insufficient number of vector physical registers. In order to avoid the above performance loss, the number of registers in the vector register file must be increased, further increasing the hardware resources required for the ROB.

[0008] To address the above problems, no effective solution has been proposed yet. Summary of the invention

[0009] The embodiments of this specification provide a RISC-V vector register release method and device, an optimized RISC-V vector instruction ROB extension scheme, which uses physical registers as the granularity for release, can release physical vector registers as soon as possible, and improve the utilization efficiency of vector register files. Therefore, it is possible to use fewer hardware resources and fewer register files to achieve the same performance as a simple extension scheme.

[0010] An embodiment of this specification provides a RISC-V vector register release method, including:

[0011] In response to a vector instruction, multiple vector target register mapping information of the vector instruction is stored in a circular cache list preset in a reorder cache; the reorder cache is assisted by the circular cache list, and the vector target register corresponding to the vector target register mapping information is released at a granularity of a register identified by a register retirement item in the circular cache list.

[0012] In one embodiment, the method further comprises:

[0013] A circular cache entry identification field is set in the reorder cache entry, wherein the circular cache entry identification field is used to configure different values ​​according to the vector target register corresponding to the vector instruction.

[0014] In one embodiment, the method further comprises:

[0015] In response to a vector instruction, scalar register mapping information of the vector instruction is stored in the architectural register and physical register fields in the re-order buffer.

[0016] In one embodiment, the method further comprises:

[0017] The circular cache list allocates a register retirement entry for each vector target register corresponding to the vector instruction; wherein the register retirement entry includes a circular cache list index, a vector instruction index field corresponding to the reorder cache, a target architecture register field, a corresponding target physical register field, a vector instruction processing exception record identification field and a register write microinstruction quantity field.

[0018] In one embodiment, releasing the vector target register corresponding to the vector target register mapping information with the register identified by the register retirement item in the circular cache list as the granularity comprises: sequentially releasing registers starting from the item pointed to by the preset circular cache pointer head in each clock cycle; sequentially allocating vector register mapping starting from the item pointed to by the preset circular cache pointer tail in each clock cycle; wherein the circular cache pointer head points to the longest valid item in the circular cache list, and the circular cache pointer tail points to the first invalid item in the circular cache list.

[0019] In one embodiment, the number field of the register write microinstruction is used to initialize and generate a corresponding numerical value according to the number of vector microinstructions written into the vector target register corresponding to the register retirement item as needed; and to make corresponding numerical adjustments according to the execution status of the vector microinstruction; wherein the vector microinstruction is generated by decoding the vector instruction.

[0020] In one embodiment, the number field of the register write microinstruction is used to initialize and generate the corresponding number of fields or bytes according to the number of vector microinstructions that need to be written into the vector target register corresponding to the register retirement item; and to adjust the corresponding number of fields or bytes according to the execution status of the vector microinstruction; wherein the vector microinstruction is generated by decoding the vector instruction.

[0021] In one embodiment, each clock cycle starts to release registers sequentially through the item pointed to by the preset circular cache pointer head, including: starting to identify all consecutive register retirement items that are filled with the number field of the register write microinstructions in the register retirement items by microinstructions and have no vector instruction processing exceptions according to the item pointed to by the preset circular cache pointer head; releasing the corresponding registers through the identified register retirement items, storing the register mapping corresponding to the register retirement items in the architecture rename table, and releasing the physical registers in the replaced items in the architecture rename table to the free register table for subsequent calls.

[0022] An embodiment of the present specification also provides a RISC-V vector register release device, the device comprising: an allocation module and a release module; the allocation module is used to store multiple vector target register mapping information of the vector instruction in a circular cache list preset in the reorder cache in response to the vector instruction; the release module is used to assist the reorder cache through the circular cache list, and release the vector target register corresponding to the vector target register mapping information at the granularity of the register identified by the register retirement item in the circular cache list.

[0023] An embodiment of the present specification also provides a central processing unit, which includes a central processing core with a reordering cache based on instructions, microinstructions and macroinstructions, and the central processing unit applies the above-mentioned RISC-V vector register release method.

[0024] For a RISC-V CPU core that implements RISC-V vector extension, the RISC-V vector register release method and device provided by this application, compared with the traditional solution, does not need to significantly increase the hardware resources required for each ROB item, and releases the vector register into FRL as soon as possible to improve the utilization efficiency of vector physical registers. Based on the original ROB, this solution proposes the following changes to vector instructions.

[0025] With reference to the following description and drawings, specific embodiments of the present invention are disclosed in detail, indicating the manner in which the principles of the present invention can be adopted. It should be understood that the embodiments of the present invention are not limited in scope. Features described and / or shown for one embodiment can be used in one or more other embodiments in the same or similar manner, combined with features in other embodiments, or replace features in other embodiments.

[0026] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, parts, steps or components, but does not exclude the presence or addition of one or more other features, parts, steps or components. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings described herein are used to provide a further understanding of this specification, constitute a part of this specification, and do not constitute a limitation of this specification. In the drawings:

[0028] Figure 1 A flowchart of a RISC-V vector register release method provided in an embodiment of the present application;

[0029] Figure 2 A schematic diagram of the application effect of the RISC-V vector register release method provided in one embodiment of the present application;

[0030] Figure 3 It is an example diagram of multiple pipeline stages of a CPU architecture in the prior art;

[0031] Figure 4 A schematic diagram of a release process provided in another embodiment of the present application;

[0032] Figure 5 A schematic diagram of the structure of a RISC-V vector register release device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0033] The principles and spirit of this specification will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are provided only to enable those skilled in the art to better understand and implement this specification, and are not intended to limit the scope of this specification in any way. On the contrary, these embodiments are provided to make this specification more thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art.

[0034] Those skilled in the art will appreciate that the embodiments of this specification may be implemented as a system, device, method, or computer program product. Therefore, this specification may be implemented in the following forms: complete hardware, complete software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0035] The details of the present invention can be more clearly understood by combining the accompanying drawings and the description of the specific embodiments of the present invention. However, the specific embodiments of the present invention described herein are only used for the purpose of explaining the present invention and cannot be understood as limiting the present invention in any way. Under the guidance of the present invention, technicians can conceive of any possible variations based on the present invention, which should be regarded as belonging to the scope of the present invention. It should be noted that when an element is referred to as "arranged on" another element, it can be directly on another element or there can also be a central element. When an element is considered to be "connected" to another element, it can be directly connected to another element or there may be a central element at the same time. The terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a mechanical connection or an electrical connection, or it can be the communication between the two elements, it can be directly connected, or it can be indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to the specific circumstances. The terms "vertical", "horizontal", "up", "down", "left", "right" and similar expressions used herein are only for illustrative purposes and do not represent the only implementation method.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this specification belongs. The terms used herein in this specification are only for the purpose of describing specific embodiments and are not intended to limit this specification. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0037] The embodiments of this specification provide a method for releasing hardware resources for a RISC-V vector store. Figure 1 A flowchart of a RISC-V vector register release method in an embodiment of this specification is shown. Although this specification provides method operation steps or device structures as shown in the following embodiments or drawings, more or fewer operation steps or module units may be included in the method or device based on routine or no creative labor. In the steps or structures where there is no necessary causal relationship logically, the execution order of these steps or the module structure of the device is not limited to the execution order or module structure described in the embodiments of this specification and shown in the drawings. When the method or module structure described is applied to an actual device or terminal product, it can be connected according to the method or module structure shown in the embodiment or drawings for sequential execution or parallel execution (for example, a parallel processor or a multi-threaded processing environment, or even a distributed processing environment).

[0038] Please refer to Figure 1 As shown, the RISC-V vector register release method provided in the embodiments of this specification may specifically include:

[0039] S101, in response to a vector instruction, storing a plurality of vector target register mapping information of the vector instruction in a circular cache list preset in a reorder cache;

[0040] S102 assists in reordering cache by using the circular cache list, and releases vector target registers corresponding to the vector target register mapping information at a granularity of registers identified by register retirement items in the circular cache list.

[0041] In this embodiment, the main purpose is to target the vector register file utilization efficiency defects caused by the existing register release with instructions as the granularity; specifically, the RISC-V vector instruction set is one of the many standard instruction set extensions of RISC-V, which is used to support the computing mode of single instruction multiple data (SIMD) to improve the computing power and efficiency of the corresponding CPU. The register width used by SIMD instructions is generally 128 bits or wider, and each vector register contains multiple integer fields with a width of 8 / 16 / 32 / 64 bits or 16 / 32 / 64-bit floating-point fields. In common SIMD instruction sets (such as AVX512 in X64), the register and data width corresponding to each instruction are fixed. A RISC-V vector instruction can be used for different register widths and data widths. The advantage of this is that an application using RISC-V vector instructions can run on a variety of CPU implementations with different register and vector pipeline widths without making any modifications. In RISC-V, the width of the field is represented by SEW (selected element width). However, in this method, since there are multiple microinstructions in the vector instruction, each microinstruction has a corresponding vector target register, and these vector target registers are only released after the entire vector instruction is completed, the vector target registers occupied by the executed microinstructions cannot be effectively released during this process, thereby reducing the efficiency of using the vector target registers. The above-mentioned embodiment provided by the present application sets a circular cache list to monitor the execution status of each microinstruction, and assists the reorder cache to release the vector target register at the granularity of the register, so that less hardware resources and fewer register files can be used to achieve the same performance as the simple expansion solution. The specific implementation method of each step will be described in detail in the subsequent embodiments, and will not be described in detail here.

[0042] In one embodiment, the method further comprises: setting a circular cache entry identification field in the reorder cache entry, wherein the circular cache entry identification field is used to configure different values ​​according to the vector target register corresponding to the vector instruction.

[0043] Specifically, in this embodiment, a 1-bit circular cache entry identification field (use_VRRB field) is added to the reorder buffer (ROB). If a vector instruction has one or more vector target registers, this bit is set to 1 when the ROB entry is allocated; otherwise, this bit is set to 0. In this way, the relevant situation of the corresponding vector target register can be determined through the use_VRRB field later.

[0044] In one embodiment, the method further comprises: in response to the vector instruction, storing scalar register mapping information of the vector instruction in architectural register and physical register fields in a re-order cache.

[0045] Specifically, in actual work, the existing architectural registers and physical register fields in the ROB are only used to store scalar register mappings, not vector register mappings. Some RISC-V vector instructions have scalar target registers, and the ROB entries corresponding to these instructions store the corresponding scalar register mapping information.

[0046] In one embodiment, the method further comprises: allocating, by the circular cache list, a register retirement entry for each vector target register corresponding to the vector instruction;

[0047] The register retirement item includes a circular cache list index, a vector instruction index field corresponding to the reorder cache, a target architecture register field, a corresponding target physical register field, a vector instruction processing exception record identification field, and a register write microinstruction quantity field.

[0048] Specifically, a new hardware table is added in this application: a circular cache list (vector registerretire buffer, VRRB), which is the same as the reorder buffer (Reorder buffer, ROB). VRRB is also a first-in first-out (First In First Out, FIFO) circular buffer. Each vector target register is assigned a VRRB item, i.e., a circular cache item. The VRRB item contains the following fields:

[0049] Circular cache list index IDX: provides VRRB index for sequential allocation and release of VRRB items;

[0050] Vector instruction index field IID corresponding to the reorder buffer: provides an instruction index, corresponding to the IID field in the ROB, used to identify the ROB item / instruction to which the VRRB item belongs;

[0051] Target architecture register field Arch_Reg: provides target architecture register information;

[0052] Corresponding target physical register field Phy_Reg: provides corresponding target physical register information;

[0053] The number of microinstructions written to the register field Cnt_Down: provides a register change counter to initialize the number of microinstructions generated for this instruction and written to this register. When a microinstruction is written to this physical register, the corresponding Cnt_Down value is reduced by one. If the Cnt_Down value of a field is 0, all fields in the register have been written.

[0054] Vector instruction processing exception record identification field Exception: The initial value is -1. If an exception occurs when the instruction / microinstruction processes a certain field, the index corresponding to the field will be written into this field.

[0055] Further, in one embodiment, releasing the vector target register corresponding to the vector target register mapping information with the register identified by the register retirement item in the circular cache list as the granularity includes: sequentially releasing registers starting from the item pointed to by the preset circular cache pointer head in each clock cycle; sequentially allocating vector register mapping starting from the item pointed to by the preset circular cache pointer tail in each clock cycle; wherein, the circular cache pointer head points to the longest valid item in the circular cache list, and the circular cache pointer tail points to the first invalid item in the circular cache list.

[0056] Specifically, in actual work, this application also provides two pointers:

[0057] Circular buffer pointer head VRRB head: points to the oldest valid item in VRRB, and attempts to release registers sequentially starting from the item pointed to by VRRB head in each clock cycle.

[0058] Circular buffer pointer tail VRRB tail: points to the first invalid item in VRRB. New vector register mapping is allocated sequentially starting from the item pointed to by VRRB tail in each clock cycle.

[0059] Please refer to Figure 2 As shown, Figure 2 In the RISC-V vector register release method provided in this application, ROB+VRRB supported by vector instructions is added; Figure 2The code in the example is a section of SAXPY (Scalar Alpha X Plus Y). SAXPY is a commonly used calculation operation in parallel vector processors. It is a combination of scalar multiplication and vector addition: v8 = fa0 * v0 + v8, where fa0 is a scalar, and v8 and v0 are vectors. In the example, the instruction with IID = 0 sets LMUL to 4 (m4), SEW = 32 (e32), and assumes VLEN = 128, so each register has 4 32-bit fields, and each vector instruction processes the contents of 4 target registers. The 6th and 7th instructions in the ROB (IID = 5 and 6) are vector ALU instructions. They each have 4 target registers, so each instruction is allocated 4 VRRB entries, as shown in the figure. The IID value in the VRRB entry is the IID value of its corresponding instruction in the ROB.

[0060] In one embodiment of the present application, each clock cycle starts to release registers sequentially through the item pointed to by the preset circular cache pointer head, which includes: starting to identify all consecutive register retirement items that are filled with the number field of the register write microinstructions in the register retirement items by microinstructions according to the item pointed to by the preset circular cache pointer head, and there are no vector instruction processing exceptions; releasing the corresponding registers through the identified register retirement items, storing the register mapping corresponding to the register retirement items in the architecture renaming table, and releasing the physical registers in the replaced items in the architecture renaming table to the free registration table for subsequent calls.

[0061] Specifically, Figure 2 As shown in the figure, in actual work, when a vector instruction becomes the oldest unreleased instruction in the ROB (that is, the ROB head points to its ROB item), if its use_VRRB field is 1, it has one or more corresponding VRRB items. At this time, the VRRB head pointer should point to the first VRRB item of the vector instruction. Starting from this VRRB head item, all consecutive VRRB items with Cnt_Down of 0 and Exception of -1 can be released, their register mappings will be written into the ART, and the VRRB head will move to the first item in the instruction that does not meet the above conditions; after all VRRB items of the instruction are released, the VRRB head will move to the first VRRB item of the next vector instruction. In the latter case, the VRRB will notify the ROB that the instruction has been fully executed and can be released from the ROB. As shown in the figure, the first two target registers of the instruction with IID=5 have been completely written without exception, and the third target register has a field that has not been written (Cnt_Down=1), so the first two registers can be released, and the VRRB head moves from IDX=0 item to IDX=2 item.

[0062] In one embodiment of the present application, the number field of the register write microinstruction is used to initialize and generate a corresponding numerical value, number of fields or number of bytes according to the number of vector microinstructions that need to be written into the vector target register corresponding to the register retirement item; and to adjust the corresponding numerical value, number of fields or number of bytes according to the execution status of the vector microinstruction; wherein the vector microinstruction is generated by decoding the vector instruction.

[0063] Specifically, in this application, the VRRB Cnt_Down field is initialized to the number of microinstructions written to the register. A possible solution is to set the field to the number of fields (VLEN / SEW), or always initialize it to the number of bytes (VLEN / 8). In these two alternatives, the rewrite time of Cnt_Down is the same as this solution, except that the number of Cnt_Down reductions is the number of fields written and the number of bytes written, respectively.

[0064] In order to more clearly understand the application of the RISC-V vector register release method provided by this application in actual work, please refer to Figure 3 As shown, in order to improve performance, modern CPU architectures generally include multiple pipeline stages, including branch prediction, instruction cache, instruction decoding, register renaming, distribution, execution, and retirement.

[0065] This application mainly adjusts the dispatch, execution and retirement, as follows:

[0066] Dispatch: Information related to an instruction is written into the ROB. If the instruction is a vector instruction with a vector target register, the instruction is allocated the same number of VRRB items as the target register, and the contents of these items are initialized. This stage also saves the current number of free VRRB items. If there are not enough VRRB items at this time, the vector microinstructions that have not been allocated VRRB items will stall in the Dispatch stage and wait for free VRRB items to be released in the next clock cycle.

[0067] Execution: When a vector microinstruction is executed and the result is written into the register file, the Cnt_Down field of its VRRB item is reduced by 1. If an exception occurs, the index of the exception field is written into the Exception field of the corresponding VRRB item.

[0068] Retire: Perform the following operations on the oldest item in ROB: Figure 4 The following operations are shown:

[0069] 1. First check the Use_VRRB value in the ROB head item. If it is 1, that is, the item has at least one VRRB item, jump to step 4; otherwise, execute the next step.

[0070] 2. Check whether the instruction without VRRB item is abnormal. If it is abnormal, the exception handling is triggered and the process ends; otherwise, go to the next step.

[0071] 3. Determine whether the instruction has been executed. If it has been executed, jump to step 11; otherwise, the instruction has not been executed and cannot be retired, so the process ends.

[0072] 4. Read the VRRB item pointed to by the VRRB head pointer.

[0073] 5. If the Cnt_Down item is not 0, the corresponding vector uop has not been executed and ends; otherwise, execute the next step.

[0074] 6. If the Exception item is not zero, it indicates that the corresponding vector uop execution exception occurs, and execute the next step; otherwise, jump to step 8.

[0075] 7. Send the exception index to ROB. After receiving it, ROB saves the exception index in vstart CSR, then triggers exception processing and ends.

[0076] 8. At this time, the uop corresponding to the VRRB head item has been executed without exception, and the register mapping of this item is written to the vector ART, and the physical register in the replaced item in the vector ART is released to the vector FRL.

[0077] 9. Release the VRRB head item, that is, move the VRRB head pointer to the next position (VRRB_head+1)%VRRB_size, and notify the Dispatch stage that the VRRB item is released.

[0078] 10. Determine whether the new VRRB head item has the same IID as the old VRRB head item. If yes, jump to step 4; otherwise, execute the next step.

[0079] 11. At this point, the instruction corresponding to the ROB head item has completed execution without exception and can be retired. If the item has a scalar register mapping, write the mapping to the scalar ART and release the physical registers in the replaced item in the vector ART to the vector FRL.

[0080] 12. Release the ROB head item, that is, move the ROB head pointer to the next position (ROB_head+1)%ROB_size, and end.

[0081] Please refer to Figure 5 As shown, the embodiment of this specification also provides a RISC-V vector register release device, the device includes an allocation module 501 and a release module 502; the allocation module 501 is used to respond to the vector instruction, and store multiple vector target register mapping information of the vector instruction in a circular cache list preset in the reorder cache; the release module 502 is used to assist the reorder cache through the circular cache list, and release the vector target register corresponding to the vector target register mapping information with the register identified by the register retirement item in the circular cache list as the granularity. Since the principle of solving the problem by the device is similar to the RISC-V vector register release method, the implementation of the device can refer to the implementation of the RISC-V vector register release method, and the repeated parts will not be repeated.

[0082] An embodiment of the present specification also provides a central processing unit, which includes a central processing core with a reordering cache based on instructions, microinstructions and macroinstructions, and the central processing unit applies the above-mentioned RISC-V vector register release method.

[0083] In the above embodiments, in many CPU cores, ROB does not store instructions, but stores microinstructions (microuop) or macroinstructions (macro op), which are specific conversion formats of instructions in a CPU core: an instruction may be converted into one or more microinstructions / macroinstructions, or two instructions may be merged into one microinstruction / macroinstruction, etc. ROBs based on instructions / microinstructions / macroinstructions are all designed for scalar instructions, and face the same problems for vector instructions. Therefore, the present application is also applicable to CPU cores using ROBs based on microinstructions / macroinstructions. Similarly, the present application is also applicable to high-performance, superscalar CPU cores that can rename, execute, and retire multiple instructions in one clock cycle.

[0084] For a RISC-V CPU core that implements RISC-V vector extension, the RISC-V vector register release method and device provided by this application, compared with the traditional solution, does not need to significantly increase the hardware resources required for each ROB item, and releases the vector register into FRL as soon as possible to improve the utilization efficiency of vector physical registers. Based on the original ROB, this solution proposes the following changes to vector instructions.

[0085] Obviously, those skilled in the art should understand that the modules or steps of the above-mentioned embodiments of this specification can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. In this way, the embodiments of this specification are not limited to any specific combination of hardware and software.

[0086] It should be understood that the above description is for illustration and not for limitation. Many embodiments and many applications beyond the examples provided will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of this specification should not be determined with reference to the above description, but should be determined with reference to the preceding claims and the full scope of equivalents to which these claims belong.

[0087] The above description is only the preferred embodiment of this specification and is not intended to limit this specification. For those skilled in the art, the embodiments of this specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this specification shall be included in the protection scope of this specification.

Claims

1. A RISC-V vector register release method, It is characterized in that The method comprises: In response to a vector instruction, storing a plurality of vector target register mapping information of the vector instruction in a circular cache list preset in a reorder cache; The circular cache list is used to assist the reordering cache, and the vector target register corresponding to the vector target register mapping information is released with the register identified by the register retirement item in the circular cache list as the granularity.

2. The RISC-V vector register release method according to claim 1, It is characterized in that The method further comprises: A circular cache entry identification field is set in the reorder cache entry, wherein the circular cache entry identification field is used to configure different values ​​according to the vector target register corresponding to the vector instruction.

3. The RISC-V vector register release method according to claim 1, It is characterized in that The method further comprises: In response to a vector instruction, scalar register mapping information of the vector instruction is stored in the architectural register and physical register fields in the re-order buffer.

4. The RISC-V vector register release method according to claim 1, It is characterized in that The method further comprises: The circular cache list allocates a register retirement entry for each vector target register corresponding to the vector instruction; The register retirement item includes a circular cache list index, a vector instruction index field corresponding to the reorder cache, a target architecture register field, a corresponding target physical register field, a vector instruction processing exception record identification field, and a register write microinstruction quantity field.

5. The RISC-V vector register release method according to claim 4, It is characterized in that Releasing the vector target register corresponding to the vector target register mapping information with the register identified by the register retirement item in the circular cache list as the granularity includes: Each clock cycle starts to release registers sequentially by presetting the item pointed to by the circular cache pointer head; Each clock cycle starts sequentially allocating the vector register map by presetting the entry pointed to by the tail of the circular cache pointer; The circular cache pointer head points to the longest valid item in the circular cache list, and the circular cache pointer tail points to the first invalid item in the circular cache list.

6. The RISC-V vector register release method according to claim 5, It is characterized in that The register write microinstruction quantity field is used to initialize and generate a corresponding value according to the number of vector microinstructions written into the vector target register corresponding to the register retirement item as needed; and to adjust the corresponding value according to the execution state of the vector microinstruction; The vector microinstruction is generated by decoding the vector instruction.

7. The RISC-V vector register release method according to claim 5, It is characterized in that The register write microinstruction quantity field is used to initialize and generate the corresponding field quantity or byte quantity according to the vector microinstruction quantity written into the vector target register corresponding to the register retirement item as needed; and to adjust the corresponding field quantity or byte quantity according to the execution state of the vector microinstruction; The vector microinstruction is generated by decoding the vector instruction.

8. The RISC-V vector register release method according to claim 6 or 7, It is characterized in that Each clock cycle starts by presetting the circular buffer pointer head to point to the entry and starts to release the registers in sequence, including: Starting from the item pointed to by the preset circular cache pointer head, identifying all consecutive register retirement items that are filled with the number field of the register write microinstructions in the register retirement items by microinstructions, and having no vector instruction processing exceptions; The corresponding register is released by identifying the obtained register retirement item, the register mapping corresponding to the register retirement item is stored in the architecture rename table, and the physical register in the replaced item in the architecture rename table is released to the free register table for subsequent calling.

9. A RISC-V vector register release device, It is characterized in that The device comprises: an allocation module and a release module; The allocation module is used for storing a plurality of vector target register mapping information of the vector instruction in a circular cache list preset in the reorder cache in response to the vector instruction; The release module is used to assist in reordering cache through the circular cache list, and release the vector target register corresponding to the vector target register mapping information at a granularity of registers identified by register retirement items in the circular cache list.

10. A central processing unit, comprising a central processing core based on a reorder cache of instructions, microinstructions and macroinstructions, It is characterized in that The central processing unit applies the RISC-V vector register release method described in any one of claims 1 to 8.

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