Communication method based on core particle architecture multi-DIE expansion

Abstract

The invention discloses a communication method based on core particle architecture multi-DIE expansion, a multi-DIE expansion communication structure is configured, the multi-DIE expansion communication structure comprises a master control MCU DIE and a plurality of controlled ASIC DIEs, handshake protocols of read-write operations comprise ST, SP, MODE, DEVADDR, REGADDR, WDATA, RDATA and paradigits, and a service transmission protocol comprises the steps of sending a transmission function enabling instruction, and returning the data to the master control MCU DIE after the data of the controlled ASIC DIEs are prepared. The method has the advantages that the expansion of a plurality of DIEs is facilitated, the flexibility is higher, a special service data transmission line is provided, and the bandwidth of a register read-write control line is not occupied.

Description

Technical Field

[0001] The present invention relates to a communication method, in particular to a communication method based on core-grain architecture multi-DIE expansion, belonging to the field of communication technology. Background Art

[0002] Chiplet architecture is a new packaging technology that packages small chips with different functions and different manufacturing processes together to form a heterogeneous chip. The chiplets are interconnected through the D2D (DIE to DIE) communication interface. Using chiplet packaging technology, the best process nodes can be used for modules with different functions to reduce power consumption and area costs; at the same time, the area of ​​a single chip is reduced, and the yield can also be improved, thereby reducing chip manufacturing costs and risks. The D2D communication interface interconnection technology is the key to chiplet. The cost of advanced processes is very high, especially analog circuits, I / O, etc. are becoming increasingly difficult to shrink with process technology, while the demand for control and data processing is increasing. However, there is no unified interconnection standard for chiplet interconnection transmission, which is usually divided into serial interconnection technology and parallel interconnection technology. Serial interconnection technology, also known as SerDes, has fast speed, long transmission distance and small number of IOs, but the transceiver circuit technology is more complex, has high energy consumption, and large area. It is usually end-to-end connection, which is not conducive to the realization of one master and multiple slaves interconnection mode; parallel interconnection technology uses high interface interconnection density. When multiple DIEs are interconnected, the number of pads used increases greatly, and the area cost increases greatly. At the same time, the parallel interface has extremely high delay requirements between each bit of bus data.

[0003] For analog circuits including analog-to-digital conversion modules, both digital control and real-time data transmission are required. The main problems are as follows: 1. Simple, flexible and extensible protocols: For multiple analog DIEs interconnected with a master MCU DIE, it is required not to occupy a large amount of interconnection space. Once the traditional parallel interface is expanded, it will occupy a large amount of interconnection resources; and Serdes is highly complex and more suitable for one-to-one interconnection, which is not easy to expand. 2. Efficient data transmission and high reliability: For multi-chip interconnection, it is necessary to ensure that the digital controller configures each analog chip, and that the data collected by each analog chip can be transmitted back to the digital master controller for processing in a timely manner, while also ensuring the high reliability of data transmission.

[0004] Therefore, it is necessary to design an interconnection communication method between multiple analog chips and the main digital control chip DIE to DIE. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a communication method for multi-DIE expansion based on a core-grain architecture, which is convenient for expansion of multiple DIEs.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: A communication method based on multi-DIE extension of core-grain architecture, comprising the following steps: Configure a multi-DIE extended communication structure, which includes a master MCU DIE and several controlled ASIC DIEs; The handshake protocol for the read and write operations between the master MCU DIE and several controlled ASIC DIEs includes the start bit ST and the end bit SP, as well as the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR, the data WDATA written by the master MCU DIE to the controlled ASIC DIE, the data RDATA read back by the master MCU DIE from the controlled ASIC DIE, and the parity bit parity; The service transmission protocol between the master MCU DIE and several controlled ASIC DIEs includes sending a transmission function enabling instruction, waiting for the controlled ASIC DIE data to be ready before returning to the master MCU DIE.

[0007] Furthermore, the communication between the master control MCU DIE and the plurality of controlled ASIC DIEs includes a clock signal CLK, a control instruction CMD, a return data signal RXn of the controlled ASIC DIE, and collected service data DATAn.

[0008] Furthermore, the CLK interface of the master MCU DIE is interconnected with the CLK interfaces of several controlled ASIC DIEs, the clock signal CLK is provided by any one of the master MCU DIE and several controlled ASIC DIEs, and all DIEs share one clock signal CLK.

[0009] Furthermore, the TX data transmitting end of the master control MCU DIE is connected to the RX data receiving ends of several controlled ASIC DIEs, and the control instruction CMD is sent by the TX data transmitting end of the master control MCU DIE and simultaneously sent to the RX data receiving ends of each controlled ASIC DIE.

[0010] Further, the TX data transmitting ends of the several controlled ASIC DIEs are connected to the RX data receiving end of the master MCU DIE, and the return data signal RXn of the controlled ASIC DIE sent from the TX data transmitting end of each controlled ASIC DIE is received by the RX data receiving end of the master MCU DIE, and the master MCU DIE selects through the data signal selector RX_mux, and the return data signal RXn of the controlled ASIC DIE selected by the control instruction CMD enters the master MCU DIE; the collection service data DATAn sent from the TX data transmitting end of each controlled ASIC DIE does not need to pass through the data signal selector RX_mux, and is directly transmitted to the master MCU DIE in real time.

[0011] Furthermore, the master MCU DIE writes the controlled ASIC DIE as follows: The master MCU DIE writes the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR, the data WDATA and the start bit ST written by the master MCU DIE to the corresponding position of the register of the master MCU DIE, writes 0 to the start bit ST to generate a start pulse, and the master MCU DIE starts to control the state machine to operate, and encodes the start bit ST, the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR, the data WDATA written by the master MCU DIE to the controlled ASIC DIE, the parity bit parity and the end bit SP in turn to generate a control instruction CMD, wherein the parity bit parity is calculated by the master MCU DIE, and the end bit SP is written 1, and then the control instruction CMD is converted from parallel to serial and sent to all the controlled ASIC DIEs through the TX data transmitting end of the master MCU DIE; When the master MCU DIE sends the control command CMD, the master MCU DIE writes 1 to the write status register WR_NOTICE. The master MCU DIE reads the data of the write status register WR_NOTICE and determines that the write operation is completed if it is 1. The RX data receiving end of all controlled ASIC DIEs decodes the received control instruction CMD, and parses out the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR and the data WDATA written by the master MCU DIE to the controlled ASIC DIE. All controlled ASIC DIEs match the parsed controlled ASIC DIE device address DEVADDR with their own device address. If the match is successful, the corresponding controlled ASIC DIE writes the data WDATA written by the master MCU DIE to the controlled ASIC DIE register. If the match is unsuccessful, the frame control instruction CMD is discarded.

[0012] Furthermore, the master control MCU DIE performs a read operation on the controlled ASIC DIE as follows: The master MCU DIE writes the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR and the start bit ST to the corresponding position of the master MCU DIE register. The start bit ST is written as 0 to generate a start pulse. The master MCU DIE starts to control the state machine to operate. The start bit ST, the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR, the parity bit parity and the end bit SP are encoded in turn to generate a control instruction CMD, wherein the parity bit parity is calculated by the master MCU DIE, and the end bit SP is written as 1. Then the control instruction CMD is converted from parallel to serial and sent to all controlled ASIC DIEs through the TX data transmitting end of the master MCU DIE. The RX data receiving end of all controlled ASIC DIEs decodes the received control instruction CMD, and parses out the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR and the parity bit parity. All controlled ASIC DIEs match the parsed controlled ASIC DIE device address DEVADDR with their own device address. If the match is unsuccessful, no operation is performed. If the match is successful, the corresponding controlled ASIC DIE parses the operation mode MODE and reads the data RDATA of the controlled ASIC DIE read back by the master MCU DIE from the register of the corresponding controlled ASIC DIE. The controlled ASIC DIE encodes the start bit ST, the response bit ACK, the data RDATA read back from the controlled ASIC DIE by the master control MCU DIE, the parity bit parity and the end bit SP to generate the return data signal RXn of the controlled ASIC DIE, wherein the parity bit parity is calculated by the controlled ASIC DIE, and the end bit SP is written as 1, and then the controlled ASIC DIE sends the return data signal RXn of the controlled ASIC DIE to the master control MCU DIE through the TX data transmitting end of the controlled ASIC DIE; The master control MCU DIE selects through the data signal selector RX_mux, and passes the return data signal RXn of the controlled ASIC DIE selected by the control instruction CMD into the master control MCU DIE. The master control MCU DIE parses the return data signal RXn of the controlled ASIC DIE returned by the controlled ASIC DIE, and the master control MCU DIE reads back the data RDATA and the parity bit parity of the controlled ASIC DIE, and then checks the parity bit parity. If the check is correct, the master control MCU DIE stores the data RDATA of the controlled ASIC DIE read back by the master control MCU DIE into the register, and writes 1 into the read status register RD_NOTICE at the same time. The master control MCU DIE reads the data of the read status register RD_NOTICE as 1, and determines that the read operation is completed.

[0013] Furthermore, the controlled ASIC DIE automatically sends back the service data operation as follows: The master MCU DIE writes the operation mode MODE, the controlled ASIC DIE device address DEVADDR and the start bit ST to the corresponding position of the register of the master MCU DIE. The start bit ST is written as 0 to generate a start pulse. The master MCU DIE starts to control the state machine to operate, and sequentially encodes the start bit ST, the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the parity bit parity and the end bit SP to generate a control instruction CMD, wherein the parity bit parity is calculated by the master MCU DIE, and the end bit SP is written as 1. Then the control instruction CMD is converted from parallel to serial and sent to all controlled ASIC DIEs through the TX data transmitting end of the master MCU DIE; The RX data receiving end of all controlled ASIC DIEs decodes the received control instruction CMD, and parses out the operation mode MODE, the controlled ASIC DIE device address DEVADDR, and the parity bit parity. All controlled ASIC DIEs match the parsed controlled ASIC DIE device address DEVADDR with their own device address. If the match is unsuccessful, no operation is performed. If the match is successful, the corresponding controlled ASIC DIE parses the operation mode MODE and automatically sends the collected service data DATAn. When the internal collected business data DATAn of the controlled ASIC DIE is ready, a valid signal is generated. When the controlled ASIC DIE detects the valid signal, the controlled ASIC DIE encodes the start bit ST, the acknowledgement bit ACK, the business data DATA, the parity bit parity and the end bit SP to generate the collected business data DATAn, and sends the collected business data DATAn back to the master MCU DIE and stores it in the register of the master MCU DIE.

[0014] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides a communication method based on the core grain architecture multi-DIE expansion. Compared with the traditional serial interconnection technology such as UART protocol and SerDes, the present invention is convenient for the expansion of multiple DIEs, has higher flexibility, and has a dedicated business data transmission route, and does not occupy the register read and write control route bandwidth; compared with the parallel interconnection technology, the present invention has less interface resource consumption and lower area cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of a multi-DIE extended communication structure of a communication method based on a core-grain architecture multi-DIE extension of the present invention.

[0016] Figure 2 It is a schematic diagram of the structure of MODE, REG_ADDR and DEVADDR in the DIE side register of the main control MCU of the present invention.

[0017] Figure 3 It is a schematic diagram of the WDATA structure in the DIE side register of the master control MCU of the present invention.

[0018] Figure 4 It is a schematic diagram of the RDATA structure in the DIE side register of the master control MCU of the present invention.

[0019] Figure 5 It is a schematic diagram of the structures of WR_NOTICE, RD_NOTICE and ST in the DIE side register of the master control MCU of the present invention.

[0020] Figure 6 It is a protocol timing diagram of the write operation of the present invention.

[0021] Figure 7 It is a protocol timing diagram of the read operation of the present invention.

[0022] Figure 8 It is a protocol timing diagram of the service data transmission of the present invention. DETAILED DESCRIPTION

[0023] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0024] A communication method based on multi-DIE expansion of a core-grain architecture of the present invention comprises the following steps: Configure multiple DIE extended communication structures, such as Figure 1 As shown, the multi-DIE extended communication structure includes a master MCU DIE and several controlled ASIC DIEs.

[0025] The communication between the master MCU DIE and several controlled ASIC DIEs includes clock signal CLK, control instruction CMD, return data signal RXn of the controlled ASIC DIE and collected business data DATAn.

[0026] The CLK interface of the master MCU DIE is interconnected with the CLK interfaces of several controlled ASIC DIEs. The clock signal CLK is provided by any one of the master MCU DIE and several controlled ASIC DIEs, and all DIEs share one clock signal CLK.

[0027] The TX data transmitting end of the master control MCU DIE is connected to the RX data receiving ends of several controlled ASIC DIEs, and the control instruction CMD is sent by the TX data transmitting end of the master control MCU DIE and is sent to the RX data receiving ends of each controlled ASIC DIE at the same time.

[0028] The TX data transmitting ends of several controlled ASIC DIEs are connected to the RX data receiving end of the master MCU DIE, and the return data signal RXn of the controlled ASIC DIE sent from the TX data transmitting end of each controlled ASIC DIE is received by the RX data receiving end of the master MCU DIE. The master MCU DIE selects through the data signal selector RX_mux, and the return data signal RXn of the controlled ASIC DIE selected by the control instruction CMD enters the master MCU DIE; the collected business data DATAn sent from the TX data transmitting end of each controlled ASIC DIE does not need to pass through the data signal selector RX_mux, and is directly transmitted to the master MCU DIE in real time.

[0029] The handshake protocol for read and write operations between the master MCU DIE and several controlled ASIC DIEs includes the start bit ST and the end bit SP, as well as the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR, the data WDATA written by the master MCU DIE to the controlled ASIC DIE, the data RDATA read back by the master MCU DIE from the controlled ASIC DIE, and the parity bit parity.

[0030] like Figure 2 As shown in the figure, the controlled ASIC DIE device address DEVADDR is 4 bits, so it can support up to 16 ASIC DIEs to be interconnected with the MCU DIE. The operation mode MODE is 4 bits, and the controlled ASIC DIE device address DEVADDR and the controlled ASIC DIE register address REG_ADDR are 12 bits in total. In actual projects, the number of bits of the controlled ASIC DIE device address DEVADDR and the number of bits of the controlled ASIC DIE register address REG_ADDR can be flexibly increased or decreased according to the number of controlled ASIC DIEs and the number of registers of the controlled ASIC DIE that need to be expanded in the end. For example, when there are only 4 controlled ASIC DIEs, the controlled ASIC DIE device address DEVADDR only needs 2 bits, and the controlled ASIC DIE register address REG_ADDR can be expanded to 10 bits; when there are 16 controlled ASIC DIEs, the controlled ASIC DIE device address DEVADDR needs 4 bits, and the controlled ASIC DIE register address REG_ADDR needs to be reduced to 8 bits. If the operation mode MODE is 4 bits, then theoretically up to 16 instruction modes can be supported, such as read instructions, write instructions, enable automatic business data transmission function, and control ASIC DIE to enter sleep mode.

[0031] The service transmission protocol between the master MCU DIE and several controlled ASIC DIEs includes sending a transmission function enabling instruction, waiting for the controlled ASIC DIE data to be ready before returning to the master MCU DIE.

[0032] The write operation of the master MCU DIE to the controlled ASIC DIE is: The master MCU DIE writes the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR, the data WDATA and the start bit ST written by the master MCU DIE to the corresponding position of the register of the master MCU DIE, writes 0 to the start bit ST to generate a start pulse, and the master MCU DIE starts to control the state machine to operate, and encodes the start bit ST, the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR, the data WDATA written by the master MCU DIE to the controlled ASIC DIE, the parity bit parity and the end bit SP in turn to generate the control instruction CMD, wherein the parity bit parity is calculated by the master MCU DIE, and the end bit SP is written 1, and then the control instruction CMD is converted from parallel to serial and sent to all the controlled ASIC DIEs through the TX data transmitting end of the master MCU DIE.

[0033] After the master control MCU DIE sends the control instruction CMD, the master control MCU DIE writes 1 in the write status register WR_NOTICE. When the master control MCU DIE reads the data of the write status register WR_NOTICE as 1, it determines that the write operation is completed.

[0034] The RX data receiving end of all controlled ASIC DIEs decodes the received control instruction CMD, and parses out the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR and the data WDATA written by the master MCU DIE to the controlled ASIC DIE. All controlled ASIC DIEs match the parsed controlled ASIC DIE device address DEVADDR with their own device address. If the match is successful, the corresponding controlled ASIC DIE writes the data WDATA written by the master MCU DIE to the controlled ASIC DIE register. If the match is unsuccessful, the frame control instruction CMD is discarded.

[0035] The master MCU DIE reads the controlled ASIC DIE as follows: The master MCU DIE writes the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR and the start bit ST to the corresponding position of the master MCU DIE register. The start bit ST is written to 0 to generate a start pulse. The master MCU DIE starts to control the state machine to operate, and encodes the start bit ST, the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR, the parity bit parity and the end bit SP in turn to generate a control instruction CMD, wherein the parity bit parity is calculated by the master MCU DIE, and the end bit SP is written to 1. Then the control instruction CMD is converted from parallel to serial and sent to all controlled ASIC DIEs through the TX data transmitting end of the master MCU DIE.

[0036] The RX data receiving end of all controlled ASIC DIEs decodes the received control instruction CMD, and parses out the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR and the parity bit parity. All controlled ASIC DIEs match the parsed controlled ASIC DIE device address DEVADDR with their own device address. If the match is unsuccessful, no operation is performed. If the match is successful, the corresponding controlled ASIC DIE parses the operation mode MODE and reads the data RDATA of the controlled ASIC DIE read back by the master MCU DIE from the register of the corresponding controlled ASIC DIE.

[0037] The controlled ASIC DIE encodes the start bit ST, the response bit ACK, the data RDATA read back from the controlled ASIC DIE by the master MCU DIE, the parity bit parity and the end bit SP to generate the return data signal RXn of the controlled ASIC DIE, wherein the parity bit parity is calculated by the controlled ASIC DIE, and the end bit SP is written as 1. Then the controlled ASIC DIE sends the return data signal RXn of the controlled ASIC DIE to the master MCU DIE through the TX data transmitting end of the controlled ASIC DIE.

[0038] The master control MCU DIE selects through the data signal selector RX_mux, and passes the return data signal RXn of the controlled ASIC DIE selected by the control instruction CMD into the master control MCU DIE. The master control MCU DIE parses the return data signal RXn of the controlled ASIC DIE returned by the controlled ASIC DIE, and the master control MCU DIE reads back the data RDATA and the parity bit parity of the controlled ASIC DIE, and then checks the parity bit parity. If the check is correct, the master control MCU DIE stores the data RDATA of the controlled ASIC DIE read back by the master control MCU DIE into the register, and writes 1 into the read status register RD_NOTICE at the same time. The master control MCU DIE reads the data of the read status register RD_NOTICE as 1, and determines that the read operation is completed.

[0039] The operation of automatically sending back business data by the accused ASIC DIE is: The master MCU DIE writes the operation mode MODE, the controlled ASIC DIE device address DEVADDR and the start bit ST to the corresponding position of the register of the master MCU DIE. The start bit ST is written to 0 to generate a start pulse. The master MCU DIE starts to control the state machine to operate, and encodes the start bit ST, the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the parity bit parity and the end bit SP in turn to generate the control instruction CMD, wherein the parity bit parity is calculated by the master MCU DIE, and the end bit SP is written to 1. Then the control instruction CMD is converted from parallel to serial and sent to all the controlled ASIC DIEs through the TX data transmitting end of the master MCU DIE.

[0040] The RX data receiving end of all controlled ASIC DIEs decodes the received control instruction CMD, and parses out the operation mode MODE, the controlled ASIC DIE device address DEVADDR, and the parity bit parity. All controlled ASIC DIEs match the parsed controlled ASIC DIE device address DEVADDR with their own device address. If the match is unsuccessful, no operation is performed. If the match is successful, the corresponding controlled ASIC DIE parses the operation mode MODE and automatically sends the collected business data DATAn.

[0041] When the internal collected business data DATAn of the controlled ASIC DIE is ready, a valid signal is generated. When the controlled ASIC DIE detects the valid signal, the controlled ASIC DIE encodes the start bit ST, the acknowledgement bit ACK, the business data DATA, the parity bit parity and the end bit SP to generate the collected business data DATAn, and sends the collected business data DATAn back to the master MCU DIE and stores it in the register of the master MCU DIE.

[0042] The present invention is further described below by means of specific examples.

[0043] Figure 2 They are the MCU side MODE register, REG_ADDR register, and DEVADDR register. For the sake of convenience, the corresponding register positions of the register storage operation mode MODE of the master MCU DIE, the controlled ASIC DIE register address REG_ADDR, and the controlled ASIC DIE device address DEVADDR are respectively referred to as the MODE register, REG_ADDR register, and DEVADDR register.

[0044] Figures 3 to 5 The MCU side write data register WDATA (16 bits), the register read back data RDATA register (16 bits) storing the ASIC DIE returned to the MCUDIE, and the write status register WR_NOTICE and read status register RD_NOTICE generated when the reading and writing are completed are described respectively. In the actual implementation process, two interrupts can also be added to indicate the completion of the read and write operations, so that the CPU can respond more promptly.

[0045] For example, it is agreed that the MODE register is binary 1010 represents the write operation mode, binary 0101 represents the read operation mode, and 1001 represents the business data transmission function is turned on; the device address of the controlled ASIC DIE0 is 0, the device address of the controlled ASIC DIE1 is 1, the device address of the controlled ASIC DIE2 is 2, and so on. The device address of the controlled ASIC DIEn is n (maximum 15).

[0046] When the master MCU DIE needs to write a 0xAA55 to the controlled ASIC DIE2 address 0x2c register, the steps are: the master MCU DIE writes binary 1010 to the MODE register through the APB bus, writes binary 0010 to the DEVADDR register, writes 0x2c to the REG_ADDR register, writes 0xAA55 to the WDATA register, and finally writes 0 to the ST register, which will generate a start pulse, and the control module of the master MCU DIE will start to control the state machine operation, such as Figure 6 As shown, the ST bit, MODE, DEVADDR, REG_ADDR, WDATA, the calculated check bit parity and stop bit 1 are encoded in turn, and then converted from parallel to serial and sent to all controlled ASIC DIEs through the TX data transmitter. After the transmission is completed, the control module will set the WR_NOTICE register to 1, and the master MCU DIE will know that the write operation has been completed by reading the write status register WR_NOTICE to 1. The RX data receiving end of all controlled ASIC DIEs decodes the received code stream and parses out MODE, DEVADDR, REG_ADDR, and WDATA. If the DEVADDR parsed by the controlled ASIC DIE other than the controlled ASIC DIE2 does not match its own device address, the frame of data is discarded and the register write operation is not performed; if the DEVADDR parsed by the controlled ASIC DIE2 is binary 0010 and successfully matches its own device address and the MODE is binary 1010, 0xAA55 is written to the corresponding 0x2c register address through the APB bus.

[0047] When the master MCU DIE needs to read the value of the register at address 0x28 of ASIC DIE3, the operation steps are: write binary 0101 to the MODE register through the APB bus, write binary 0011 to the DEVADDR register, write 0x28 to the REG_ADDR register, and finally write 0 to the ST register, which will generate a start pulse. The control module of the master MCU DIE will start to control the operation of the state machine, and encode the ST bit, MODE, DEVADDR, REG_ADDR, the calculated check bit parity and the stop bit SP (1) in turn, and then convert parallel to serial and send them to all controlled ASIC DIEs through the TX data transmitter. The RX data receiving end of all controlled ASIC DIEs decodes the received code stream and parses out MODE, DEVADDR, REG_ADDR, and parity. Only the device address of DEVADDR parsed by controlled ASIC DIE3 matches successfully, and the other controlled ASIC DIEs will not match successfully and will not operate. When the controlled ASIC DIE3 parses MODE as binary 0101, it reads the register value (assuming the value is 0x55AA) from the register at address 0x28 through the APB bus. Then the control and encoding module Encoder encodes the start bit ST (0), the response bit ACK (0), 0x55AA, the calculated parity, and the stop bit SP (1), and sends them back to the main control MCU DIE; Figure 7 As shown in the read operation protocol timing, the SP of the control instruction CMD and the returned start bit are separated by 7 CLKs. The RX data receiving end of the master MCU DIE will have a selector, which will only receive the data returned by the controlled ASIC DIE3; then the Decoder module and the control module of the master MCU DIE will parse out the 0x55AA returned by the controlled ASIC DIE and calculate the comparison check bit. If the check is correct, the returned 0x55AA will be stored in the RDATA register, and the control module will set the write status register RD_NOTICE to 1. The master MCU DIE will know that the read operation has been completed by reading the write status register RD_NOTICE to 1, and then read the RDATA register to know the return value of the register at address 0x28 on the controlled ASIC DIE3.

[0048] When the master MCU DIE needs the controlled ASIC DIE15 to automatically send back business data, the following steps are performed: First, the master MCU DIE broadcasts the automatic transmission of business data command to the controlled ASIC DIE through the control command CMD, such as Figure 8As shown, first write binary 1001 to the MODE register and write binary 1111 to the DEVADDR; finally write 0 to the ST register, and a start pulse will be generated to start encoding and parallel-to-serial conversion and send it out; when the other controlled ASIC DIEs do not match their own DEVADDR, they discard this frame data and do not take any action; only when the controlled ASIC DIE15 matches its own DEVADDR and the parsed MODE is binary 1001, the automatic sending of business data function is enabled; wait for the internal business data of the controlled ASIC DIE15 to be ready, when the business data is ready, a valid signal will be generated, when the control detects the valid signal, the control and the encoding module Encoder encode the start bit ST (0), the response bit ACK (0), DATA, the calculated check bit parity and the stop bit SP (1), and send them back to the main control MCU DIE and store them in the relevant registers.

[0049] The present invention provides a communication method based on multi-DIE expansion of a core-grain architecture. Compared with traditional serial interconnection technologies such as UART protocol and SerDes, the present invention facilitates the expansion of multiple DIEs, has higher flexibility, and has a dedicated business data transmission route, and does not occupy the bandwidth of the register read and write control route; compared with parallel interconnection technology, the present invention has less interface resource consumption and lower area cost.

[0050] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A communication method based on multi-DIE expansion of core-grain architecture, characterized in that The following steps are involved: Configure a multi-DIE extended communication structure, which includes a master MCU DIE and several controlled ASIC DIEs; The handshake protocol for the read and write operations between the master MCU DIE and several controlled ASIC DIEs includes the start bit ST and the end bit SP, as well as the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR, the data WDATA written by the master MCU DIE to the controlled ASIC DIE, the data RDATA read back by the master MCU DIE from the controlled ASIC DIE, and the parity bit parity; The service transmission protocol between the master MCU DIE and several controlled ASIC DIEs includes sending a transmission function enabling instruction, waiting for the controlled ASIC DIE data to be ready before returning to the master MCU DIE.

2. A communication method based on multi-DIE expansion of core-grain architecture according to claim 1, characterized in that: The communication between the master control MCU DIE and the controlled ASIC DIEs includes a clock signal CLK, a control instruction CMD, a return data signal RXn of the controlled ASIC DIEs, and collected service data DATAn.

3. A communication method based on multi-DIE expansion of core-grain architecture according to claim 2, characterized in that: The CLK interface of the master MCU DIE is interconnected with the CLK interfaces of several controlled ASIC DIEs. The clock signal CLK is provided by the master MCU DIE and any one of the several controlled ASIC DIEs, and all DIEs share one clock signal CLK.

4. A communication method based on multi-DIE expansion of core-grain architecture according to claim 2, characterized in that: The TX data transmitting end of the master control MCU DIE is connected to the RX data receiving ends of several controlled ASIC DIEs, and the control instruction CMD is sent by the TX data transmitting end of the master control MCU DIE and is sent to the RX data receiving ends of each controlled ASIC DIE at the same time.

5. A communication method based on multi-DIE expansion of core-grain architecture according to claim 2, characterized in that: The TX data transmitting ends of the several controlled ASIC DIEs are connected to the RX data receiving end of the master MCU DIE, and the return data signal RXn of the controlled ASIC DIE sent from the TX data transmitting end of each controlled ASIC DIE is received by the RX data receiving end of the master MCU DIE, and the master MCU DIE selects through the data signal selector RX_mux, and the return data signal RXn of the controlled ASIC DIE selected by the control instruction CMD enters the master MCU DIE; the collection service data DATAn sent from the TX data transmitting end of each controlled ASIC DIE does not need to pass through the data signal selector RX_mux, and is directly transmitted to the master MCU DIE in real time.

6. A communication method based on multi-DIE expansion of core-grain architecture according to claim 1, characterized in that: The master MCU DIE writes the controlled ASIC DIE as follows: The master MCU DIE writes the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR, the data WDATA and the start bit ST written by the master MCU DIE to the corresponding position of the register of the master MCU DIE, writes 0 to the start bit ST to generate a start pulse, and the master MCU DIE starts to control the state machine to operate, and encodes the start bit ST, the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR, the data WDATA written by the master MCU DIE to the controlled ASIC DIE, the parity bit parity and the end bit SP in turn to generate a control instruction CMD, wherein the parity bit parity is calculated by the master MCU DIE, and the end bit SP is written 1, and then the control instruction CMD is converted from parallel to serial and sent to all the controlled ASIC DIEs through the TX data transmitting end of the master MCU DIE; When the master MCU DIE sends the control command CMD, the master MCU DIE writes 1 to the write status register WR_NOTICE. The master MCU DIE reads the data of the write status register WR_NOTICE and determines that the write operation is completed if it is 1. The RX data receiving end of all controlled ASIC DIEs decodes the received control instruction CMD, and parses out the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR and the data WDATA written by the master MCUDIE to the controlled ASIC DIE. All controlled ASIC DIEs match the parsed controlled ASIC DIE device address DEVADDR with their own device address. If the match is successful, the corresponding controlled ASIC DIE writes the data WDATA written by the master MCU DIE to the controlled ASIC DIE register. If the match is unsuccessful, the frame control instruction CMD is discarded.

7. A communication method based on multi-DIE expansion of core-grain architecture according to claim 1, characterized in that: The master MCU DIE reads the controlled ASIC DIE as follows: The master MCU DIE writes the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR and the start bit ST to the corresponding position of the master MCU DIE register. The start bit ST is written as 0 to generate a start pulse. The master MCU DIE starts to control the state machine to operate. The start bit ST, the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR, the parity bit parity and the end bit SP are encoded in turn to generate a control instruction CMD, wherein the parity bit parity is calculated by the master MCU DIE, and the end bit SP is written as 1. Then the control instruction CMD is converted from parallel to serial and sent to all controlled ASIC DIEs through the TX data transmitting end of the master MCU DIE. The RX data receiving end of all controlled ASIC DIEs decodes the received control instruction CMD, and parses out the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the controlled ASIC DIE register address REG_ADDR and the parity bit parity. All controlled ASIC DIEs match the parsed controlled ASIC DIE device address DEVADDR with their own device address. If the match is unsuccessful, no operation is performed. If the match is successful, the corresponding controlled ASIC DIE parses the operation mode MODE and reads the data RDATA of the controlled ASIC DIE read back by the master MCU DIE from the register of the corresponding controlled ASIC DIE. The controlled ASIC DIE encodes the start bit ST, the response bit ACK, the data RDATA read back from the controlled ASIC DIE by the master MCU DIE, the parity bit parity and the end bit SP to generate the return data signal RXn of the controlled ASIC DIE, wherein the parity bit parity is calculated by the controlled ASIC DIE, and the end bit SP is written as 1, and then the controlled ASIC DIE sends the return data signal RXn of the controlled ASIC DIE to the master MCU DIE through the TX data transmitting end of the controlled ASIC DIE; The master control MCU DIE selects through the data signal selector RX_mux, and passes the return data signal RXn of the controlled ASIC DIE selected by the control instruction CMD into the master control MCU DIE. The master control MCU DIE parses the return data signal RXn of the controlled ASIC DIE returned by the controlled ASIC DIE, and the master control MCU DIE reads back the data RDATA and the parity bit parity of the controlled ASIC DIE, and then checks the parity bit parity. If the check is correct, the master control MCU DIE stores the data RDATA of the controlled ASIC DIE read back by the master control MCU DIE into the register, and writes 1 to the read status register RD_NOTICE. The master control MCUDIE reads the data of the read status register RD_NOTICE as 1, and determines that the read operation is completed.

8. A communication method based on multi-DIE expansion of core-grain architecture according to claim 1, characterized in that: The controlled ASIC DIE automatically sends back the service data as follows: The master MCU DIE writes the operation mode MODE, the controlled ASIC DIE device address DEVADDR and the start bit ST to the corresponding position of the register of the master MCU DIE. The start bit ST is written as 0 to generate a start pulse. The master MCU DIE starts to control the state machine to operate, and sequentially encodes the start bit ST, the operation mode MODE, the controlled ASIC DIE device address DEVADDR, the parity bit parity and the end bit SP to generate a control instruction CMD, wherein the parity bit parity is calculated by the master MCU DIE, and the end bit SP is written as 1. Then the control instruction CMD is converted from parallel to serial and sent to all controlled ASIC DIEs through the TX data transmitting end of the master MCU DIE; The RX data receiving end of all controlled ASIC DIEs decodes the received control instruction CMD, and parses out the operation mode MODE, the controlled ASIC DIE device address DEVADDR, and the parity bit parity. All controlled ASIC DIEs match the parsed controlled ASIC DIE device address DEVADDR with their own device address. If the match is unsuccessful, no operation is performed. If the match is successful, the corresponding controlled ASIC DIE parses the operation mode MODE and automatically sends the collected service data DATAn. When the internal collected business data DATAn of the controlled ASIC DIE is ready, a valid signal is generated. When the controlled ASIC DIE detects the valid signal, the controlled ASIC DIE encodes the start bit ST, the acknowledgement bit ACK, the business data DATA, the parity bit parity and the end bit SP to generate the collected business data DATAn, and sends the collected business data DATAn back to the master MCU DIE and stores it in the register of the master MCU DIE.

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