Calibration method and device for stable parameters of memory, equipment and medium
By dynamically adjusting the stable parameters of the memory, the problem of unstable driving recorder chips in high and low temperature tests is solved, the compatibility and product competitiveness of DDR are improved, and the negotiation rights with DDR suppliers are enhanced.
Patent Information
- Application Number
- CN202411061541.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-05
- Publication Date
- 2024-12-17
AI Technical Summary
The existing driving recorder chips are unstable in high and low temperature tests, resulting in poor startup, which is mainly related to the stability of DDR. How to ensure the stability of chip tests is an urgent issue.
By obtaining the program to be tested, performing write or read operations, dynamically adjusting the stable parameters of the memory according to temperature and time, including burst length, CAS latency, etc., to avoid crashes caused by voltage changes and ensure that the memory operates stably under different temperature environments.
It improves the stability and compatibility of the chip, can be built-in low-cost DDR or compatible with more models of DDR, dispersing the risk of DDR model discontinuation, enhancing product competitiveness and improving negotiation rights with DDR suppliers.
Smart Images
Figure CN119152920A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip technology, and in particular to a method, device, equipment and medium for calibrating stable parameters of a memory. Background Art
[0002] The current driving recorder products are sold in areas covering both home and abroad. Due to the large temperature differences in different regions, some poor startup problems may occur. That is, when the chips in the driving recorder products are tested at high and low temperatures, the tests become unstable, resulting in poor startup. This is mainly related to the stability of the DDR inside the chip. Therefore, how to ensure the stability of chip testing is an issue that urgently needs to be addressed. Summary of the invention
[0003] In view of the above problems, embodiments of the present invention are proposed to provide a method, device, apparatus and medium for calibrating stable parameters of a memory that overcomes the above problems or at least partially solves the above problems.
[0004] In a first aspect, an embodiment of the present invention provides a method for calibrating stable parameters of a memory, which is applied to a memory, wherein the memory and a main control chip are packaged together, and the method includes:
[0005] Get the program to be tested;
[0006] Executing the program to be tested so that the main control chip performs a write operation or a read operation on the memory to be tested;
[0007] When the temperature of the memory under test is greater than a first preset value or the memory under test works for a preset time period, a stable parameter of the memory under test is obtained so that the memory under test works with the stable parameter.
[0008] Optionally, the stability parameters include at least one or more of burst length, CAS latency, CAS write latency, row enable cycle, access time after clock trigger, write / correction time, precharge effective time, first command delay time, row effective to row precharge time, refresh cycle, row refresh cycle time, and row unit to row unit delay time.
[0009] Optionally, the method further comprises:
[0010] According to a preset first delay time, increasing the power-on voltage of the memory from a first voltage value to a second voltage value;
[0011] According to the preset second delay time, the power-on voltage of the memory is increased from the second voltage value to a third voltage value, so as to avoid a freeze phenomenon when the voltage of the memory to be tested changes.
[0012] Optionally, the method further comprises:
[0013] When the temperature of the memory to be tested is greater than a preset temperature value, the stability parameters of the memory to be tested are adjusted according to the actually collected temperature at every preset time period.
[0014] Optionally, the method further comprises:
[0015] When the computer is powered on, the stability parameters of the memory to be tested are adjusted by a preset adjustment program until the stability parameters reach a stable state;
[0016] When the stable parameters of the memory to be tested reach a stable state, the main program is executed.
[0017] Optionally, the method further comprises:
[0018] An operation of writing different values to different addresses is added between the write operation and the read operation on the main control chip.
[0019] In a second aspect, an embodiment of the present invention provides a device for calibrating stable parameters of a memory, which is applied to the memory, wherein the memory and the main control chip are packaged together, and the device includes:
[0020] An acquisition module is used to acquire the program to be tested;
[0021] An execution module, used for executing the program to be tested, so that the main control chip performs a write operation or a read operation on the memory to be tested;
[0022] The calibration module is used to obtain stable parameters of the memory under test when the temperature of the memory under test is greater than a first preset value or the memory under test works for a preset time period, so that the memory under test works with the stable parameters.
[0023] Optionally, the stability parameters include at least one or more of burst length, CAS latency, CAS write latency, row enable cycle, access time after clock trigger, write / correction time, precharge effective time, first command delay time, row effective to row precharge time, refresh cycle, row refresh cycle time, and row unit to row unit delay time.
[0024] Optionally, the calibration module is used to:
[0025] According to a preset first delay time, increasing the power-on voltage of the memory from a first voltage value to a second voltage value;
[0026] According to the preset second delay time, the power-on voltage of the memory is increased from the second voltage value to a third voltage value, so as to avoid a freeze phenomenon when the voltage of the memory to be tested changes.
[0027] Optionally, the calibration module is used to:
[0028] When the temperature of the memory to be tested is greater than a preset temperature value, the stability parameters of the memory to be tested are adjusted according to the actually collected temperature at every preset time period.
[0029] Optionally, the calibration module is used to:
[0030] When the computer is powered on, the stability parameters of the memory to be tested are adjusted by a preset adjustment program until the stability parameters reach a stable state;
[0031] When the stable parameters of the memory to be tested reach a stable state, the main program is executed.
[0032] Optionally, the calibration module is used to:
[0033] An operation of writing different values to different addresses is added between the write operation and the read operation on the main control chip.
[0034] In a third aspect, an embodiment of the present invention provides a terminal device, including: at least one processor and a memory;
[0035] The memory stores a computer program; and at least one processor executes the computer program stored in the memory to implement the method for calibrating stable parameters of the memory provided in the first aspect.
[0036] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed, the method for calibrating the stability parameters of the memory provided in the first aspect is implemented.
[0037] The embodiments of the present invention include the following advantages:
[0038] The method, device, equipment and medium for calibrating the stable parameters of a memory provided in an embodiment of the present invention obtain a program to be tested; execute the program to be tested so that the main control chip performs a write operation or a read operation on the memory to be tested; and obtain the stable parameters of the memory to be tested when the temperature of the memory to be tested is greater than a first preset value or the memory to be tested works for a preset time period, so that the memory to be tested works with the stable parameters. In the embodiment of the present application, the chip can be built-in with a low-cost DDR or be compatible with more models of DDR, thereby improving the competitiveness of the chip itself. In addition, by improving the compatibility of DDR, the risk of discontinuation of DDR models can be dispersed, thereby improving product competitiveness, and the right to speak in negotiations with DDR suppliers can also be improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Figure 1 is a flow chart of steps of an embodiment of a method for calibrating stable parameters of a memory of the present invention;
[0040] Figure 2 It is a structural block diagram of an embodiment of a device for calibrating stable parameters of a memory of the present invention;
[0041] Figure 3 It is a structural schematic diagram of a terminal device of the present invention. DETAILED DESCRIPTION
[0042] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0043] An embodiment of the present invention provides a method for calibrating a stability parameter of a memory, which is used to perform stability testing on the memory. The execution subject of this embodiment is a calibration device for calibrating a stability parameter of a memory, which is arranged on a terminal device, wherein the terminal device at least includes a computer, a tablet terminal, etc.
[0044] In order to improve the price competitiveness of products, they must also be compatible with small brands of DDR, otherwise they will be eliminated by the market due to price issues; but the quality of DDR of different brands varies, and high and low temperature tests are prone to instability, resulting in multiple poor startup problems during production. Analysis shows that this is mainly related to the stability of DDR. If the original practice of fixed calibration of DDR at the factory is still followed, the existing problems cannot be completely solved. Therefore, in order to solve the stability of DDR, the software has been optimized in a targeted manner, with the aim of being compatible with different types of DDR, such as DDR that is greatly affected by ambient temperature factors; and in the testing process, customers with adverse phenomena are mainly concentrated in provinces and cities with low temperatures. For example, the low temperature of about -30 degrees is simulated to perform low temperature testing on the chip, and the lock is that the main control makes errors when reading and writing DDR at low temperatures. Stable memory is crucial to software operations. The general practice in the market is to configure fixed DDR parameters by default. According to the customer's actual application environment, in order to achieve a stable DDR state in both high and low temperature conditions, an algorithm for DDR parameter calibration has been added to the software to dynamically set the DDR parameters in different temperature ranges. At the same time, the software will also increase the load on the main control. For example, when conditions such as large-scale data movement operations are performed in the program at the same time, the DDR read and write tests are performed to simulate the full-load operation of the chip. After obtaining the minimum and maximum values of the DDR stable parameters, the middle value with margin on both sides is selected as the most stable parameter.
[0045] Reference Figure 1 , shows a flow chart of steps of an embodiment of a method for calibrating a stable parameter of a memory of the present invention, the method may specifically include the following steps:
[0046] S101, obtaining a program to be tested;
[0047] Specifically, the terminal device stores a program to be tested, which is used to test the stability of the DDR in the chip. This test program is stored in the external SPI FLASH. The terminal device is connected to the SPI memory through the control chip. After booting, the main control chip will load the SPI FLASH program into the IRAM inside the main control chip itself.
[0048] S102, executing the IRAM to-be-tested program to enable the main control chip to perform a write operation or a read operation on the to-be-tested memory;
[0049] The main control chip grabs the program of IRAM to run, and executes a large number of write operations or read operations on the memory to be tested through the main control chip, and this is done in a low-temperature environment to accelerate the preheating of the chip. In order to maintain the versatility of the program, the same process is used for non-low temperature. The terminal device sends the program to be tested to the main control chip, so that the main control chip executes a large number of write operations or read operations on the memory to be tested, which can be done in a low-temperature environment.
[0050] S103 . When the temperature of the memory under test is greater than a first preset value or the memory under test works for a preset time period or the preset working time period, obtain stable parameters of the memory under test so that the memory under test works with stable parameters.
[0051] Among them, the preset time period can be set as needed and is not specifically limited in the embodiments of the present application.
[0052] Specifically, the detection of storage cells is the real detection of DDR memory chips. The common error of memory chips is that when it is 0, it is biased to 1, and when it is 1, it is biased to 0. By modifying the parameters of DDR, and then using the test program to write / read all address intervals of DDR; if the write / read test fails, then adjust the value of DDR parameters, and re-test the write / read test, cycle in sequence..., and then get the final stable parameters as the most stable parameters of this chip DDR. Combined with the actual customer application scenarios and actual feedback problems, the process of calibrating DDR parameters has been optimized.
[0053] The coping mechanism for the scenario where the internal temperature of the IC may reach 90-100 degrees after long-term use when the device is turned on at low temperature (-20 degrees). Since the DDR is packaged together with the main control chip GP15E, the software method of GP15E is as follows:
[0054] In low temperature environment, GP15E master control uses its hardware DMA or CPU to perform a large number of write / read operations on DDR from the beginning, increasing the load, accelerating power consumption, and accelerating the temperature rise of the chip, so that it can get out of the low temperature working state as soon as possible.
[0055] The method for calibrating the stable parameters of a memory provided in an embodiment of the present invention obtains a program to be tested; executes the program to be tested so that a main control chip performs a write operation or a read operation on the memory to be tested; and obtains the stable parameters of the memory to be tested when the temperature of the memory to be tested is greater than a first preset value or the memory to be tested works for a preset time period, so that the memory to be tested works with the stable parameters. In the embodiment of the present application, the chip can be built with a low-cost DDR or be compatible with more models of DDR, thereby improving the competitiveness of the chip itself. Moreover, by improving the compatibility of DDR, the risk of discontinuation of DDR models can be dispersed, thereby improving product competitiveness, and also improving the right to speak in negotiations with DDR suppliers.
[0056] Another embodiment of the present invention further supplements the method for calibrating the stability parameters of the memory provided in the above embodiment.
[0057] Optionally, the stability parameters include at least one or more of burst length, CAS latency, CAS write latency, row enable cycle, access time after clock trigger, write / correction time, precharge effective time, first command delay time, row effective to row precharge time, refresh cycle, row refresh cycle time, and row unit to row unit delay time.
[0058] Specifically, BL: Burst refers to the way of continuous data transmission between adjacent storage cells in the same row. The number of storage cells (columns) involved in the continuous transmission is the burst length (Burst Length, BL for short). With burst transmission technology, as long as the starting column address and burst length are specified, the memory will automatically read / write the corresponding number of storage cells in sequence without the need for the controller to continuously provide column addresses. In this way, except for the transmission of the first data which requires several cycles (mainly the previous delay, generally tRCD+CL), each subsequent data can be obtained in just one cycle.
[0059] CL: After CAS is issued, it takes a certain amount of time for data to be output. The time from when CAS and read commands are issued to when the first data is output is defined as CL (CAS Latency). Since CL only occurs when reading, it is also called read latency (RL). DDR3 has an AL (Additive Latency), so RL = AL + CL.
[0060] CWL: Similar to reading data, after CAS is issued, a certain amount of time is still required before data is allowed to enter. The time from the issuance of CAS and write commands to the writing of the first beat of data is defined as CWL (CAS Write Latency).
[0061] tRCD: When sending column read and write commands, there must be an interval with the row valid command. This interval is defined as tRCD, that is, RAS to CAS Delay (RAS to CAS delay); it can also be understood as the row selection cycle, which is a delay based on the response time of the electronic components of the chip storage array (the process of changing from one state to another).
[0062] tAC: From the rising edge of the clock before data is output on the data I / O bus, the data has been transmitted to the S-AMP, that is, the data has been triggered at this time, and after a certain driving time, it is finally transmitted to the data I / O bus for output. This period of time is called tAC (Access Time from CLK, access time after clock triggering). Each data has tAC when it is read, including in continuous reading, but the tAC of the second data starts at the same time as the first data is transmitted.
[0063] tWR: Since the data signal is sent from the control end, the chip does not need to make any adjustments when inputting. It only needs to be directly transmitted to the data input register, and then the storage capacitor is charged by the write driver. Therefore, the data can be sent at the same time as CAS, which means that the write delay is 0. However, the data is not written to the storage capacitor immediately, because the selection transistor (just like when reading) and the charging of the capacitor must take some time, so the actual writing of the data requires a certain period of time. In order to ensure the reliable writing of data, sufficient writing / correction time (tWR, Write Recovery Time) will be reserved. This operation is also called write back (Write Back). tWR takes at least one clock cycle or a little more (the higher the clock frequency, the more cycles tWR takes).
[0064] tRP: After the precharge command is issued, it takes some time before the RAS row valid command is allowed to be sent to open a new working row. This interval is called tRP (RAS#Precharge time, precharge valid time).
[0065] tDQS: The time from when the write command is issued to when the first rising edge of DQS is written is called tDQSS. It has a range of 0.75 to 1.25tCK.
[0066] tCR: Command Rate "First Command Delay" refers to the time after chip selection to issue a specific addressed row activation command, in clock cycles. Chip selection refers to the selection of the physical bank of the row (through the CS chip select signal on the DIMM). If the system refers to using a single-sided memory, there is no chip selection problem because there is only one physical bank at this time.
[0067] tRA: RAS active time, also referred to as Active to Precharge Delay, the time from row effective to row precharge. It refers to the interval from receiving a request to initializing RAS (row address strobe pulse) to actually starting to receive data, tRAS = tRCD + tWR.
[0068] tREF: Refresh Period, which means "refresh period". It refers to the refresh period of the memory module.
[0069] tRFC: Row Refresh Cycle Time, which stands for "SDRAM row refresh cycle time", is the number of clock cycles required to refresh a row unit. This value also represents the time interval between sending two refresh commands (i.e., REF commands) to another row unit in the same bank. The smaller the tRFC value, the better, and it is slightly higher than the tRC value.
[0070] tRRD: Row to Row Delay, also known as RAS to RASDelay, means "row to row delay". This value also indicates the time interval between sending activation instructions (ie: REF instructions) twice to the same row unit in the same bank. The smaller the tRRD value, the better. The lower the delay, the faster the next bank can be activated for read and write operations. However, since a certain amount of data is required, too short a delay will cause continuous data expansion.
[0071] tRTP: Read to precharge delay, similar to tWR, defines the interval time from the issuance of a read command to tRP of the memory on the same rank, but it will not take effect until the read is completed and the row address is closed.
[0072] tWTR: Write to Read Delay, which means "read to write delay". Samsung calls it "TCDLR (last data into read command)", which means the last data into the read command. It sets the clock cycle that must be waited between the last valid write operation and the next read operation to the same unit in the DDR memory module. Increasing the tWTR value allows the memory module to run at a faster speed than its default speed.
[0073] tRC: Row Cycle Time, which stands for "SDRAM row cycle time", is the minimum number of clock cycles required for the entire process including row cell precharge to activation. tRC = tRAS + tRP. If the tRC time is too long, the performance will be reduced due to unnecessary delays in activating the new address after completing the entire clock cycle. However, if the value is set too small, a new cycle can be initialized before the activated row cell is fully charged, which will also cause data loss and corruption.
[0074] Optionally, the method further comprises:
[0075] According to a preset first delay time, increasing the power-on voltage of the memory from a first voltage value to a second voltage value;
[0076] According to the preset second delay time, the power-on voltage of the memory is increased from the second voltage value to the third voltage value, so as to avoid the phenomenon of freezing when the voltage of the memory to be tested changes.
[0077] Specifically, the chip's internal startup program sets a lower 2.1V DDR voltage by default when DDR is powered on, which is compatible with DDR1 and DDR2. After power-on, it will increase the DDR voltage to 2.3V after a delay of about 100ms based on the test results, and then increase the DDR voltage to 2.5V in the main program after a delay of about 100ms. The gradual voltage adjustment method solves the problem of the DDR voltage jumping directly from 2.1v to 2.5v at the mass production end, causing a freeze.
[0078] Optionally, the method further comprises:
[0079] When the temperature of the memory to be tested is greater than a preset temperature value, the stability parameters of the memory to be tested are adjusted according to the actually collected temperature at every preset time period.
[0080] Specifically, since the actual burn-in test found that the machine would freeze at high temperatures, if the power is turned on and the chip works for about 1 minute, the temperature of the chip will basically stop rising. At this time, the DDR parameters will be recalibrated at a fixed interval (60s) to cope with the temperature change.
[0081] Optionally, the method further comprises:
[0082] When the device is powered on, the stability parameters of the memory to be tested are adjusted through a preset adjustment program until the stability parameters reach a stable state;
[0083] When the stable parameters of the memory to be tested reach a stable state, the main program is executed.
[0084] For products that need to start up quickly, BootLoader (a small program that runs before the operating system kernel runs) is used. The program uses a mechanism to continuously calibrate DDR until it is calibrated to the correct parameters. This allows the machine that is started at room temperature to quickly complete the DDR code loading, and it can continue to wait until the DDR reaches stability at high and low temperatures. It will not run to the main program until the DDR parameters are calibrated to the correct ones.
[0085] Optionally, the method further comprises:
[0086] An operation of writing different values to different addresses is added between the write operation and the read operation on the main control chip.
[0087] If the test software writes and then reads a value very quickly, the write operation will charge the capacitor on the data line, and the bus will briefly hold its state. When the test software reads, the bus will return the value just written, even if the data line is actually open. The algorithm to detect this error is to insert another write operation to a different address between the write and read back. For example, writing X to the X1 position, Y to the Y1 position, and then reading the value X from the X1 position indicates that the error does not exist.
[0088] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.
[0089] The method for calibrating the stable parameters of a memory provided in an embodiment of the present invention obtains a program to be tested; executes the program to be tested so that a main control chip performs a write operation or a read operation on the memory to be tested; and obtains the stable parameters of the memory to be tested when the temperature of the memory to be tested is greater than a first preset value or the memory to be tested works for a preset time period, so that the memory to be tested works with the stable parameters. In the embodiment of the present application, the chip can be built with a low-cost DDR or be compatible with more models of DDR, thereby improving the competitiveness of the chip itself. Moreover, by improving the compatibility of DDR, the risk of discontinuation of DDR models can be dispersed, thereby improving product competitiveness, and also improving the right to speak in negotiations with DDR suppliers.
[0090] Another embodiment of the present invention provides a device for calibrating stable parameters of a memory, which is used to execute the method for calibrating stable parameters of the memory provided in the above embodiment.
[0091] Reference Figure 2 , shows a structural block diagram of an embodiment of a device for calibrating stable parameters of a memory of the present invention, which is applied to a memory, and the memory and the main control chip are packaged together. The device may specifically include the following modules: an acquisition module 201, an execution module 202 and a calibration module 203, wherein:
[0092] The acquisition module 201 is used to acquire the program to be tested;
[0093] The execution module 202 is used to execute the program to be tested, so that the main control chip performs a write operation or a read operation on the memory to be tested;
[0094] The calibration module 203 is used to obtain stable parameters of the memory under test when the temperature of the memory under test is greater than a first preset value or the memory under test works for a preset time period, so that the memory under test works with stable parameters.
[0095] The device for calibrating the stable parameters of a memory provided in an embodiment of the present invention obtains a program to be tested; executes the program to be tested so that a main control chip performs a write operation or a read operation on the memory to be tested; and obtains the stable parameters of the memory to be tested when the temperature of the memory to be tested is greater than a first preset value or the memory to be tested works for a preset time period, so that the memory to be tested works with the stable parameters. In the embodiment of the present application, the chip can be built with a low-cost DDR or be compatible with more models of DDR, thereby improving the competitiveness of the chip itself. Moreover, by improving the compatibility of DDR, the risk of discontinuation of DDR models can be dispersed, thereby improving product competitiveness, and also improving the right to speak in negotiations with DDR suppliers.
[0096] Another embodiment of the present invention further supplements the device for calibrating the stable parameters of the memory provided in the above embodiment.
[0097] Optionally, the stability parameters include at least one or more of burst length, CAS latency, CAS write latency, row enable cycle, access time after clock trigger, write / correction time, precharge effective time, first command delay time, row effective to row precharge time, refresh cycle, row refresh cycle time, and row unit to row unit delay time.
[0098] Optionally, a calibration module is used to:
[0099] According to a preset first delay time, increasing the power-on voltage of the memory from a first voltage value to a second voltage value;
[0100] According to the preset second delay time, the power-on voltage of the memory is increased from the second voltage value to the third voltage value, so as to avoid the phenomenon of freezing when the voltage of the memory to be tested changes.
[0101] Optionally, a calibration module is used to:
[0102] When the temperature of the memory to be tested is greater than a preset temperature value, the stability parameters of the memory to be tested are adjusted according to the actually collected temperature at every preset time period.
[0103] Optionally, a calibration module is used to:
[0104] When the device is powered on, the stability parameters of the memory to be tested are adjusted through a preset adjustment program until the stability parameters reach a stable state;
[0105] When the stable parameters of the memory to be tested reach a stable state, the main program is executed.
[0106] Optionally, a calibration module is used to:
[0107] An operation of writing different values to different addresses is added between the write operation and the read operation on the main control chip.
[0108] It should be noted that each implementable method in this embodiment may be implemented separately, or may be implemented in combination in any combination without conflict, and this application is not limited thereto.
[0109] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
[0110] The device for calibrating the stable parameters of a memory provided in an embodiment of the present invention obtains a program to be tested; executes the program to be tested so that a main control chip performs a write operation or a read operation on the memory to be tested; and obtains the stable parameters of the memory to be tested when the temperature of the memory to be tested is greater than a first preset value or the memory to be tested works for a preset time period, so that the memory to be tested works with the stable parameters. In the embodiment of the present application, the chip can be built with a low-cost DDR or be compatible with more models of DDR, thereby improving the competitiveness of the chip itself. Moreover, by improving the compatibility of DDR, the risk of discontinuation of DDR models can be dispersed, thereby improving product competitiveness, and also improving the right to speak in negotiations with DDR suppliers.
[0111] Still another embodiment of the present invention provides a terminal device, which is used to execute the method for calibrating the stable parameters of the memory provided in the above embodiment.
[0112] Figure 3 is a schematic diagram of the structure of a terminal device of the present invention, such as Figure 3 As shown, the terminal device includes: at least one processor 301 and a memory 302;
[0113] The memory stores a computer program; and at least one processor executes the computer program stored in the memory to implement the method for calibrating the stable parameters of the memory provided in the above embodiment.
[0114] The terminal device provided in this embodiment obtains the program to be tested; executes the program to be tested so that the main control chip performs a write operation or a read operation on the memory to be tested; and obtains stable parameters of the memory to be tested when the temperature of the memory to be tested is greater than a first preset value or the memory to be tested works for a preset time period, so that the memory to be tested works with stable parameters. In the embodiment of the present application, the chip can be built-in with low-cost DDR or be compatible with more models of DDR, thereby improving the competitiveness of the chip itself. In addition, by improving the compatibility of DDR, the risk of discontinuation of DDR models can be dispersed, thereby improving product competitiveness, and the right to speak in negotiations with DDR suppliers can also be improved.
[0115] Yet another embodiment of the present application provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed, the method for calibrating the stable parameters of the memory provided in any of the above embodiments is implemented.
[0116] According to the computer-readable storage medium of the present embodiment, by acquiring the program to be tested and executing the program to be tested, the main control chip performs a write operation or a read operation on the memory to be tested; when the temperature of the memory to be tested is greater than a first preset value or the memory to be tested works for a preset time period, the stable parameters of the memory to be tested are obtained, so that the memory to be tested works with stable parameters. In the embodiment of the present application, the chip can be built-in with a low-cost DDR or be compatible with more models of DDR, thereby improving the competitiveness of the chip itself. Moreover, by improving the compatibility of DDR, the risk of discontinuation of DDR models can be dispersed, thereby improving product competitiveness, and the right to speak in negotiations with DDR suppliers can also be improved.
[0117] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.
[0118] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
[0119] The embodiments of the present invention are described with reference to flowcharts and / or block diagrams of methods, electronic devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing electronic device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing electronic device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0120] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing electronic device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0121] These computer program instructions can also be loaded onto a computer or other programmable data processing electronic device so that a series of operating steps are executed on the computer or other programmable electronic device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable electronic device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0122] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.
[0123] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or electronic device that includes a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also includes elements that are inherent to such process, method, article or electronic device. In the absence of further restrictions, the elements defined by the sentence "comprises a..." do not exclude the presence of other identical elements in the process, method, article or electronic device that includes the elements.
[0124] The above is a detailed introduction to a method for calibrating the stable parameters of a memory and a device for calibrating the stable parameters of a memory provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.
Claims
1. A method for calibrating a stable parameter of a memory, characterized in that: Applied to a memory, the memory and the main control chip are packaged together, and the method includes: Get the program to be tested; Executing the program to be tested so that the main control chip performs a write operation or a read operation on the memory to be tested; When the temperature of the memory under test is greater than a first preset value or the memory under test works for a preset time period, a stable parameter of the memory under test is obtained so that the memory under test works with the stable parameter.
2. The method according to claim 1, characterized in that The stability parameters include at least one or more of burst length, CAS latency, CAS write latency, row enable cycle, access time after clock triggering, write / correction time, precharge effective time, first command delay time, row effective to row precharge time, refresh cycle, row refresh cycle time, and row unit to row unit delay time.
3. The method according to claim 1, characterized in that The method further comprises: According to a preset first delay time, increasing the power-on voltage of the memory from a first voltage value to a second voltage value; According to the preset second delay time, the power-on voltage of the memory is increased from the second voltage value to a third voltage value, so as to avoid a freeze phenomenon when the voltage of the memory to be tested changes.
4. The method according to claim 1, characterized in that: The method further comprises: When the temperature of the memory to be tested is greater than a preset temperature value, the stability parameters of the memory to be tested are adjusted according to the actually collected temperature at every preset time period.
5. The method according to claim 1, characterized in that The method further comprises: When the computer is powered on, the stability parameters of the memory to be tested are adjusted by a preset adjustment program until the stability parameters reach a stable state; When the stable parameters of the memory to be tested reach a stable state, the main program is executed.
6. The method according to claim 1, characterized in that The method further comprises: An operation of writing different values to different addresses is added between the write operation and the read operation on the main control chip.
7. A device for calibrating the stability parameters of a memory, characterized in that: The device comprises: An acquisition module is used to acquire the program to be tested; An execution module, used for executing the program to be tested, so that the main control chip performs a write operation or a read operation on the memory to be tested; The calibration module is used to obtain stable parameters of the memory under test when the temperature of the memory under test is greater than a first preset value or the memory under test works for a preset time period, so that the memory under test works with the stable parameters.
8. The device according to claim 7, characterized in that The stability parameters include at least one or more of burst length, CAS latency, CAS write latency, row enable cycle, access time after clock triggering, write / correction time, precharge effective time, first command delay time, row effective to row precharge time, refresh cycle, row refresh cycle time, and row unit to row unit delay time.
9. A terminal device, characterized in that: include: at least one processor and memory; The memory stores a computer program; The at least one processor executes the computer program stored in the memory to implement the method for calibrating the stable parameters of the memory according to any one of claims 1 to 6.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed, the method for calibrating the stability parameters of the memory according to any one of claims 1 to 6 is implemented.