Semiconductor power device with multilayer field plate and manufacturing method thereof

Abstract

The invention provides a semiconductor power device with multiple layers of field plates and a manufacturing method of the semiconductor power device. The manufacturing method comprises the following steps: providing a gallium nitride substrate, and depositing a first dielectric layer; manufacturing an ohmic contact hole; manufacturing an ohmic electrode; depositing a second dielectric layer; manufacturing a first-stage field plate; depositing a lower dielectric layer and an upper dielectric layer in sequence; manufacturing an upper-level field plate region and a lower-level field plate region; and manufacturing a lower-level field plate and an upper-level field plate. Under the same etching condition, the etching speed of the lower dielectric layer is smaller than that of the upper dielectric layer, and only a small part of the lower dielectric layer is etched off after the upper dielectric layer outside the upper field plate area is completely etched off, so that an etching stop layer does not need to be arranged between the two dielectric layers, the manufacturing process is reduced, and the preparation time is saved; and meanwhile, a gap can be prevented from being generated between the two dielectric layers, and the shape forming effect of the field plate at the position is relatively good, so that the local concentration effect of an electric field caused by etching damage is reduced, and the reliability of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a semiconductor power device with a multi-layer field plate and a manufacturing method thereof. Background Art

[0002] Gallium nitride (GaN) high electron mobility transistors (HEMTs) offer superior performance and broad application prospects in high-frequency and high-power applications. GaN HEMTs are primarily categorized as depletion-mode (D-mode) and enhancement-mode (E-mode). Depletion-mode HEMTs have a simpler structure, maximizing the high electron concentration and mobility of the GaN heterojunction. They also offer a highly reliable gate.

[0003] In GaN HEMT devices, the introduction of field plates can suppress surface electric field concentration and mitigate electric field spikes. For high-voltage devices, multiple layers of field plates are typically required, and the length and height of each layer are adjusted to achieve the desired electric field distribution. However, this technology has the disadvantage that the electric field intensity is higher at the edges of the field plates, making breakdown more likely to occur prematurely at lower potentials, and potentially at the surface, placing higher demands on the quality of the dielectric layer.

[0004] Existing devices use a contact field plate structure with an etch barrier layer between the dielectric layers. The existing field plate process requires dry etching of the dielectric layer followed by wet etching of the etch barrier layer. Multiple etching steps can easily damage the contact area between the field plate metal, etch barrier layer, and dielectric layer, leading to uneven local electric field distribution and impacting device reliability. Summary of the Invention

[0005] The present invention provides a semiconductor power device with a multi-layer field plate and a manufacturing method thereof, which can improve the reliability of the device.

[0006] In a first aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor power device having a multi-layer field plate, comprising the following steps: a. providing a gallium nitride substrate, and depositing a first dielectric layer on the gallium nitride substrate; b. Etching the first dielectric layer and the gallium nitride substrate in the source region and the drain region to form ohmic contact holes; c. depositing an ohmic metal layer in the ohmic contact hole and on the first dielectric layer, and etching the ohmic metal layer to form an ohmic electrode; d. depositing a second dielectric layer on the first dielectric layer and the ohmic electrode; e. Fabricating a primary field plate on the second dielectric layer; f. sequentially depositing a lower dielectric layer and an upper dielectric layer on the second dielectric layer and the primary field plate, wherein under the same etching conditions, the etching rate of the lower dielectric layer is lower than the etching rate of the upper dielectric layer; g. Etching the upper dielectric layer except the upper field plate region to form the upper field plate region on the upper dielectric layer and forming the lower field plate region on the lower dielectric layer; h. performing an etching operation on the gate region to form a gate contact hole; i. Forming a gate metal in the gate contact hole, forming a lower-level field plate on the lower-level field plate region, and forming an upper-level field plate on the upper-level field plate region.

[0007] Before the step of etching the gate region to form the gate contact hole, a protective dielectric layer is formed on the upper dielectric layer and the lower dielectric layer.

[0008] Wherein, the etching rate ratio of the upper dielectric layer and the lower dielectric layer under the same etching conditions is greater than 10:1.

[0009] The lower field plate is connected to the gate metal, or the lower field plate is separated from the gate metal.

[0010] In a second aspect, an embodiment of the present invention provides another method for manufacturing a semiconductor power device having a multi-layer field plate, comprising the following steps: a. providing a gallium nitride substrate, and depositing a first dielectric layer on the gallium nitride substrate; b. Etching the first dielectric layer and the gallium nitride substrate in the source region and the drain region to form ohmic contact holes; c. depositing an ohmic metal layer in the ohmic contact hole and on the first dielectric layer, and etching the ohmic metal layer to form an ohmic electrode; d. depositing a second dielectric layer on the first dielectric layer and the ohmic electrode; e. Fabricating a primary field plate on the second dielectric layer; f. depositing a third dielectric layer on the second dielectric layer and the primary field plate; g. Etching the gate region to form a gate contact hole; h. forming a gate metal in the gate contact hole and fabricating a secondary field plate on the third dielectric layer; i. depositing a lower dielectric layer and an upper dielectric layer in sequence on the gate metal, the secondary field plate and the third dielectric layer, wherein under the same etching conditions, the etching rate of the lower dielectric layer is lower than the etching rate of the upper dielectric layer; j. Etching the upper dielectric layer except the upper field plate region to form the upper field plate region on the upper dielectric layer and the lower field plate region on the lower dielectric layer; k. Forming a lower field plate on the lower field plate region, and forming an upper field plate on the upper field plate region.

[0011] Before the steps of forming the lower field plate on the lower field plate region and forming the lower field plate on the lower field plate region, a protective dielectric layer is formed on the upper dielectric layer and the lower dielectric layer.

[0012] Wherein, the etching rate ratio of the upper dielectric layer and the lower dielectric layer under the same etching conditions is greater than 10:1.

[0013] The secondary field plate is connected to the gate metal, or the secondary field plate is separated from the gate metal.

[0014] In a third aspect, an embodiment of the present invention provides another method for manufacturing a semiconductor power device having a multi-layer field plate, comprising the following steps: a. providing a gallium nitride substrate, and depositing a first dielectric layer on the gallium nitride substrate; b. Etching the first dielectric layer and the gallium nitride substrate in the source region and the drain region to form ohmic contact holes; c. depositing an ohmic metal layer in the ohmic contact hole and on the first dielectric layer, and etching the ohmic metal layer to form an ohmic electrode; d. depositing a second dielectric layer on the first dielectric layer and the ohmic electrode; e. Fabricating a primary field plate on the second dielectric layer; f. depositing a third dielectric layer on the primary field plate and the second dielectric layer; g. Fabricating a secondary field plate on the third dielectric layer; h. depositing a lower dielectric layer and an upper dielectric layer in sequence on the third dielectric layer and the secondary field plate; wherein under the same etching conditions, the etching rate of the lower dielectric layer is lower than the etching rate of the upper dielectric layer; i. performing an etching operation on the upper dielectric layer except the upper field plate region to form the upper field plate region on the upper dielectric layer and the lower field plate region on the lower dielectric layer; j. performing an etching operation in the gate region to form a gate contact hole; k. Forming a gate metal in the gate contact hole, forming a lower-level field plate on the lower-level field plate region, and forming an upper-level field plate on the upper-level field plate region.

[0015] In a fourth aspect, the present invention further provides a semiconductor power device with a multi-layer field plate, which is manufactured by the aforementioned method for manufacturing a semiconductor power device with a multi-layer field plate.

[0016] The semiconductor power device with a multi-layer field plate provided by the present invention and the manufacturing method thereof, under the same etching conditions, the etching rate of the lower dielectric layer is lower than the etching rate of the upper dielectric layer. After the upper dielectric layer outside the upper field plate area is completely etched away, only a small portion of the lower dielectric layer is etched away, thereby eliminating the need to provide an etching stop layer between the two dielectric layers, reducing the manufacturing process and saving preparation time; at the same time, the generation of a gap between the two dielectric layers can be avoided, and the shape forming effect of the field plate at this position is better, thereby reducing the local concentration effect of the electric field caused by etching damage and improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a flow chart of a method for manufacturing a semiconductor power device with a multi-layer field plate provided in Example 1 of the present invention.

[0018] Figure 2A-2G A schematic diagram of the manufacturing process of a semiconductor power device with a multi-layer field plate provided in Example 1 of the present invention.

[0019] Figure 3 This is a schematic structural diagram of a semiconductor power device with a multi-layer field plate provided in Example 2 of the present invention.

[0020] Figure 4 This is a schematic structural diagram of a semiconductor power device with a multi-layer field plate provided in Example 3 of the present invention.

[0021] Figure 5 This is a schematic structural diagram of a semiconductor power device with a multi-layer field plate provided in Example 4 of the present invention.

[0022] Figure 6 This is a schematic structural diagram of a semiconductor power device with a multi-layer field plate provided in Example 5 of the present invention.

[0023] Figure 7 This is a schematic structural diagram of a semiconductor power device with a multi-layer field plate provided in Example 6 of the present invention.

[0024] Figure 8 This is a schematic structural diagram of a semiconductor power device with a multi-layer field plate provided in Example 7 of the present invention. DETAILED DESCRIPTION

[0025] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0026] In the figures, structurally similar elements are denoted by the same reference numerals.

[0027] Example 1 The semiconductor power device with a multi-layer field plate prepared in this embodiment is a D-type gallium nitride high electron mobility transistor, which can be used as a high-power application device such as a switching device or an amplifier device.

[0028] Specifically, if Figure 1 As shown, the method for manufacturing a semiconductor power device with a multi-layer field plate in this embodiment includes the following steps.

[0029] Step S110 : providing a gallium nitride substrate 1 , and depositing a first dielectric layer 31 on the gallium nitride substrate 1 .

[0030] In the present invention, the semiconductor power device is a gallium nitride device, so a gallium nitride substrate is used. Figure 2A As shown, the gallium nitride substrate 1 includes a silicon substrate 11 , a gallium nitride (GaN) layer 12 , an aluminum gallium nitride (ALGaN) layer 13 , and a silicon nitride (SiN) layer 14 , which are sequentially arranged.

[0031] The first dielectric layer 31 is deposited on a side of the gallium nitride substrate 1 away from the silicon substrate 11 .

[0032] In step S120, the first dielectric layer 31 and the gallium nitride substrate 1 in the source and drain regions are etched to form ohmic contact holes 20. This step allows ohmic contact holes 20 to be formed simultaneously in the source and drain regions. There are at least two ohmic contact holes, one in the source region and one in the drain region.

[0033] The ohmic contact hole 20 penetrates the first dielectric layer 31 and the silicon nitride layer 14 , and reaches a depth of the aluminum gallium nitride layer 13 , so that the fabricated ohmic electrode 2 can contact the aluminum gallium nitride layer 13 .

[0034] In step S130, an ohmic metal layer is deposited in the ohmic contact hole 20 and on the first dielectric layer 31, and the ohmic metal layer is etched to form an ohmic electrode 2. This step specifically includes the following sub-steps.

[0035] Step S131: Deposit an ohmic metal layer. The ohmic metal layer covers the first dielectric layer 31 and fills the ohmic contact hole 20. The ohmic metal layer is preferably a stack of titanium and aluminum. Titanium has strong adhesion to the gallium nitride substrate, ensuring the mechanical stability of the ohmic metal contact; aluminum naturally forms an ohmic contact with the gallium nitride substrate. Of course, in other embodiments, the ohmic metal layer can also be a multilayer structure formed by various combinations of metals, such as titanium, aluminum, nickel, and gold.

[0036] Step S132: Anneal the ohmic metal layer. Preferably, the ohmic metal layer can be annealed. An RTP (Rapid Thermal Processing) annealing process can be used to repair lattice defects, eliminate stress, and optimize the material's conductivity. Annealing the ohmic metal layer before etching reduces deformation caused by grain growth and rearrangement during the annealing process, reduces stress, and maintains the overall shape of the ohmic metal layer, effectively addressing the issue of deteriorating ohmic contact resistance.

[0037] In step S133 , preferably, a titanium nitride metal layer (not shown in the figure) may be deposited on the ohmic metal layer. The titanium nitride metal layer covers the ohmic metal layer.

[0038] In step S134 , the titanium nitride metal layer and the ohmic metal layer are etched to form an ohmic electrode.

[0039] In this embodiment, a diffusion barrier layer can be deposited on the first dielectric layer before depositing the ohmic metal layer. The diffusion barrier layer is aluminum nitride or aluminum oxide deposited by atomic vapor deposition or physical vapor deposition, or highly dense silicon oxide, silicon nitride, or silicon oxynitride deposited by chemical vapor deposition. In this embodiment, the diffusion barrier layer is an aluminum nitride layer. This diffusion barrier layer is a highly dense dielectric layer that prevents the ohmic metal layer from diffusing into the underlying first dielectric layer during the annealing process, thereby improving device reliability.

[0040] When etching the titanium nitride metal layer and the ohmic metal layer, the diffusion barrier layer is also etched to expose the first dielectric layer 31 .

[0041] Through the above steps, ohmic electrodes can be formed. An ohmic electrode is formed at each ohmic contact hole. The ohmic electrode formed at the ohmic contact hole in the source region is the source ohmic electrode, and the ohmic electrode formed at the ohmic contact hole in the drain region is the drain ohmic electrode. The ohmic electrodes can also be formed using other methods.

[0042] Step S140: depositing a second dielectric layer 32 on the first dielectric layer 31 and the ohmic electrode 2. Figure 2A FIG. 1 is a schematic diagram of the structure after the second dielectric layer 32 is deposited.

[0043] Step S150: fabricating a primary field plate 41 on the second dielectric layer 32. This step includes the following sub-steps.

[0044] Step S151, as Figure 2B As shown, a field plate metal is deposited on the second dielectric layer 32 and then a mask is set.

[0045] Step S152, forming a primary field plate 41 on the second dielectric layer 32 by etching, and finally removing the mask, such as Figure 2C , which is a schematic structural diagram after the primary field plate 41 is prepared and formed.

[0046] Step S160, as Figure 2D As shown, a lower dielectric layer 51 and an upper dielectric layer 52 are sequentially deposited on the second dielectric layer 32 and the primary field plate.

[0047] Among them, under the same etching conditions, the etching rate of the lower dielectric layer 51 is lower than the etching rate of the upper dielectric layer 52, so that when the upper dielectric layer is etched, the etching of the lower dielectric layer 51 is reduced, so that there is no need to set an additional etching barrier layer between the upper dielectric layer 52 and the lower dielectric layer 51 to prevent the lower dielectric layer 51 from being etched through, thereby reducing the production process and saving preparation time; at the same time, it can avoid the generation of gaps between the two dielectric layers, thereby reducing the local concentration effect of the electric field caused by etching damage, and improving the reliability of the device.

[0048] Furthermore, preferably, the etching rate ratio of the upper dielectric layer 52 to the lower dielectric layer 51 under the same etching conditions is greater than 10:1, so that the etching rate of the lower dielectric layer 51 is much lower than the etching rate of the upper dielectric layer 52. The upper dielectric layer 52 and the lower dielectric layer 51 can be made of homogeneous or heterogeneous materials. Here, a suitable dielectric material can be selected to achieve the above-mentioned etching rate ratio under the same conditions.

[0049] Step S170, etching the upper dielectric layer 52 except the upper field plate region to form an upper field plate region on the upper dielectric layer 52 and a lower field plate region on the lower dielectric layer 51. Figure 2E , which is a schematic diagram of the structure after etching of the upper dielectric layer 52 is completed.

[0050] When etching the upper dielectric layer 52, the upper dielectric layer 52 located in the upper field plate region is retained, and the rest of the upper dielectric layer 52 is completely etched away. Due to the large difference in etching rates between the upper and lower dielectric layers, after the upper dielectric layer 52 outside the upper field plate region is completely etched away, only a small portion of the lower dielectric layer 51 is etched away or is almost not etched, ensuring that the thickness of the lower dielectric layer 51 meets the predetermined requirements, thereby eliminating the need to set an etching stop layer between the two dielectric layers.

[0051] Step S180: performing etching in the gate region to form a gate contact hole 60. Figure 2F FIG. 1 is a schematic diagram of the structure after the gate contact hole 60 is prepared and formed.

[0052] The gate contact hole 60 penetrates the lower dielectric layer 51 , the second dielectric layer 32 and the first dielectric layer 31 , and reaches the silicon nitride layer 14 of the gallium nitride substrate 1 , so that the prepared gate metal can contact the silicon nitride layer 14 of the gallium nitride substrate 1 .

[0053] Step S190: forming a gate metal 6 in the gate contact hole 60, forming a lower field plate 71 on the lower field plate region, and forming an upper field plate 72 on the upper field plate region. Figure 2G , which is a schematic structural diagram after the gate metal 6 , the lower field plate 71 and the upper field plate 72 are prepared and formed.

[0054] Step S190 of this embodiment specifically includes the following sub-steps.

[0055] In step S191 , a field plate metal is deposited to fill the gate contact hole 60 and cover the upper surfaces of the lower dielectric layer 51 and the upper dielectric layer 52 .

[0056] Step S192, etching the field plate metal. Figure 2G , which is a schematic diagram of a double-layer field plate structure formed after etching. The field plate metal filled in the gate contact hole 60 forms the gate metal 6, a lower field plate 71 is formed above the lower dielectric layer 51, and an upper field plate 72 is formed above the upper dielectric layer 52. The lower field plate 71 and the upper dielectric layer 52 are arranged horizontally, and the upper field plate 72 is connected to the lower field plate 71 to form a double-layer field plate structure. In this embodiment, the gate metal 6 is also connected to the lower field plate 71. The lower field plate 71 is located above the primary field plate 41, and the projection of the primary field plate 41 on the horizontal plane is located within the projection of the lower field plate 71 on the horizontal plane.

[0057] Since there is no gap at the connection between the upper dielectric layer 52 and the lower dielectric layer 51, the structural damage caused by etching is small, and the field plate has a better shape forming effect at this position, thereby reducing the local concentration effect of the electric field and improving the reliability of the device.

[0058] The primary field plate 41, the lower field plate 71, and the upper field plate 72 form a multi-layer field plate structure. The upper field plate 72 is offset from the primary field plate, meaning their horizontal projections do not overlap. At least a portion of the lower field plate 71 is offset from the primary field plate 41, meaning its horizontal projection does not overlap. This allows each field plate to effectively exert its electric field effect at its corresponding location, effectively regulating the electric field distribution.

[0059] Embodiment 1 of the present invention further provides a semiconductor power device having a multilayer field plate, which is manufactured by the aforementioned manufacturing method. Figure 2G As shown, the semiconductor power device includes a gallium nitride substrate 1, a first dielectric layer 31, a second dielectric layer 32, a lower dielectric layer 51, and an upper dielectric layer 52, which are stacked in sequence. A primary field plate 41 is disposed between the lower dielectric layer 51 and the second dielectric layer 32. Under the same etching conditions, the etch rate ratio of the upper dielectric layer 52 to the lower dielectric layer 51 is greater than 10:1. A lower field plate 71 is disposed on the lower dielectric layer 51, and an upper field plate 72 is disposed on the upper dielectric layer 52.

[0060] A gate metal 6 is disposed within the lower dielectric layer 51 and the second dielectric layer 32, with the top of the gate metal 6 extending above the lower dielectric layer 51. In this embodiment, the bottom of the gate metal 6 penetrates the first dielectric layer 31 and contacts the silicon nitride layer 14 of the gallium nitride substrate. In other embodiments, the bottom of the gate metal 6 may not penetrate the first dielectric layer 31, but may directly contact the first dielectric layer 31. The gate metal 6 may be insulated from the ohmic electrode 2 by the first dielectric layer 31 or the silicon nitride layer 14.

[0061] The semiconductor power device further includes an ohmic electrode 2 , which is located below the second dielectric layer 32 and penetrates the first dielectric layer 31 . The bottom of the ohmic electrode 2 is connected to the gallium nitride substrate, and the ohmic electrode 2 is insulated from the gate metal 6 .

[0062] In this embodiment, the gallium nitride substrate 1 includes a silicon substrate 11, a gallium nitride (GaN) layer 12, an aluminum gallium nitride layer 13, and a silicon nitride layer 14, which are arranged in sequence. The first dielectric layer 31 is located on the side of the gallium nitride substrate 1 away from the silicon substrate 11. That is, the first dielectric layer 31 is deposited on the silicon nitride layer 14.

[0063] The ohmic electrode 2 penetrates the silicon nitride layer 14 and reaches the depth of the aluminum gallium nitride layer 13, so that the ohmic electrode 2 can contact the aluminum gallium nitride layer 13. The ohmic electrode 2 is preferably a stack of titanium and aluminum metals.

[0064] In this embodiment, in the horizontal direction, the primary field plate 41 is located between the upper field plate 72 and the gate metal 6, and the gate metal 6 is connected to the lower field plate 71, and the lower field plate 71 is connected to the upper field plate 72. The gate metal 6, the lower field plate 71, and the upper field plate 72 can be manufactured simultaneously in the same step to simplify the manufacturing process and improve manufacturing efficiency.

[0065] Example 2 The method for manufacturing a semiconductor power device with a multi-layer field plate provided in this embodiment has a field plate structure of the semiconductor power device as shown in FIG. Figure 3As shown, it is a further improvement on the basis of Example 1. The difference from Example 1 is that, before performing the etching operation on the gate region to form the gate contact hole 60 in step S180, it also includes the step of forming a protective dielectric layer 8 on the upper dielectric layer 52 and the lower dielectric layer 51. The protective dielectric layer 8 is a dielectric layer with good density, and its density is preferably higher than that of the lower dielectric layer 51 and the upper dielectric layer 52. The protective dielectric layer 8 can cover the etched damaged area, thereby preventing the etched damaged area from affecting the shape and structure of the field plate, thereby improving the reliability of the device.

[0066] After depositing the protective dielectric layer 8 , the gate contact hole 60 is formed by etching.

[0067] Example 3 In the method for manufacturing a semiconductor power device with a multi-layer field plate provided in this embodiment, the field plate structure of the semiconductor power device formed is as follows: Figure 4 As shown, this is a further improvement on the basis of Example 1. The difference from the first embodiment is that in step 190, after depositing the gate metal 6 and etching to form the gate metal 6, the lower field plate 71, and the upper field plate 72, the lower field plate 71 is separated from the gate metal 6. By isolating the lower field plate 71 from the gate metal 6, cracking caused by stress problems when large pieces of metal are connected together is reduced, thereby ensuring device reliability.

[0068] In this embodiment, since a primary field plate 41 is prepared on the device, the partition position between the lower field plate 71 and the gate metal 6 is located above the primary field plate 41, and the lower field plate 71 and the gate metal 6 are respectively located on both sides of the primary field plate 41; so as to reduce the mutual influence of the electric field between the lower field plate 71 and the primary field plate 41, and at the same time reduce the stress problem between different field plates.

[0069] The width W of the overlapping area between the lower field plate 71 and the primary field plate 41 projected on the horizontal plane is less than 1 / 5 of the width of the primary field plate 41. This relatively small width of the overlapping area can effectively reduce the stress of the lower field plate 71 at the location of the base field plate 4, reduce the mutual influence of the electric fields between the two, and facilitate the regulation of the electric field. It can be understood that the width direction referred to in each embodiment of the present invention is the left and right horizontal direction in the figure.

[0070] In the aforementioned embodiment, the lower field plate 71 is connected to the upper field plate 72 to reduce the problem of unstable electric fields at the adjacent edges of the two. Of course, in other embodiments, the upper field plate 72 and the lower field plate 71 can also be separated by etching, that is, the two are separated and not connected, and arranged in a horizontally spaced manner to avoid excessive stress problems caused by the large area of ​​connection between the two.

[0071] Example 4 The method for manufacturing a semiconductor power device with a multi-layer field plate provided in this embodiment is as follows: Figure 5 As shown, it includes the following steps.

[0072] Step S410 : providing a gallium nitride substrate, and depositing a first dielectric layer 31 on the gallium nitride substrate 1 .

[0073] Step S420 , etching the first dielectric layer 31 and the gallium nitride substrate 1 in the source region and the drain region to form ohmic contact holes 20 .

[0074] In step S430 , an ohmic metal layer is deposited in the ohmic contact hole 20 and on the first dielectric layer 31 , and the ohmic metal layer is etched to form an ohmic electrode 2 .

[0075] Step S440 : depositing a second dielectric layer 32 on the first dielectric layer 31 and the ohmic electrode 2 .

[0076] Step S450 , manufacturing a primary field plate 41 on the second dielectric layer 32 .

[0077] The aforementioned steps S410 to S450 may be identical to the specific contents of steps S110 to S150 in Example 1, and will not be repeated here.

[0078] Step S460 , depositing a third dielectric layer 33 on the second dielectric layer 32 and the primary field plate 41 .

[0079] In step S470 , an etching operation is performed in the gate region to form a gate contact hole 60 .

[0080] Step S480 , forming a gate metal 6 in the gate contact hole 60 , and fabricating a secondary field plate 42 on the third dielectric layer 33 .

[0081] In this step, after the metal layer is deposited, the gate metal 6 and the secondary field plate 42 can be simultaneously prepared by etching. In this embodiment, the secondary field plate 42 and the gate 6 can be simultaneously prepared by one metal deposition and etching, which simplifies the preparation process and improves the preparation efficiency. In this embodiment, the gate metal 6 is connected to the secondary field plate 42. Furthermore, the end of the secondary field plate 42 away from the gate metal 6 extends to the side of the primary field plate 41 away from the gate metal 6, so that the end of the secondary field plate 42 away from the gate metal 6 does not overlap with the projection of the primary field plate 41 in the horizontal plane, thereby allowing the secondary field plate 42 to better play the role of regulating the electric field.

[0082] In step S490, a lower dielectric layer 51 and an upper dielectric layer 52 are sequentially deposited on the gate metal 6, the secondary field plate 42 and the third dielectric layer 33, wherein under the same etching conditions, the etching rate of the lower dielectric layer 51 is lower than the etching rate of the upper dielectric layer 52, so that when the upper dielectric layer 52 is etched, the etching of the lower dielectric layer 51 is reduced, thereby eliminating the need for an additional etching barrier layer between the upper dielectric layer 52 and the lower dielectric layer 51 to prevent the lower dielectric layer 51 from being etched through, thereby reducing the manufacturing process and saving preparation time; at the same time, it can avoid the generation of gaps between the two dielectric layers, thereby reducing the local concentration effect of the electric field caused by etching damage, and improving the reliability of the device.

[0083] Furthermore, preferably, the etching rate ratio of the upper dielectric layer 52 to the lower dielectric layer 51 under the same etching conditions is greater than 10:1, so that the etching rate of the lower dielectric layer 51 is much lower than the etching rate of the upper dielectric layer 52. The upper dielectric layer 52 and the lower dielectric layer 51 can be made of homogeneous or heterogeneous materials. Here, a suitable dielectric material can be selected to achieve the above-mentioned etching rate ratio under the same conditions.

[0084] In step S491 , etching is performed on the upper dielectric layer 52 except the upper field plate region to form an upper field plate region on the upper dielectric layer 52 and a lower field plate region on the lower dielectric layer 51 .

[0085] Step S492: Form a lower field plate 71 on the lower field plate region, and form an upper field plate 72 on the upper field plate region. In this step, field plate metal is first deposited, covering the upper surfaces of the lower dielectric layer 51 and the remaining upper dielectric layer 52. Then, the field plate metal is etched to form the lower field plate 71 above the lower dielectric layer 51 and the upper field plate 72 above the upper dielectric layer 52. The upper field plate 72 is connected to the lower field plate 71 to form a double-layer field plate structure.

[0086] In this embodiment, the upper field plate 72 is staggered with the primary field plate 41 and the secondary field plate 42 , that is, the projections of the three on the horizontal plane do not overlap, so that the upper field plate 72 can better play the role of the electric field at the corresponding position.

[0087] The primary field plate 41, the secondary field plate 42, the lower field plate 71 and the upper field plate 72 form a four-layer field plate structure. In other embodiments, the number of field plates can be increased, and the number of dielectric layers can be increased to achieve a multi-layer field plate structure.

[0088] This embodiment 4 also provides a semiconductor power device with a multi-layer field plate, which is manufactured using the manufacturing method of the aforementioned embodiment 4. The semiconductor power device includes a gallium nitride substrate 1, a first dielectric layer 31, a second dielectric layer 32, a third dielectric layer 33, a lower dielectric layer 51, and an upper dielectric layer 52, which are stacked in sequence. A primary field plate 41 is disposed between the second dielectric layer 32 and the third dielectric layer 33, and a secondary field plate 42 is disposed between the lower dielectric layer 51 and the third dielectric layer 33. The etching rate ratio of the upper dielectric layer 52 to the lower dielectric layer 51 under the same etching conditions is greater than 10:1. A lower field plate 71 is disposed on the lower dielectric layer 51, and the lower field plate 71 and the upper dielectric layer 52 are arranged in a horizontal direction. The upper field plate 72 is disposed on the upper dielectric layer 52.

[0089] A gate metal 6 is disposed within the third dielectric layer 33 and the second dielectric layer 32, with the top of the gate metal 6 located below the lower dielectric layer 51. In this embodiment, the bottom of the gate metal 6 penetrates the first dielectric layer 31 and contacts the silicon nitride layer 14 of the gallium nitride substrate 1. In other embodiments, the bottom of the gate metal 6 may not penetrate the first dielectric layer 31, but may directly contact the first dielectric layer 31. The gate metal 6 may be insulated from the ohmic electrode 2 by the first dielectric layer 31 or the silicon nitride layer.

[0090] The semiconductor power device further includes an ohmic electrode 2 . The gallium nitride substrate 1 and the ohmic electrode 2 may be the same as those in the first embodiment, and are not described in detail here.

[0091] In this embodiment, in the horizontal direction, the primary field plate 41 and the secondary field plate 42 are both located between the upper field plate 72 and the gate metal 6, and the gate metal 6 is connected to the secondary field plate 42, and the lower field plate 71 is connected to the upper field plate 72. The gate metal 6 and the secondary field plate 42 can be manufactured simultaneously in the same step, and the lower field plate 71 and the upper field plate 72 can be manufactured simultaneously in the same step to simplify the manufacturing process and improve manufacturing efficiency.

[0092] Example 5 The method for manufacturing a semiconductor power device with a multi-layer field plate provided in this embodiment is as follows: Figure 6 As shown, it includes the following steps.

[0093] In step S510 , a gallium nitride substrate 1 is provided, and a first dielectric layer 31 is deposited on the gallium nitride substrate 1 .

[0094] In step S520 , the first dielectric layer 31 and the gallium nitride substrate 1 in the source region and the drain region are etched to form ohmic contact holes 20 .

[0095] In step S530 , an ohmic metal layer is deposited in the ohmic contact hole 20 and on the first dielectric layer 31 , and the ohmic metal layer is etched to form an ohmic electrode 2 .

[0096] Step S540 : depositing a second dielectric layer 32 on the first dielectric layer 31 and the ohmic electrode 2 .

[0097] Step S550 , manufacturing a primary field plate 41 on the second dielectric layer 32 .

[0098] The aforementioned steps S510 to S550 may be identical to the specific contents of steps S110 to S150 in Example 1, and will not be repeated here.

[0099] Step S560 , depositing a third dielectric layer 33 on the second dielectric layer 32 and the primary field plate 41 .

[0100] Step S570 , manufacturing a secondary field plate 42 on the third dielectric layer 33 .

[0101] In step S580, a lower dielectric layer 51 and an upper dielectric layer 52 are sequentially deposited on the third dielectric layer 33 and the secondary field plate 42. Under the same etching conditions, the etching rate of the lower dielectric layer 51 is lower than that of the upper dielectric layer 52. This reduces the etching rate of the lower dielectric layer 51 when the upper dielectric layer 52 is etched. This eliminates the need for an additional etch barrier layer between the upper dielectric layer 52 and the lower dielectric layer 51 to prevent the lower dielectric layer 51 from being etched through. This reduces the manufacturing process and saves preparation time. Furthermore, it prevents the formation of gaps between the two dielectric layers, thereby reducing the local concentration of the electric field caused by etching damage and improving device reliability.

[0102] Furthermore, preferably, the etching rate ratio of the upper dielectric layer 52 to the lower dielectric layer 51 under the same etching conditions is greater than 10:1, so that the etching rate of the lower dielectric layer 51 is much lower than the etching rate of the upper dielectric layer 52. The upper dielectric layer 52 and the lower dielectric layer 51 can be made of homogeneous or heterogeneous materials. Here, a suitable dielectric material can be selected to achieve the above-mentioned etching rate ratio under the same conditions.

[0103] In step S590 , etching is performed on the upper dielectric layer 52 except the upper field plate region to form an upper field plate region on the upper dielectric layer 52 and a lower field plate region on the lower dielectric layer 51 .

[0104] When etching the upper dielectric layer 52, the upper dielectric layer 52 located in the upper field plate region is retained, and the rest of the upper dielectric layer 52 is completely etched away. Due to the large difference in etching rates between the upper and lower dielectric layers, after the upper dielectric layer 52 outside the upper field plate region is completely etched away, only a small portion of the lower dielectric layer 51 is etched away or is almost not etched, ensuring that the thickness of the lower dielectric layer 51 meets the predetermined requirements, thereby eliminating the need to set an etching stop layer between the two dielectric layers.

[0105] In step S591 , an etching operation is performed in the gate region to form a gate contact hole 60 .

[0106] The gate contact hole 60 penetrates the lower dielectric layer 51 , the third dielectric layer 33 , the second dielectric layer 32 and the first dielectric layer 31 , and reaches the silicon nitride layer 14 of the gallium nitride substrate 1 , so that the prepared gate metal 6 can contact the silicon nitride layer 14 of the gallium nitride substrate 1 .

[0107] Step S592: forming a gate metal 6 on the gate contact hole 60, forming a lower field plate 71 on the lower field plate region, and forming an upper field plate 72 on the upper field plate region. This step may be the same as step S190 of embodiment 1 and will not be repeated here.

[0108] In this step, after the metal layer is deposited, etching can be performed to simultaneously form the gate metal 6, the lower field plate 71, and the upper field plate 72. This embodiment can simultaneously form the gate metal 6, the lower field plate 71, and the upper field plate 72 through a single metal deposition and etching process, thereby simplifying the preparation process and improving preparation efficiency.

[0109] In this embodiment, the upper field plate 72 is staggered with the primary field plate 41 and the secondary field plate 42 , that is, the projections of the three on the horizontal plane do not overlap, so that the upper field plate 72 can better play the role of the electric field at the corresponding position.

[0110] The primary field plate 41, the secondary field plate 42, the lower field plate 71 and the upper field plate 72 form a four-layer field plate structure. In other embodiments, the number of field plates can be increased, and the number of dielectric layers can be increased to achieve a multi-layer field plate structure.

[0111] This embodiment 5 also provides a semiconductor power device with a multi-layer field plate, fabricated using the fabrication method of the aforementioned embodiment 5. The semiconductor power device comprises a gallium nitride substrate 1, a first dielectric layer 31, a second dielectric layer 32, a third dielectric layer 33, a lower dielectric layer 51, and an upper dielectric layer 52, stacked in sequence. A primary field plate 41 is disposed between the second dielectric layer 32 and the third dielectric layer 33, and a secondary field plate 42 is disposed between the lower dielectric layer 51 and the third dielectric layer 33. Under the same etching conditions, the etching rate of the lower dielectric layer 51 is lower than that of the upper dielectric layer 52. Preferably, the etching rate ratio of the upper dielectric layer 52 to the lower dielectric layer 51 under the same etching conditions is greater than 10:1. A lower field plate 71 is disposed on the lower dielectric layer 51, and the lower field plate 71 is arranged horizontally with the upper dielectric layer 52. The upper field plate 72 is disposed on the upper dielectric layer 52. In this embodiment, the lower field plate 71 is connected to the upper field plate 72 .

[0112] A gate metal 6 is disposed within the third dielectric layer 33 and the second dielectric layer 32. The top of the gate metal 6 extends above the lower dielectric layer 51 and is connected to the lower field plate 71. In this embodiment, the bottom of the gate metal 6 penetrates the first dielectric layer 31 and contacts the silicon nitride layer 14 of the gallium nitride substrate 1. In other embodiments, the bottom of the gate metal 6 may not penetrate the first dielectric layer 31, but may directly contact the first dielectric layer 31. The gate metal 6 may be insulated from the ohmic electrode 2 by the first dielectric layer 31 or the silicon nitride layer.

[0113] The semiconductor power device further includes an ohmic electrode 2 . The gallium nitride substrate 1 and the ohmic electrode 2 may be the same as those in the first embodiment, and are not described in detail here.

[0114] In this embodiment, in the horizontal direction, the primary field plate 41 and the secondary field plate 42 are both located between the upper field plate 72 and the gate metal 6, and the gate metal 6 is connected to the lower field plate 71, and the lower field plate 71 is connected to the upper field plate 72. The gate metal 6, the lower field plate 71, and the upper field plate 72 can be manufactured simultaneously in the same step to simplify the manufacturing process and improve manufacturing efficiency.

[0115] Example 6 The method for manufacturing a semiconductor power device with a multi-layer field plate provided in this embodiment is as follows: Figure 7As shown. Example 6 is a further improvement on the above-mentioned Example 4. Specifically, before forming the lower field plate 71 on the lower field plate region and forming the upper field plate 72 on the upper field plate region in step S492 and after step S491, it also includes the step of forming a protective dielectric layer 8 on the lower dielectric layer 51 and the upper dielectric layer 52. The protective dielectric layer 8 is a dielectric layer with good density, and its density is preferably higher than that of the lower dielectric layer 51 and the upper dielectric layer 52. The protective dielectric layer 8 can cover the etched damaged area, thereby avoiding the influence of the etched damaged area on the shape structure of the field plate and improving the reliability of the device. The method and structure of depositing the protective dielectric layer 8 are also applicable to Examples 3 and 5.

[0116] Example 7.

[0117] The method for manufacturing a semiconductor power device with a multi-layer field plate provided in this embodiment is as follows: Figure 8 Example 7 is a further improvement on the above-mentioned Example 4, and the difference lies mainly in step S480 and step S492, as detailed below.

[0118] Step S480 , forming a gate metal 6 on the gate contact hole 60 , and manufacturing a secondary field plate 42 on the third dielectric layer 33 .

[0119] In this step, after the metal layer is deposited, the gate metal 6 and the secondary field plate 42 are separated during etching to isolate them. This isolation reduces stress-induced cracking caused by connecting large pieces of metal together, ensuring device reliability. The gate metal 6 and the secondary field plate 42 are isolated above the primary field plate 41. The gate metal 6 and the secondary field plate 42 are located on either side of the primary field plate 41 in the width direction, effectively avoiding stress issues caused by connecting large pieces of metal.

[0120] In step S492, a lower field plate 71 is formed on the lower field plate region, and an upper field plate 72 is formed on the upper field plate region. In this step, when etching is performed after depositing the metal layer, the lower field plate 71 only partially overlaps with the secondary field plate 42 after etching. The width of the overlapping area between the projections of the lower field plate 71 and the secondary field plate 42 on the horizontal plane is less than 1 / 5 of the width of the secondary field plate 42. The relatively small width of the overlapping area facilitates the regulation of the electric field distribution of the lower field plate 71 and the secondary field plate 42, and can reduce the stress of the lower field plate 71 at the position of the primary field plate 41.

[0121] The semiconductor power device with a multi-layer field plate provided by the present invention and the method for manufacturing the same have an etching rate ratio of greater than 10:1 between the upper dielectric layer 52 and the lower dielectric layer 51 under the same conditions. Due to the large difference in etching rates between the upper and lower dielectric layers, after the upper dielectric layer 52 outside the upper field plate region is completely etched away, only a small portion of the lower dielectric layer 51 is etched away. This eliminates the need for an etching stop layer between the two dielectric layers, reduces the manufacturing process, and saves preparation time. At the same time, it can avoid the formation of a gap between the two dielectric layers, and the field plate has a better shape forming effect at this position, thereby reducing the local concentration effect of the electric field caused by etching damage and improving the reliability of the device.

[0122] The lower dielectric layer 51 and the upper dielectric layer 52 may be covered with a protective dielectric layer 8. The protective dielectric layer 8 is a dielectric layer with good density, preferably higher than that of the lower dielectric layer 51 and the upper dielectric layer 52. The protective dielectric layer 8 can cover the etched damaged area, thereby preventing the etched damaged area from affecting the shape and structure of the field plate, thereby improving device reliability.

[0123] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. A person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor power device having a multi-layer field plate, characterized in that: The following steps are involved: a. providing a gallium nitride substrate, and depositing a first dielectric layer on the gallium nitride substrate; b. Etching the first dielectric layer and the gallium nitride substrate in the source region and the drain region to form ohmic contact holes; c. depositing an ohmic metal layer in the ohmic contact hole and on the first dielectric layer, and etching the ohmic metal layer to form an ohmic electrode; d. depositing a second dielectric layer on the first dielectric layer and the ohmic electrode; e. Fabricating a primary field plate on the second dielectric layer; f. sequentially depositing a lower dielectric layer and an upper dielectric layer on the second dielectric layer and the primary field plate, wherein under the same etching conditions, the etching rate of the lower dielectric layer is lower than the etching rate of the upper dielectric layer; g. performing an etching operation on the upper dielectric layer except the upper field plate region to form the upper field plate region on the upper dielectric layer and to form the lower field plate region on the lower dielectric layer; h. performing etching operation on the gate region to form a gate contact hole; i. Forming a gate metal in the gate contact hole, forming a lower field plate on the lower field plate region, and forming an upper field plate on the upper field plate region.

2. The method for manufacturing a semiconductor power device with a multi-layer field plate according to claim 1, characterized in that: Before the step of etching the gate region to form a gate contact hole, a protective dielectric layer is formed on the upper dielectric layer and the lower dielectric layer.

3. The method for manufacturing a semiconductor power device with a multi-layer field plate according to claim 1, characterized in that: The ratio of the etching rates of the upper dielectric layer and the lower dielectric layer under the same etching conditions is greater than 10:

1.

4. The method for manufacturing a semiconductor power device with a multi-layer field plate according to any one of claims 1 to 3, characterized in that: The lower field plate is connected to the gate metal, or the lower field plate is separated from the gate metal.

5. A method for manufacturing a semiconductor power device having a multi-layer field plate, characterized in that: The following steps are involved: a. providing a gallium nitride substrate, and depositing a first dielectric layer on the gallium nitride substrate; b. Etching the first dielectric layer and the gallium nitride substrate in the source region and the drain region to form ohmic contact holes; c. depositing an ohmic metal layer in the ohmic contact hole and on the first dielectric layer, and etching the ohmic metal layer to form an ohmic electrode; d. depositing a second dielectric layer on the first dielectric layer and the ohmic electrode; e. Fabricating a primary field plate on the second dielectric layer; f. depositing a third dielectric layer on the second dielectric layer and the primary field plate; g. performing etching operation on the gate region to form a gate contact hole; h. forming a gate metal in the gate contact hole and manufacturing a secondary field plate on the third dielectric layer; i. depositing a lower dielectric layer and an upper dielectric layer on the gate metal, the secondary field plate and the third dielectric layer in sequence, wherein under the same etching conditions, the etching rate of the lower dielectric layer is lower than the etching rate of the upper dielectric layer; j. Etching the upper dielectric layer except the upper field plate region to form the upper field plate region on the upper dielectric layer and the lower field plate region on the lower dielectric layer; k. forming a lower field plate on the lower field plate region, and forming an upper field plate on the upper field plate region.

6. The method for manufacturing a semiconductor power device with a multi-layer field plate according to claim 5, characterized in that: Before the steps of forming a lower-level field plate on the lower-level field plate region and forming a lower-level field plate on the lower-level field plate region, a protective dielectric layer is formed on the upper dielectric layer and the lower dielectric layer.

7. The method for manufacturing a semiconductor power device with a multi-layer field plate according to claim 5, characterized in that: The ratio of the etching rates of the upper dielectric layer and the lower dielectric layer under the same etching conditions is greater than 10:

1.

8. The method for manufacturing a semiconductor power device with a multi-layer field plate according to any one of claims 5 to 7, characterized in that: The secondary field plate is connected to the gate metal, or the secondary field plate is separated from the gate metal.

9. A method for manufacturing a semiconductor power device having a multi-layer field plate, characterized in that: The following steps are involved: a. providing a gallium nitride substrate, and depositing a first dielectric layer on the gallium nitride substrate; b. Etching the first dielectric layer and the gallium nitride substrate in the source region and the drain region to form ohmic contact holes; c. depositing an ohmic metal layer in the ohmic contact hole and on the first dielectric layer, and etching the ohmic metal layer to form an ohmic electrode; d. depositing a second dielectric layer on the first dielectric layer and the ohmic electrode; e. Fabricating a primary field plate on the second dielectric layer; f. depositing a third dielectric layer on the primary field plate and the second dielectric layer; g. Fabricating a secondary field plate on the third dielectric layer; h. Depositing a lower dielectric layer and an upper dielectric layer on the third dielectric layer and the secondary field plate in sequence; Wherein, under the same etching conditions, the etching rate of the lower dielectric layer is lower than the etching rate of the upper dielectric layer; i. performing an etching operation on the upper dielectric layer except the upper field plate region to form the upper field plate region on the upper dielectric layer and form the lower field plate region on the lower dielectric layer; j. performing an etching operation in the gate region to form a gate contact hole; k. Forming a gate metal in the gate contact hole, forming a lower field plate on the lower field plate region, and forming an upper field plate on the upper field plate region.

10. A semiconductor power device having a multi-layer field plate, characterized in that: The semiconductor power device is prepared by the method for manufacturing a semiconductor power device with a multi-layer field plate according to any one of claims 1 to 9.

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