Semiconductor package

Abstract

The semiconductor package may include: a base semiconductor chip; a connection semiconductor chip on the base semiconductor chip; an upper semiconductor chip on the connection semiconductor chip; a filling layer in the trench in the upper semiconductor chip; and a molding layer extending around the upper semiconductor chip.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0076190 filed in the Korean Intellectual Property Office on June 14, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to semiconductor packages, and in particular to semiconductor packages including a fill layer. Background Art

[0004] Semiconductor packages are configured to easily use integrated circuit chips as part of electronic products. Typically, semiconductor packages include a printed circuit board (PCB) and a semiconductor chip, which is mounted on the PCB and electrically connected to the PCB by using bonding wires or bumps. With the development of the semiconductor industry, many studies are being conducted to improve the reliability of semiconductor packages. Summary of the invention

[0005] Embodiments of the inventive concept provide a semiconductor package having improved electrical and reliability characteristics.

[0006] According to an embodiment of the present invention, a semiconductor package may include: a base semiconductor chip; a connecting semiconductor chip on the base semiconductor chip; an upper semiconductor chip on the connecting semiconductor chip, wherein the upper semiconductor chip includes a groove; a filling layer in the groove; and a molding layer extending around the upper semiconductor chip.

[0007] According to an embodiment of the inventive concept, a semiconductor package may include: a base semiconductor chip; a connecting semiconductor chip on the base semiconductor chip; an upper semiconductor chip on the connecting semiconductor chip; a filling layer in the upper semiconductor chip; and a molding layer extending around the upper semiconductor chip. The upper semiconductor chip may include an inner side surface in contact with the filling layer and an outer side surface in contact with the molding layer.

[0008] According to an embodiment of the present inventive concept, a semiconductor package may include: a base semiconductor chip; a terminal connected to the base semiconductor chip; a connecting semiconductor chip on the base semiconductor chip; an upper semiconductor chip on the connecting semiconductor chip; a filling layer in the upper semiconductor chip; and a molding layer extending around the connecting semiconductor chip and the upper semiconductor chip. The upper semiconductor chip may include a lower pad in contact with the connecting semiconductor chip, an interconnection structure electrically connected to the lower pad, and an upper substrate on the interconnection structure. The upper substrate may include a lower portion and a plurality of upper portions, and the plurality of upper portions of the upper substrate may be spaced apart from each other by the filling layer.

[0009] According to an embodiment of the inventive concept, a method of manufacturing a semiconductor package may include forming a base semiconductor chip; forming a connection semiconductor chip on the base semiconductor chip; forming a trench in an upper semiconductor chip; and bonding the upper semiconductor chip to the connection semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0011] Figure 1B It shows Figure 1A A plan view of a semiconductor package.

[0012] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F and Figure 2G It shows the manufacturing Figure 1A and Figure 1B A cross-sectional view of a method of semiconductor packaging.

[0013] Figure 3 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0014] Figure 4 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0015] Figure 5 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0016] Figure 6 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0017] Figure 7 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0018] Figure 8 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0019] Fig. 9 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0020] Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0021] Figure 1Ais a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. Figure 1B It shows Figure 1A A plan view of a semiconductor package.

[0022] Reference Figure 1A and Figure 1B , the semiconductor package may include a base semiconductor chip BC, a connection semiconductor chip CC, an upper semiconductor chip UC, a filling layer 41 , a molding layer 42 , and terminals TE.

[0023] The base semiconductor chip BC may include a first lower protective layer 11, a first interconnection structure 13 on the first lower protective layer 11, a first substrate 12 on the first interconnection structure 13, a first upper protective layer 14 on the first substrate 12, a first lower pad 15 in the first lower protective layer 11, a first upper pad 16 in the first upper protective layer 14, and a first through-via 17 penetrating the first substrate 12.

[0024] The first substrate 12 may be a plate-like (i.e., flat) structure extending in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may not be parallel to each other. As an example, the first direction D1 and the second direction D2 may be horizontal directions orthogonal to each other. The first substrate 12 may be a semiconductor substrate. As an example, the first substrate 12 may be formed of or include at least one of silicon, germanium, silicon germanium, phosphorus gallium, or gallium arsenic. In an embodiment, the first substrate 12 may be a silicon on insulator (SOI) substrate or a germanium on insulator (GOI) substrate.

[0025] The first lower protective layer 11 may cover the bottom surface of the first interconnect structure 13. The first lower protective layer 11 may be formed of an insulating material or include an insulating material. As an example, the first lower protective layer 11 may be formed of an oxide material or include an oxide material. In an embodiment, the first lower protective layer 11 may be a multilayer structure including a plurality of insulating layers.

[0026] The first interconnect structure 13 may cover a bottom surface of the first substrate 12. The first substrate 12 may be disposed on a top surface of the first interconnect structure 13.

[0027] The first interconnect structure 13 may include a first interconnect insulating layer and a first conductive structure. The first interconnect insulating layer may be disposed on the first lower protective layer 11. The first interconnect insulating layer may be formed of or include an insulating material. In an embodiment, the first interconnect insulating layer may be a multilayer structure including a plurality of insulating layers.

[0028] The first conductive structure may be disposed in the first interconnect insulating layer. The first conductive structure may be surrounded by the first interconnect insulating layer. The first conductive structure may include at least one of a conductive pad, a conductive contact portion, and a conductive wire. The first conductive structure of the first interconnect structure 13 may electrically connect the first through-via 17 to the first lower pad 15.

[0029] The first upper protective layer 14 may cover the top surface of the first substrate 12. The first upper protective layer 14 may include an insulating material. As an example, the first upper protective layer 14 may be formed of an oxide material or include an oxide material. In an embodiment, the first upper protective layer 14 may be a multilayer structure including a plurality of insulating layers.

[0030] The first lower pad 15 may be surrounded by the first lower protective layer 11. The first lower pad 15 may include a conductive material. As an example, the first lower pad 15 may be formed of or include copper.

[0031] The first upper pad 16 may be surrounded by the first upper protective layer 14. The first upper pad 16 may include a conductive material. As an example, the first upper pad 16 may be formed of or include copper.

[0032] The first through-via 17 may be connected to the first upper pad 16 and the first interconnect structure 13. The first through-via 17 may be arranged to penetrate the first substrate 12 along the third direction D3, and may electrically connect the first upper pad 16 to the first interconnect structure 13. The third direction D3 may not be parallel to the first direction D1 and the second direction D2. As an example, the third direction D3 may be a vertical direction orthogonal to the first direction D1 and the second direction D2. The first through-via 17 may be formed of a conductive material or include a conductive material.

[0033] The base semiconductor chip BC may be a logic semiconductor chip including a logic semiconductor device. The logic semiconductor device of the base semiconductor chip BC may be disposed between the first interconnect structure 13 and the first substrate 12. In an embodiment, the base semiconductor chip BC may be a memory semiconductor chip including a memory semiconductor device.

[0034] The terminal TE may be connected to the base semiconductor chip BC. The terminal TE may be in contact with the first lower pad 15. The terminal TE may be formed of or include a conductive material. The semiconductor package may be electrically connected to an external device through the terminal TE.

[0035] The connection semiconductor chip CC may be disposed on the base semiconductor chip BC. The connection semiconductor chip CC may be stacked on the base semiconductor chip BC along the third direction D3. Figure 1A As shown, the width of the connecting semiconductor chip CC in the first direction D1 may be smaller than the width of the base semiconductor chip BC in the first direction D1.

[0036] The number of connection semiconductor chips CC is not limited to the example shown. In an embodiment, four or more connection semiconductor chips CC may be provided.

[0037] Each connecting semiconductor chip CC may include a second lower protective layer 21, a second interconnect structure 23 on the second lower protective layer 21, a second substrate 22 on the second interconnect structure 23, a second upper protective layer 24 on the second substrate 22, a second lower pad 25 in the second lower protective layer 21, a second upper pad 26 in the second upper protective layer 24, and a second through-via 27 penetrating the second substrate 22.

[0038] The second substrate 22 may be a semiconductor substrate. In an embodiment, the second substrate 22 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0039] The second lower protective layer 21 may cover the bottom surface of the second interconnect structure 23. The second lower protective layer 21 may include an insulating material. As an example, the second lower protective layer 21 may be formed of an oxide material or include an oxide material. In an embodiment, the second lower protective layer 21 may be a multilayer structure including a plurality of insulating layers.

[0040] The second interconnect structure 23 may cover the bottom surface of the second substrate 22. The connection semiconductor chip CC may be a storage semiconductor chip including a storage semiconductor device. The storage semiconductor device of the connection semiconductor chip CC may be disposed between the second interconnect structure 23 and the second substrate 22.

[0041] The second interconnect structure 23 may include a second interconnect insulating layer and a second conductive structure. The second interconnect insulating layer may be disposed on the second lower protective layer 21. The second interconnect insulating layer may include an insulating material. In an embodiment, the second interconnect insulating layer may be a multilayer structure including a plurality of insulating layers.

[0042] The second conductive structure may be disposed in the second interconnect insulating layer. The second conductive structure may be surrounded by the second interconnect insulating layer. The second conductive structure may include at least one of a conductive pad, a conductive contact portion, and a conductive wire. The second conductive structure of the second interconnect structure 23 may electrically connect the second through-via 27 to the second lower pad 25.

[0043] The second upper protective layer 24 may cover the top surface of the second substrate 22. The second upper protective layer 24 may include an insulating material. As an example, the second upper protective layer 24 may be formed of an oxide material or include an oxide material. In an embodiment, the second upper protective layer 24 may be a multilayer structure including a plurality of insulating layers.

[0044] The second lower pad 25 may be surrounded by the second lower protective layer 21. The second lower pad 25 may be formed of or include a conductive material. As an example, the second lower pad 25 may be formed of or include copper.

[0045] The second upper pad 26 may be surrounded by the second upper protective layer 24. The second upper pad 26 may be formed of or include a conductive material. As an example, the second upper pad 26 may be formed of or include copper.

[0046] The second through via 27 may be connected to the second upper pad 26 and the second interconnection structure 23. The second through via 27 may be disposed to penetrate the second substrate 22 along the third direction D3, and may electrically connect the second upper pad 26 to the second interconnection structure 23. The second through via 27 may be formed of or include a conductive material.

[0047] The lowermost connecting semiconductor chip among the connecting semiconductor chips CC may be bonded to the base semiconductor chip BC in a hybrid bonding manner. The second lower protective layer 21 of the lowermost connecting semiconductor chip among the connecting semiconductor chips CC may be in contact with the first upper protective layer 14 of the base semiconductor chip BC. The second lower pad 25 of the lowermost connecting semiconductor chip among the connecting semiconductor chips CC may be in contact with the first upper pad 16 of the base semiconductor chip BC. The connecting semiconductor chips CC may be bonded to each other in a hybrid bonding manner.

[0048] The upper semiconductor chip UC may be disposed on the connecting semiconductor chip CC. The upper semiconductor chip UC may be bonded to the uppermost semiconductor chip in the connecting semiconductor chip CC in a hybrid bonding manner. Figure 1A As shown, the width of the upper semiconductor chip UC in the first direction D1 may be equal to the width of the connecting semiconductor chip CC in the first direction D1.

[0049] like Figure 1A As shown, the height of the upper semiconductor chip UC in the third direction D3 may be greater than the height of the connecting semiconductor chip CC in the third direction D3 and the height of the base semiconductor chip BC in the third direction D3. The distance between the top surface T1 and the bottom surface of the upper semiconductor chip UC in the third direction D3 may be greater than the distance between the top surface and the bottom surface of the connecting semiconductor chip CC in the third direction D3 and the distance between the top surface and the bottom surface of the base semiconductor chip BC in the third direction D3. In an embodiment, the height of the upper semiconductor chip UC in the third direction D3 may be equal to or greater than 100 μm.

[0050] The upper semiconductor chip UC may include a third lower protective layer 31 , a third interconnection structure 33 on the third lower protective layer 31 , an upper substrate 32 on the third interconnection structure 33 , and a third lower pad 35 in the third lower protective layer 31 .

[0051] The upper substrate 32 may be a semiconductor substrate. In an embodiment, the upper substrate 32 may be a silicon on insulator (SOI) substrate or a germanium on insulator (GOI) substrate. The height of the upper substrate 32 in the third direction D3 may be greater than the height of the first substrate 12 and the second substrate 22 in the third direction D3.

[0052] The third lower protective layer 31 may cover the bottom surface of the third interconnect structure 33. The third lower protective layer 31 may include an insulating material. As an example, the third lower protective layer 31 may be formed of an oxide material or include an oxide material. In an embodiment, the third lower protective layer 31 may be a multilayer structure including a plurality of insulating layers. The third lower protective layer 31 may contact the second upper protective layer 24 of the uppermost semiconductor chip connected in the semiconductor chip CC.

[0053] The third interconnect structure 33 may cover the bottom surface of the upper substrate 32. The upper semiconductor chip UC may be a storage semiconductor chip including a storage semiconductor device. The storage semiconductor device of the upper semiconductor chip UC may be disposed between the third interconnect structure 33 and the upper substrate 32. In an embodiment, the upper semiconductor chip UC may be a dummy semiconductor chip that does not include a semiconductor device.

[0054] The third interconnect structure 33 may include a third interconnect insulating layer and a third conductive structure. The third interconnect insulating layer may be disposed on the third lower protective layer 31. The third interconnect insulating layer may be formed of an insulating material or include an insulating material. In an embodiment, the third interconnect insulating layer may be a multilayer structure including a plurality of insulating layers.

[0055] The third conductive structure may be disposed in the third interconnect insulating layer. The third conductive structure may be surrounded by the third interconnect insulating layer. The third conductive structure may include at least one of a conductive pad, a conductive contact portion, and a conductive wire. The third conductive structure of the third interconnect structure 33 may be electrically connected to the third lower pad 35.

[0056] The third lower pad 35 may be surrounded by the third lower protective layer 31. The third lower pad 35 may contact the second upper pad 26 of the uppermost semiconductor chip connected in the connected semiconductor chip CC. The third lower pad 35 may be formed of a conductive material or include a conductive material. As an example, the third lower pad 35 may be formed of copper or include copper.

[0057] The upper semiconductor chip UC may be arranged to define a trench TR (ie, as shown, the trench TR is formed within the upper semiconductor chip UC). The trench TR may have a straight (ie, non-curved) shape extending in the second direction D2. The trenches TR may be spaced apart from each other in the first direction D1.

[0058] The filling layers 41 may be disposed in the trench TR. The filling layers 41 may have a straight shape extending in the second direction D2. The filling layers 41 may be spaced apart from each other in the first direction D1.

[0059] As shown in the figure, the mold layer 42 can be arranged to surround the upper semiconductor chip UC and the connecting semiconductor chip CC (i.e., extend around the upper semiconductor chip UC and the connecting semiconductor chip CC). As shown in the figure, the mold layer 42 can surround the filling layer 41 (i.e., extend around the filling layer 41). The mold layer 42 can be arranged on the base semiconductor chip BC.

[0060] The filling layer 41 and the molding layer 42 may be formed of or include the same material. In an embodiment, the molding layer 42 and the filling layer 41 may be formed of or include a polymer material. As an example, the polymer material may include an epoxy molding compound (EMC). The filling layer 41 and the molding layer 42 may be connected to each other without any observable interface therebetween, thereby forming a single body structure.

[0061] The trench TR may be defined by an upper substrate 32. The upper substrate 32 may include an upper portion 32a defining a side surface of the trench TR and a lower portion 32b defining a bottom surface of the trench TR.

[0062] The upper portion 32a of the upper substrate 32 may be disposed on the lower portion 32b of the upper substrate 32. The upper portion 32a of the upper substrate 32 may have a straight (ie, non-curved) shape extending in the second direction. Figure 1A As shown, the upper portions 32a of the upper substrate 32 may be spaced apart from each other in the first direction D1. The filling layer 41 may be disposed between the upper portions 32a of the upper substrate 32. The upper portions 32a of the upper substrate 32 may be spaced apart from each other by the filling layer 41. The lower portion 32b of the upper substrate 32 may be in contact with the bottom surface 41_B of the filling layer 41. The height of the upper portion 32a of the upper substrate 32 in the third direction D3 may be equal to the height of the filling layer 41 in the third direction D3.

[0063] The top surface T1 of the upper semiconductor chip UC, the top surface 41_T of the filling layer 41, and the top surface 42_T of the molding layer 42 may be coplanar with each other. The level of the top surface T1 of the upper semiconductor chip UC, the level of the top surface 41_T of the filling layer 41, and the level of the top surface 42_T of the molding layer 42 may be the same as each other. The top surface T1 of the upper semiconductor chip UC may be the top surface of the upper portion 32a of the upper substrate 32. The top surface T2 of the lower portion 32b of the upper substrate 32 may be in contact with the bottom surface 41_B of the filling layer 41. The top surface T2 of the lower portion 32b of the upper substrate 32 may be connected to the side surface of the upper portion 32a of the upper substrate 32.

[0064] The upper semiconductor chip UC may include an inner side surface S1 in contact with the filling layer 41 and an outer side surface S2 in contact with the molding layer 42. Figure 1A As shown, the length of the inner side surface S1 of the upper semiconductor chip UC in the third direction D3 may be less than the length of the outer side surface S2 of the upper semiconductor chip UC in the third direction D3. The inner side surface S1 of the upper semiconductor chip UC may be the side surface of the upper portion 32a of the upper substrate 32. The outer side surface S2 of the upper semiconductor chip UC may include the side surface of the upper portion 32a of the upper substrate 32 and the side surface of the lower portion 32b of the upper substrate 32. The side surface 41_S of the filling layer 41 may be in contact with the inner side surface S1 of the upper semiconductor chip UC.

[0065] The inner side surface S1 of the upper semiconductor chip UC may define a side surface of the trench TR.The top surface T2 of the lower portion 32 b of the upper substrate 32 may define a bottom surface of the trench TR.

[0066] In the semiconductor package according to the embodiment of the inventive concept, since the trench TR and the filling layer 41 are provided in the upper semiconductor chip UC, the rigidity of the upper semiconductor chip UC can be relatively reduced. Therefore, the formation of a gap between the upper semiconductor chip UC and the connecting semiconductor chip CC can be prevented or suppressed.

[0067] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F and Figure 2G It shows the manufacturing Figure 1A and Figure 1B A cross-sectional view of a method of semiconductor packaging.

[0068] Reference Figure 2A , a base semiconductor chip BC may be formed. The terminal TE may be formed to be connected to the first lower pad 15 of the base semiconductor chip BC.

[0069] Reference Figure 2B, a connection semiconductor chip CC may be formed on the base semiconductor chip BC. The lowermost connection semiconductor chip among the connection semiconductor chips CC may be bonded to the base semiconductor chip BC by a hybrid bonding process. The connection semiconductor chips CC may be bonded to each other by a hybrid bonding process.

[0070] Reference Figure 2C , an upper semiconductor chip UC may be formed. The formation of the upper semiconductor chip UC may include: forming a third interconnect structure 33 on the upper substrate 32 and forming a third lower pad 35 and a third lower protective layer 31 on the third interconnect structure 33. After forming the third lower pad 35 and the third lower protective layer 31, the upper substrate 32 may be turned over.

[0071] Reference Figure 2D , a process of thinning the upper substrate 32 may be performed to reduce a height of the upper substrate 32 in the third direction D3.

[0072] Reference Figure 2E , a trench TR may be formed in the upper semiconductor chip UC. The trench TR may be formed in the upper substrate 32 of the upper semiconductor chip UC. Due to the formation of the trench TR, a lower portion 32b and an upper portion 32a of the upper substrate 32 may be defined.

[0073] Reference Figure 2F , the upper semiconductor chip UC may be disposed on (ie, bonded to) the connecting semiconductor chip CC. For example, the upper semiconductor chip UC may be bonded to the connecting semiconductor chip CC through a hybrid bonding process.

[0074] Reference Figure 2G , the preliminary molding layer 43 may be formed to cover the connection semiconductor chip CC and the upper semiconductor chip UC. The preliminary molding layer 43 may fill the trench TR. The preliminary molding layer 43 may cover the top surface of the upper semiconductor chip UC. The preliminary molding layer 43 may be formed on the base semiconductor chip BC. The preliminary molding layer 43 may be formed of or include a polymer material.

[0075] Reference Figure 1A and Figure 1B , a process of thinning the preliminary mold layer 43 may be performed to remove an upper portion of the preliminary mold layer 43. Since the upper portion of the preliminary mold layer 43 is removed, the top surface T1 of the upper semiconductor chip UC may be exposed. The upper portion of the preliminary mold layer 43 may be removed to form a filling layer 41 and a molding layer 42.

[0076] In the method for manufacturing a semiconductor package according to an embodiment of the present invention, a groove TR may be formed in the upper semiconductor chip UC to reduce the rigidity of the upper semiconductor chip UC, and this may allow the upper semiconductor chip UC to be bonded to the connecting semiconductor chip CC in a hybrid bonding manner. That is, the upper semiconductor chip UC may be more easily deformed in the process of bonding the upper semiconductor chip UC to the connecting semiconductor chip CC. In addition, the bonding process may start from the center portion of the upper semiconductor chip UC and the center portion of the connecting semiconductor chip CC and proceed toward the edge portions of the upper semiconductor chip UC and the connecting semiconductor chip CC, and thus, the formation of a gap between the center portion of the upper semiconductor chip UC and the center portion of the connecting semiconductor chip CC may be prevented or suppressed.

[0077] Figure 3 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0078] Reference Figure 3 , the semiconductor package may include an upper semiconductor chip UC1 , a filling layer 141 , and a molding layer 142 . Figure 3 The upper semiconductor chip UC1, the filling layer 141 and the molding layer 142 may correspond to Figure 1A and Figure 1B The upper semiconductor chip UC, the filling layer 41 and the molding layer 42 are formed.

[0079] The trench TR1 may be defined by the upper semiconductor chip UC1. A filling layer 141 may be provided to fill the trench TR1. As shown in the figure, the filling layer 141 may include a straight portion 141b and a curved portion 141a. Figure 3 When viewed in a plan view of FIG. 1 , the straight portion 141 b of the filling layer 141 may have a straight (ie, non-curved) shape. Figure 3 When viewed in a plan view, the curved portion 141a of the filling layer 141 may have a curved shape.

[0080] The upper portion 132a of the upper substrate of the upper semiconductor chip UC1 may include a first flat side surface S11 and a first curved side surface S12. The first flat side surface S11 may be in contact with the straight portion 141b. The first curved side surface S12 may be in contact with the curved portion 141a. The first flat side surface S11 may be flat (ie, non-curved). The first curved side surface S12 may be curved.

[0081] The filling layer 141 may include a second flat side surface 141_S1 and a second curved side surface 141_S2. The second flat side surface 141_S1 may be in contact with the first flat side surface S11. The second curved side surface 141_S2 may be in contact with the first curved side surface S12. The second flat side surface 141_S1 may be flat (ie, non-curved). The second curved side surface 141_S2 may be curved. The second flat side surface 141_S1 may be a side surface of the straight portion 141b. The second curved side surface 141_S2 may be a side surface of the curved portion 141a.

[0082] Figure 4 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0083] Reference Figure 4 , the semiconductor package may include an upper semiconductor chip UC2 , a filling layer 241 , and a molding layer 242 . Figure 4 The upper semiconductor chip UC2, the filling layer 241 and the molding layer 242 may correspond to Figure 1A and Figure 1B The upper semiconductor chip UC, the filling layer 41 and the molding layer 42 are formed.

[0084] The trench TR2 may be defined by the upper semiconductor chip UC2. The filling layer 241 may be provided to fill the trench TR2. The filling layer 241 may include a first straight portion 241a and a second straight portion 241b. The first straight portion 241a may have a straight (ie, non-bent) shape extending along the second direction D2. The second straight portion 241b may have a straight shape extending along the first direction D1.

[0085] The upper portion 232a of the upper substrate of the upper semiconductor chip UC2 may include a first side surface S21 in contact with the first straight portion 241a and a second side surface S22 in contact with the second straight portion 241b. The first side surface S21 may be parallel to the second direction D2. The second side surface S22 may be parallel to the first direction D1.

[0086] The filling layer 241 may include a third side surface 241_S1 in contact with the first side surface S21 and a fourth side surface 241_S2 in contact with the second side surface S22 .

[0087] Figure 5 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0088] Reference Figure 5 , the semiconductor package may include an upper semiconductor chip UC3 , first to fourth filling layers 341 a , 341 b , 341 c , and 341 d , and a molding layer 342 . Figure 5The upper semiconductor chip UC3, the first to fourth filling layers 341a, 341b, 341c and 341d, and the mold layer 342 may correspond to Figure 1A and Figure 1B The upper semiconductor chip UC, the filling layer 41 and the molding layer 42 are formed.

[0089] The trench TR3 may be defined by the upper semiconductor chip UC3 . The trench TR3 may be surrounded by the upper semiconductor chip UC3 . The trench TR3 may be spaced apart from the mold layer 342 .

[0090] The first to fourth filling layers 341a, 341b, 341c, and 341d may be provided to fill the trench TR3, respectively. Figure 5 When viewed in a plan view of , each of the first to fourth filling layers 341a, 341b, 341c and 341d can have a circular shape. The first to fourth filling layers 341a, 341b, 341c and 341d can be radially spaced apart from each other (e.g., concentrically spaced apart). The first to fourth filling layers 341a, 341b, 341c and 341d can be spaced apart from the molding layer 342. The second filling layer 341b can be arranged to surround (i.e., concentrically surround) the first filling layer 341a. The third filling layer 341c can be arranged to surround (i.e., concentrically surround) the second filling layer 341b. The fourth filling layer 341d can be arranged to surround (i.e., concentrically surround) the third filling layer 341c.

[0091] The upper part 332a1, 332a2, 332a3, 332a4 and 332a5 of the upper substrate of the upper semiconductor chip UC3 may include an outermost portion 332a5 in contact with the mold layer 342, and first to fourth inner portions 332a1, 332a2, 332a3 and 332a4 surrounded by the outermost portion 332a5. The second inner portion 332a2 may be provided to surround (i.e., concentrically surround) the first inner portion 332a1, the third inner portion 332a3 may be provided to surround (i.e., concentrically surround) the second inner portion 332a2, and the fourth inner portion 332a4 may be provided to surround (i.e., concentrically surround) the third inner portion 332a3. The first to fourth inner portions 332a1, 332a2, 332a3 and 332a4 may be surrounded (i.e., concentrically surrounded) by the fourth filling layer 341d.

[0092] The outer side surface S31 of the outermost portion 332a5 may be flat. The outer side surface S31 of the outermost portion 332a5 may be in contact with the molding layer 342. The inner side surface S32 of the outermost portion 332a5 may be curved. The inner side surface S32 of the outermost portion 332a5 may be curved. The outer side surface S33 of the fourth inner portion 332a4 may be curved. The outer side surface 341d_S of the fourth filling layer 341d may be in contact with the inner side surface S32 of the outermost portion 332a5. The outer side surface 341d_S of the fourth filling layer 341d may be curved.

[0093] The first to fourth filling layers 341a, 341b, 341c, and 341d may be formed of or include the same material as the mold layer 342. In an embodiment, the first to fourth filling layers 341a, 341b, 341c, and 341d may be formed of or include a material different from the mold layer 342. In this case, the first to fourth filling layers 341a, 341b, 341c, and 341d may be formed of or include a heat dissipation material (e.g., thermal interface material (TIM)), and the mold layer 342 may be formed of or include a polymer material (e.g., EMC).

[0094] Figure 6 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0095] Reference Figure 6 , the semiconductor package may include an upper semiconductor chip UC4 , a filling layer 441 , and a molding layer 442 . Figure 6 The upper semiconductor chip UC4, the filling layer 441 and the molding layer 442 may correspond to Figure 1A and Figure 1B The upper semiconductor chip UC, the filling layer 41 and the molding layer 42 are formed.

[0096] The trench TR4 may be defined by the upper semiconductor chip UC4. A filling layer 441 may be provided to fill the trench TR4. The filling layer 441 may include a straight portion 441b and a curved portion 441a. Figure 6 When viewed in a plan view of FIG. 4 , the straight portion 441 b of the filling layer 441 may have a straight shape. Figure 6 When viewed in a plan view, the curved portion 441a of the filling layer 441 may have a curved shape.

[0097] The upper portions 432a1 and 432a2 of the upper substrate of the upper semiconductor chip UC4 may include an outermost portion 432a2 and an inner portion 432a1. The outermost portion 432a2 may contact the molding layer 442 and the filling layer 441. The inner portion 432a1 may be surrounded (i.e., surrounded) by the filling layer 441. The filling layer 441 may be spaced apart from the molding layer 442 by the outermost portion 432a2.

[0098] Figure 7 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0099] Reference Figure 7 , the semiconductor package may include an upper semiconductor chip UC5 , a filling layer 541 , and a molding layer 542 . Figure 7 The upper semiconductor chip UC5, the filling layer 541 and the molding layer 542 may correspond to Figure 1A and Figure 1B The upper semiconductor chip UC, the filling layer 41 and the molding layer 42 are formed.

[0100] The trench TR5 may be defined by the upper semiconductor chip UC5. The filling layer 541 may fill the trench TR5. The filling layer 541 may include a rounded portion 541a and a curved portion 541b. Figure 7 When viewed in a plan view of FIG. 5 , the circular portion 541a of the filling layer 541 may have a circular shape. Figure 7 The bent portion 541 b of the filling layer 541 may have a bent shape when viewed in a plan view of FIG. The bent portion 541 b may be connected to the round portion 541 a and the mold layer 542 . The upper portions 532 a of the upper substrate of the upper semiconductor chip UC5 may be spaced apart from each other by the filling layer 541 .

[0101] Figure 8 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0102] Reference Figure 8 , the semiconductor package may include an upper semiconductor chip UC6 , a filling layer 641 , and a molding layer 642 . Figure 8 The upper semiconductor chip UC6, the filling layer 641 and the molding layer 642 may correspond to Figure 1A and Figure 1B The upper semiconductor chip UC, the filling layer 41 and the molding layer 42 are formed.

[0103] The trench TR6 may be defined by the upper semiconductor chip UC6. The filling layer 641 may fill the trench TR6. The filling layer 641 may include a rounded portion 641a and a straight portion 641b. Figure 8 When viewed in a plan view, the circular portion 641a may have a circular shape. Figure 8The straight portion 641 b may have a straight shape when viewed in a plan view of FIG.

[0104] Fig. 9 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0105] Reference Fig. 9 The semiconductor package may include a first terminal TE1, a package substrate 70, a second terminal TE2, an interposer 60, a third terminal TE3, a base semiconductor chip BC, a connection semiconductor chip CC, an upper semiconductor chip UC, a filling layer 41, a molding layer 42, a fourth terminal TE4, a processor chip 50 and a package molding layer 44.

[0106] Fig. 9 The upper semiconductor chip UC, the connection semiconductor chip CC, the base semiconductor chip BC, the filling layer 41, the molding layer 42 and the third terminal TE3 may correspond to Figure 1A and Figure 1B The upper semiconductor chip UC, the connection semiconductor chip CC, the base semiconductor chip BC, the filling layer 41, the molding layer 42 and the terminals TE.

[0107] The package substrate 70 may be disposed on the first terminal TE1. For example, the package substrate 70 may be a printed circuit board. The semiconductor package may be mounted on an external device (eg, a mainboard) through the first terminal TE1. The first terminal TE1 may be formed of or include a conductive material.

[0108] The interposer 60 may be provided on the package substrate 70. The second terminal TE2 may be provided to electrically connect the package substrate 70 to the interposer 60. The second terminal TE2 may be formed of or include a conductive material.

[0109] The processor chip 50 may be disposed on the interposer 60. The processor chip 50 may be, for example, a graphics processing unit (GPU) or a central processing unit (CPU). The fourth terminal TE4 may be provided to electrically connect the processor chip 50 to the interposer 60. The fourth terminal TE4 may be formed of or include a conductive material.

[0110] The base semiconductor chip BC, the connection semiconductor chip CC and the upper semiconductor chip UC may be disposed on the interposer 60. The filling layer 41 may be disposed in the upper semiconductor chip UC. As shown in the figure, the molding layer 42 may be disposed to surround the upper semiconductor chip UC and the connection semiconductor chip CC (i.e., extend around them). The base semiconductor chip BC and the interposer 60 may be electrically connected to each other through the third terminal TE3.

[0111] The encapsulation molding layer 44 may be disposed on the encapsulation substrate 70. The encapsulation molding layer 44 may be disposed to surround the interposer 60, the processor chip 50, the base semiconductor chip BC, and the molding layer 42. The encapsulation molding layer 44 may be formed of or include a polymer material.

[0112] In the semiconductor package according to the embodiment of the inventive concept, the groove and the filling layer may be provided in the upper semiconductor chip. In this case, the upper semiconductor chip may have relatively low rigidity and can prevent a gap from being formed between the upper semiconductor chip and the connection semiconductor chip.

[0113] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the scope of the appended claims.

Claims

1. A semiconductor package, include: Base semiconductor chip; connecting a semiconductor chip on the base semiconductor chip; an upper semiconductor chip, on the connecting semiconductor chip, the upper semiconductor chip comprising a groove; filling layer in the groove, and A molding layer extends around the upper semiconductor chip.

2. The semiconductor package according to claim 1, in, The trench is in an upper portion of the upper semiconductor chip.

3. The semiconductor package according to claim 1, in, The upper semiconductor chip comprises: a lower pad on the connecting semiconductor chip; an interconnect structure electrically connected to the lower pad; and an upper substrate, on the interconnect structure, Wherein, the groove is in the upper substrate.

4. The semiconductor package according to claim 3, in, The upper substrate includes an upper portion and a lower portion, wherein a side surface of the trench is in the upper portion, and a bottom surface of the trench is a top surface of the lower portion.

5. The semiconductor package according to claim 4, in, The upper portion of the upper substrate includes a flat side surface and a curved side surface.

6. The semiconductor package according to claim 1, in, The filling layer and the molding layer are connected to each other without any interface therebetween, thereby forming a single body structure.

7. The semiconductor package according to claim 1, in, The filling layer includes a flat side surface and a curved side surface.

8. The semiconductor package according to claim 1, in, The filling layer is spaced apart from the molding layer.

9. The semiconductor package according to claim 1, in, A top surface of the filling layer, a top surface of the upper semiconductor chip, and a top surface of the molding layer are coplanar.

10. A semiconductor package, include: Base semiconductor chip; connecting a semiconductor chip on the base semiconductor chip; an upper semiconductor chip, on the connecting semiconductor chip; a filling layer in the upper semiconductor chip; as well as a molding layer extending around the upper semiconductor chip, The upper semiconductor chip includes an inner surface in contact with the filling layer and an outer surface in contact with the molding layer.

11. The semiconductor package according to claim 10, in, The filling layer is surrounded by the molding layer.

12. The semiconductor package according to claim 10, in, the upper semiconductor chip includes a lower portion contacting a bottom surface of the filling layer and an upper portion on the lower portion of the upper semiconductor chip, The upper portions of the upper semiconductor chips are spaced apart from each other by the filling layer.

13. The semiconductor package according to claim 12, in, The upper portion of the upper semiconductor chip includes an outermost portion contacting the mold layer and an inner portion surrounded by the outermost portion, wherein the outermost outer surface is flat, and Wherein, the inner surface of the outermost portion is curved.

14. The semiconductor package according to claim 10, in, The filling layer includes a plurality of first straight portions extending along a first direction and a plurality of second straight portions extending along a second direction transverse to the first direction.

15. The semiconductor package according to claim 10, in, The inner side surface of the upper semiconductor chip is curved, and Wherein, the outer surface of the upper semiconductor chip is flat.

16. The semiconductor package according to claim 10, in, The molding layer and the filling layer include the same material.

17. The semiconductor package according to claim 10, in, The molding layer and the filling layer include respective different materials.

18. The semiconductor package according to claim 10, in, The height of the upper semiconductor chip is greater than the height of the connecting semiconductor chip.

19. A semiconductor package, include: Base semiconductor chip; a terminal connected to the base semiconductor chip; connecting a semiconductor chip on the base semiconductor chip; an upper semiconductor chip, on the connecting semiconductor chip; a filling layer in the upper semiconductor chip; as well as a molding layer extending around the connecting semiconductor chip and the upper semiconductor chip, Wherein, the upper semiconductor chip comprises: a lower pad in contact with the connecting semiconductor chip; an interconnect structure electrically connected to the lower pad; and an upper substrate, on the interconnect structure, Wherein, the upper substrate includes a lower portion and a plurality of upper portions, and Wherein, the plurality of upper portions of the upper substrate are spaced apart from each other by the filling layer.

20. The semiconductor package according to claim 19, in, A top surface of the lower portion of the upper substrate contacts a bottom surface of the filling layer, and Wherein, a side surface of each of the plurality of upper portions of the upper substrate contacts a side surface of the filling layer.

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