Memory chip, chip stacking structure and memory

Abstract

The invention provides a memory chip, a chip stacking structure and a memory, for the memory chip, n through hole groups of a first area and n through hole groups of a second area are symmetrical about a first axis, and n through hole groups of a third area and n through hole groups of a fourth area are symmetrical about the first axis, the n through hole groups of the first area and the n through hole groups of the fourth area are symmetrical about a second axis; and for each through hole group, the first through hole and the second through hole are symmetrical about a third axis, the third through hole and the fourth through hole are symmetrical about the third axis, and the first through hole and the fourth through hole are symmetrical about the fourth axis.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a memory chip, a chip stacking structure and a memory. Background Art

[0002] With the development of integrated circuit technology, the production process of semiconductor devices has made significant progress. However, in recent years, the development of two-dimensional semiconductor technology has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered by two-dimensional semiconductor devices and pursue lower production costs per unit storage unit, multiple chips can be stacked using a bonding process to form a three-dimensional semiconductor device. However, for three-dimensional semiconductor devices, the connection structure between different chips still has problems such as large parasitic capacitance and large parasitic resistance, which affects the quality of signal transmission. Summary of the invention

[0003] The present disclosure provides a memory chip, a chip stacking structure and a memory.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a memory chip, the memory chip comprising 2×2 regions distributed in an array along its active surface, each of the regions being penetrated by n through-hole groups, where n is a natural number; the n through-hole groups in the first region and the n through-hole groups in the second region are symmetrical about a first axis, the n through-hole groups in the third region and the n through-hole groups in the fourth region are symmetrical about the first axis, and the n through-hole groups in the first region and the n through-hole groups in the fourth region are symmetrical about a second axis; wherein the first axis and the second axis are both located on the active surface, the first axis and the second axis are perpendicular to each other and intersect at the center of the active surface; for each of the through-hole groups , which includes 2×2 through holes distributed in an array, the first through hole and the second through hole are symmetrical about the third axis, the third through hole and the fourth through hole are symmetrical about the third axis, and the first through hole and the fourth through hole are symmetrical about the fourth axis; wherein the third axis and the fourth axis are both located on the active surface, and the third axis and the fourth axis are both located on the active surface, the third axis and the fourth axis are perpendicular to each other and intersect at the center of the through hole group; the first axis and the third axis of each through hole group are parallel to the first side of the memory chip, and the second axis and the fourth axis of each through hole group are parallel to the second side of the memory chip.

[0006] In some embodiments, the n first through holes in the first region and the n second through holes in the second region are symmetrical about the first axis; the n third through holes in the third region and the n fourth through holes in the fourth region are symmetrical about the first axis; the n first through holes in the first region and the n fourth through holes in the fourth region are symmetrical about the second axis.

[0007] In some embodiments, the n second through holes in the first region and the n first through holes in the second region are symmetrical about the first axis; the n fourth through holes in the third region and the n third through holes in the fourth region are symmetrical about the first axis; the n second through holes in the first region and the n third through holes in the fourth region are symmetrical about the second axis.

[0008] In some embodiments, the n third through holes in the first region and the n fourth through holes in the second region are symmetrical about the first axis; the n first through holes in the third region and the n second through holes in the fourth region are symmetrical about the first axis; the n third through holes in the first region and the n second through holes in the fourth region are symmetrical about the first axis.

[0009] In some embodiments, the n fourth through holes in the first region and the n third through holes in the second region are symmetrical about the first axis; the n second through holes in the third region and the n first through holes in the fourth region are symmetrical about the first axis; the n fourth through holes in the first region and the n first through holes in the fourth region are symmetrical about the second axis.

[0010] In some embodiments, any of the through holes penetrates the memory chip in a direction perpendicular to the active surface, and different through holes in the same memory chip are electrically isolated.

[0011] In some embodiments, the memory chip further includes 4n first driving circuits; the 4n through holes are connected to the 4n first driving circuits in a one-to-one correspondence, and there is only one through hole in each through hole group connected to the first driving circuit.

[0012] In some embodiments, the memory chip further includes a positioning structure; the positioning structure is located in one of the reference areas to identify the location of the reference area; wherein the reference area is one of the 2×2 areas.

[0013] In a second aspect, an embodiment of the present disclosure provides a chip stacking structure, the chip stacking structure comprising at least one stacking unit, each of the stacking units comprising a first memory chip, a second memory chip, a third memory chip and a fourth memory chip stacked in sequence along a third direction, wherein the third direction is perpendicular to the active surface of each of the memory chips; the first memory chip, the second memory chip, the third memory chip and the fourth memory chip are all memory chips as described in any one of claims 1 to 7; the first memory chip and the second memory chip are stacked face to face, the second memory chip and the third memory chip are stacked back to back, and the third memory chip and the fourth memory chip are stacked face to face.

[0014] In some embodiments, the first area in the first storage chip, the second area in the second storage chip, the third area in the third storage chip, and the fourth area in the fourth storage chip are aligned along a third direction; the second area in the first storage chip, the first area in the second storage chip, the fourth area in the third storage chip, and the third area in the fourth storage chip are aligned along the third direction; the third area in the first storage chip, the fourth area in the second storage chip, the first area in the third storage chip, and the second area in the fourth storage chip are aligned along the third direction; the fourth area in the first storage chip, the third area in the second storage chip, the second area in the third storage chip, and the first area in the fourth storage chip are aligned along the third direction.

[0015] In some embodiments, the n first through holes in the first area of ​​the first storage chip, the n second through holes in the second area of ​​the second storage chip, the n third through holes in the third area of ​​the third storage chip, and the n fourth through holes in the fourth area of ​​the fourth storage chip are aligned along a third direction; the n second through holes in the first area of ​​the first storage chip, the n first through holes in the second area of ​​the second storage chip, the n fourth through holes in the third area of ​​the third storage chip, and the n third through holes in the fourth area of ​​the fourth storage chip are aligned along a third direction; the n third through holes in the first area of ​​the first storage chip, the n fourth through holes in the second area of ​​the second storage chip, the n first through holes in the third area of ​​the third storage chip, and the n second through holes in the fourth area of ​​the fourth storage chip are aligned along a third direction; the n fourth through holes in the first area of ​​the first storage chip, the n third through holes in the second area of ​​the second storage chip, the n second through holes in the third area of ​​the third storage chip, and the n first through holes in the fourth area of ​​the fourth storage chip are aligned along a third direction.

[0016] In some embodiments, the n first through holes in the second area of ​​the first storage chip, the n second through holes in the first area of ​​the second storage chip, the n third through holes in the fourth area of ​​the third storage chip, and the n fourth through holes in the third area of ​​the fourth storage chip are aligned along a third direction; the n second through holes in the second area of ​​the first storage chip, the n first through holes in the first area of ​​the second storage chip, the n fourth through holes in the fourth area of ​​the third storage chip, and the n third through holes in the third area of ​​the fourth storage chip are aligned along a third direction; the n third through holes in the second area of ​​the first storage chip, the n fourth through holes in the first area of ​​the second storage chip, the n first through holes in the fourth area of ​​the third storage chip, and the n second through holes in the third area of ​​the fourth storage chip are aligned along a third direction; the n fourth through holes in the second area of ​​the first storage chip, the n third through holes in the first area of ​​the second storage chip, the n second through holes in the fourth area of ​​the third storage chip, and the n first through holes in the third area of ​​the fourth storage chip are aligned along a third direction.

[0017] In some embodiments, the n first through holes in the third area of ​​the first storage chip, the n second through holes in the fourth area of ​​the second storage chip, the n third through holes in the first area of ​​the third storage chip, and the n fourth through holes in the second area of ​​the fourth storage chip are aligned along a third direction; the n second through holes in the third area of ​​the first storage chip, the n first through holes in the fourth area of ​​the second storage chip, the n fourth through holes in the first area of ​​the third storage chip, and the n third through holes in the second area of ​​the fourth storage chip are aligned along a third direction; the n third through holes in the third area of ​​the first storage chip, the n fourth through holes in the fourth area of ​​the second storage chip, the n first through holes in the first area of ​​the third storage chip, and the n second through holes in the second area of ​​the fourth storage chip are aligned along a third direction; the n fourth through holes in the third area of ​​the first storage chip, the n third through holes in the fourth area of ​​the second storage chip, the n second through holes in the first area of ​​the third storage chip, and the n first through holes in the second area of ​​the fourth storage chip are aligned along a third direction.

[0018] In some embodiments, the n first through holes in the fourth area of ​​the first storage chip, the n second through holes in the third area of ​​the second storage chip, the n third through holes in the second area of ​​the third storage chip, and the n fourth through holes in the first area of ​​the fourth storage chip are aligned along a third direction; the n second through holes in the fourth area of ​​the first storage chip, the n first through holes in the third area of ​​the second storage chip, the n fourth through holes in the second area of ​​the third storage chip, and the n third through holes in the first area of ​​the fourth storage chip are aligned along a third direction; the n third through holes in the fourth area of ​​the first storage chip, the n fourth through holes in the third area of ​​the second storage chip, the n first through holes in the second area of ​​the third storage chip, and the n second through holes in the first area of ​​the fourth storage chip are aligned along a third direction; the n fourth through holes in the fourth area of ​​the first storage chip, the n third through holes in the third area of ​​the second storage chip, the n second through holes in the second area of ​​the third storage chip, and the n first through holes in the first area of ​​the fourth storage chip are aligned along a third direction.

[0019] In some embodiments, the first area in the first storage chip, the fourth area in the second storage chip, the third area in the third storage chip, and the second area in the fourth storage chip are aligned along a third direction; the second area in the first storage chip, the third area in the second storage chip, the fourth area in the third storage chip, and the first area in the fourth storage chip are aligned along the first direction; the third area in the first storage chip, the second area in the second storage chip, the first area in the third storage chip, and the fourth area in the fourth storage chip are aligned along the third direction; the fourth area in the first storage chip, the first area in the second storage chip, the second area in the third storage chip, and the third area in the fourth storage chip are aligned along the third direction.

[0020] In some embodiments, the n first through holes in the first area of ​​the first memory chip, the n fourth through holes in the fourth area of ​​the second memory chip, the n third through holes in the third area of ​​the third memory chip, and the n second through holes in the second area of ​​the fourth memory chip are aligned along a third direction; the n second through holes in the first area of ​​the first memory chip, the n third through holes in the fourth area of ​​the second memory chip, the n fourth through holes in the third area of ​​the third memory chip, and the n first through holes in the second area of ​​the fourth memory chip are aligned along a third direction; the n third through holes in the first area of ​​the first memory chip, the n second through holes in the fourth area of ​​the second memory chip, the n first through holes in the third area of ​​the third memory chip, and the n fourth through holes in the second area of ​​the fourth memory chip are aligned along a third direction; the n fourth through holes in the first area of ​​the first memory chip, the n first through holes in the fourth area of ​​the second memory chip, the n second through holes in the third area of ​​the third memory chip, and the n third through holes in the second area of ​​the fourth memory chip are aligned along a third direction.

[0021] In some embodiments, the n first through holes in the second area of ​​the first storage chip, the n fourth through holes in the third area of ​​the second storage chip, the n third through holes in the fourth area of ​​the third storage chip, and the n second through holes in the first area of ​​the fourth storage chip are aligned along a third direction; the n second through holes in the second area of ​​the first storage chip, the n third through holes in the third area of ​​the second storage chip, the n fourth through holes in the fourth area of ​​the third storage chip, and the n first through holes in the first area of ​​the fourth storage chip are aligned along a third direction; the n third through holes in the second area of ​​the first storage chip, the n second through holes in the third area of ​​the second storage chip, the n first through holes in the fourth area of ​​the third storage chip, and the n fourth through holes in the first area of ​​the fourth storage chip are aligned along a third direction; the n fourth through holes in the second area of ​​the first storage chip, the n first through holes in the third area of ​​the second storage chip, the n second through holes in the fourth area of ​​the third storage chip, and the n third through holes in the first area of ​​the fourth storage chip are aligned along a third direction.

[0022] In some embodiments, the n first through holes in the third area of ​​the first storage chip, the n fourth through holes in the second area of ​​the second storage chip, the n third through holes in the first area of ​​the third storage chip, and the n second through holes in the fourth area of ​​the fourth storage chip are aligned along a third direction; the n second through holes in the third area of ​​the first storage chip, the n third through holes in the second area of ​​the second storage chip, the n fourth through holes in the first area of ​​the third storage chip, and the n first through holes in the fourth area of ​​the fourth storage chip are aligned along a third direction; the n third through holes in the third area of ​​the first storage chip, the n second through holes in the second area of ​​the second storage chip, the n first through holes in the first area of ​​the third storage chip, and the n fourth through holes in the fourth area of ​​the fourth storage chip are aligned along a third direction; the n fourth through holes in the third area of ​​the first storage chip, the n first through holes in the second area of ​​the second storage chip, the n second through holes in the first area of ​​the third storage chip, and the n third through holes in the fourth area of ​​the fourth storage chip are aligned along a third direction.

[0023] In some embodiments, the n first through holes in the fourth area of ​​the first storage chip, the n fourth through holes in the first area of ​​the second storage chip, the n third through holes in the second area of ​​the third storage chip, and the n second through holes in the third area of ​​the fourth storage chip are aligned along a third direction; the n second through holes in the fourth area of ​​the first storage chip, the n third through holes in the first area of ​​the second storage chip, the n fourth through holes in the second area of ​​the third storage chip, and the n first through holes in the third area of ​​the fourth storage chip are aligned along a third direction; the n third through holes in the fourth area of ​​the first storage chip, the n second through holes in the first area of ​​the second storage chip, the n first through holes in the second area of ​​the third storage chip, and the n fourth through holes in the third area of ​​the fourth storage chip are aligned along a third direction; the n fourth through holes in the fourth area of ​​the first storage chip, the n first through holes in the first area of ​​the second storage chip, the n second through holes in the second area of ​​the third storage chip, and the n third through holes in the third area of ​​the fourth storage chip are aligned along a third direction.

[0024] In some embodiments, for two memory chips connected face to face, the through holes aligned along the third direction are connected through a hybrid bonding structure; for two memory chips connected back to back, the through holes aligned along the third direction are connected through a conductive bump; or, for two memory chips connected face to face or for two memory chips connected back to back, the through holes aligned along the third direction are connected through a hybrid bonding structure; or, for two memory chips connected face to face or for two memory chips connected back to back, the through holes aligned along the third direction are connected through a conductive bump.

[0025] In some embodiments, each of the memory chips further comprises 4n first driving circuits; in each of the memory chips, the 4n first driving circuits are connected one-to-one with the first ends of the 4n first through holes; wherein the first ends are located at the active surface of the memory chip.

[0026] In some embodiments, the chip stacking structure also includes a logic chip; the first stacking unit is stacked on the logic chip along a third direction, and the remaining stacking units are stacked on the previous stacking unit in sequence along the third direction; the logic chip includes 16n fifth through holes and 16n second driving circuits, wherein 4n fifth through holes are aligned with 4n first through holes in the first storage chip in a one-to-one correspondence along the third direction, wherein 4n fifth through holes are aligned with 4n second through holes in the first storage chip in a one-to-one correspondence along the third direction, wherein 4n fifth through holes are aligned with 4n third through holes in the first storage chip in a one-to-one correspondence along the third direction, wherein 4n fifth through holes are aligned with 4n fourth through holes in the first storage chip in a one-to-one correspondence along the third direction; wherein 16n second driving circuits are connected to the first ends of the 16n fifth through holes in a one-to-one correspondence, and the first ends are located on the active surface of the logic chip.

[0027] In some embodiments, the chip stacking structure also includes 16n electrical paths; if the chip stacking structure includes m stacking units, then one fifth through hole, m first through holes, m second through holes, m third through holes and m fourth through holes aligned along a third direction are connected to form one electrical path, where m is a positive integer.

[0028] In a third aspect, an embodiment of the present disclosure provides a memory comprising the chip stacking structure as described in the second aspect.

[0029] The embodiments of the present disclosure provide a memory chip, a chip stacking structure and a memory, which not only reduce the number of drive circuits and data selectors, thereby reducing parasitic capacitance; in addition, the chip stacking structure formed by the memory chip realizes a signal rotation transmission effect through a direct connection configuration of a through hole, and also reduces parasitic resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of signal transmission of a chip stacking structure;

[0031] Figure 2 A schematic diagram of signal transmission for another chip stacking structure;

[0032] Figure 3 A schematic diagram of the structure of a memory chip provided by an embodiment of the present disclosure;

[0033] Figure 4 A schematic diagram of the structure of another memory chip provided by an embodiment of the present disclosure;

[0034] Figure 5 A schematic diagram of the structure of another memory chip provided by an embodiment of the present disclosure;

[0035] Figure 6 A schematic diagram of a chip stacking structure provided in an embodiment of the present disclosure;

[0036] Figure 7 A schematic diagram of a first chip stacking structure provided in an embodiment of the present disclosure Figure 1 ;

[0037] Figure 8 A schematic diagram of a first chip stacking structure provided in an embodiment of the present disclosure Figure 2 ;

[0038] Fig. 9 A schematic diagram of a first chip stacking structure provided in an embodiment of the present disclosure Figure 3 ;

[0039] Fig.10 A schematic diagram of a second chip stacking structure provided in an embodiment of the present disclosure Figure 1 ;

[0040] Fig.11 A schematic diagram of a second chip stacking structure provided in an embodiment of the present disclosure Figure 2 ;

[0041] Fig.12 A schematic diagram of a second chip stacking structure provided in an embodiment of the present disclosure Figure 3 ;

[0042] Fig.13A schematic diagram of signal transmission of a first chip stacking structure provided in an embodiment of the present disclosure;

[0043] Fig.14 A schematic diagram of signal transmission of a second chip stacking structure provided in an embodiment of the present disclosure;

[0044] Fig.15 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant application, not to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order for the objects. It is understandable that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that shown or described.

[0046] Dynamic Random Access Memory (DRAM);

[0047] Synchronous Dynamic Random Access Memory (SDRAM);

[0048] Double Data Rate SDRAM (DDR);

[0049] Low Power DDR (LPDDR).

[0050] Before introducing the embodiments of the present disclosure, three directions that may be used to describe the three-dimensional structure of the plane involved in the following embodiments are defined first. Taking the Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis and Z-axis directions (not involved in the embodiments of the present disclosure). The semiconductor chip may include a top surface (active surface) on the front side and a bottom surface (non-active surface) on the back side opposite to the front side; ignoring the flatness of the top surface and the bottom surface, the direction that intersects (for example, perpendicular) with the top surface and the bottom surface of the semiconductor chip is defined as the third direction. On the active surface of the semiconductor chip, two directions that intersect with each other are defined, namely the first direction and the second direction. The active surface direction of the semiconductor chip can be determined based on the first direction and the second direction. In the embodiments of the present disclosure, the first direction and the second direction may be perpendicular to each other. In other embodiments, the first direction and the second direction may not be perpendicular.

[0051] In particular, the illustrations presented in this disclosure are not meant to be actual views of any particular microelectronic device or its components, but are merely idealized representations used to describe illustrative embodiments. Therefore, the drawings are not necessarily to scale.

[0052] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0053] In one embodiment, a memory chip is provided, wherein the memory chip includes a plurality of through holes (or silicon through vias, used to achieve signal transmission between different chips), and all through holes can be located at any position. In particular, every four through holes can be functionally regarded as a through hole group, but the positions of the four through holes are not limited.

[0054] In a specific embodiment, eight of the above-mentioned memory chips and one logic chip are stacked to form a 3D memory device, and the through holes of the eight memory chips are aligned along a third direction, and the nine through holes aligned along the third direction are connected to form an electrical path. Figure 1 , which shows a schematic diagram of signal transmission of a chip stacking structure. Figure 1 As shown, the chip stacking structure includes memory chips 0 to 7 and a logic chip. Figure 1 Only four through holes D0 to D3 are shown for each memory chip, and these four through holes D0 to D3 belong to the same through hole group. At this time, the through holes D0 in the eight memory chips and one logic chip are all aligned to form one electrical path, and the through holes D1 in the eight memory chips and one logic chip are all aligned to form one electrical path... and the remaining through holes are similar.

[0055] At the same time, each memory chip and logic chip is also provided with a plurality of driving circuits ( Figure 1Only one of the driving circuits is shown in a dotted box, and the rest of the driving circuits are not framed), and each through hole is connected to a driving circuit; each memory chip is also provided with a plurality of data selectors (for example Figure 1 Each through-hole group corresponds to a data selector, that is, all through-holes in a through-hole group are connected to the data port of the data selector through their respective driving circuits. In other words, the data selector can select which through-hole transmits the signal to be output to the inside of the memory chip or which through-hole the signal output by the memory chip is output to.

[0056] For the overall storage device, these 8 memory chips are divided into 4 channels (CH0, CH1, CH4, CH5) for management. Memory chip 0 and memory chip 4 belong to channel CH0, memory chip 1 and memory chip 5 belong to channel CH1, memory chip 2 and memory chip 6 belong to channel CH4, and memory chip 3 and memory chip 7 belong to channel CH5. Correspondingly, the input and output signal I / O_CH0 of channel CH0 is transmitted through the electrical path formed by "through hole D0 in the logic chip, through hole D0 in memory chip 0 - through hole D0 in memory chip 1 - through hole D0 in memory chip 2 - through hole D0 in memory chip 3 - through hole D0 in memory chip 4 - through hole D0 in memory chip 5 - through hole D0 in memory chip 6 - through hole D0 in memory chip 7", and the selection signals of the data selector mux0 in memory chip 0 and the data selector mux4 in memory chip 4 are both SEL_C0, that is, the input and output signal I / O_CH0 can enter the memory chip 0 and the memory chip 4 via the aforementioned electrical path; the output process of the signal can be understood similarly.

[0057] From the above, it can be seen that memory chip 0 only needs to obtain signals from through hole D0, memory chip 1 only needs to obtain signals from through hole D1... That is, each memory chip only needs to obtain signals from one through hole in a through hole group. It is worth noting that different memory chips may need to obtain signals from different through holes. However, since all memory chips need to be designed with exactly the same structure during process manufacturing (so as to maximize cost and manpower savings), all through holes in the memory chip need to be designed with corresponding drive structures and data selectors to achieve structural consistency. Furthermore, when using Figure 1 In the chip stacking structure shown, each through hole corresponds to a driving circuit; during the operation of the chip stacking structure, it is necessary to drive all driving circuits in all storage chips in the same channel. The load is large and the parasitic capacitance is large, which seriously affects the performance of the chips, restricts the transmission efficiency and increases the power consumption, and also restricts the number of chips stacked in the three-dimensional device.

[0058] In another embodiment, see Figure 2 , which shows another schematic diagram of signal transmission of a chip stacking structure. In particular, Figure 2 Only some through holes are marked (D0 to D3), and the others are omitted. Figure 4 For example, the through holes aligned along the third direction have the same identifier. Figure 2 As shown, the chip stacking structure also includes 8 memory chips and 1 logic chip aligned along the third direction, but the through-holes in each memory chip are rotationally connected to another through-hole at a different position in another memory chip, and a spiral ascending connection is realized as a whole, that is, the input and output signal I / O_CH0 of channel CH0 is transmitted through "through-hole D0 in the logic chip, through-hole D1 in memory chip 0 - through-hole D2 in memory chip 1 - through-hole D3 in memory chip 2 - through-hole D0 in memory chip 3 - through-hole D1 in memory chip 4 - through-hole D2 in memory chip 5 - through-hole D3 in memory chip 6 - through-hole D0 in memory chip 7", and the other signals are similar.

[0059] In this way, memory chip 0 can obtain input / output signal I / O_CH0 through the output end of through hole D0 in the logic chip, memory chip 1 can obtain input / output signal I / O_CH1 through the input end of through hole D0 in memory chip 0, memory chip 2 can obtain input / output signal I / O_CH4 through the input end of through hole D0 in memory chip 1, memory chip 3 can obtain input / output signal I / O_CH5 through the input end of through hole D0 in memory chip 2... For each memory chip, only one through hole in each through hole group is needed to connect the drive circuit, and no data selector is required, which can reduce the number of devices and thus reduce parasitic capacitance. However, compared to Figure 1 Through-hole direct connection configuration, Figure 2 The process of rotating through-hole connection (for example, through-hole D0 of memory chip 0 is connected to through-hole D1 of memory chip 1) is more complicated. Specifically, Figure 2 A horizontal interconnection structure ( Figure 2 Only one of them is marked with a five-pointed star in the figure), the signal interconnection structure can be a metal interconnection line, a through hole, etc. In order to realize the through hole rotation connection, the input signal must first be transmitted upward from the through hole D0 to the bottom of the through hole D0 of the memory chip 1 (not the through hole D0 connected to the memory chip 1), and then horizontally transmitted from the bottom of the through hole D0 of the memory chip 1 to the through hole D1 of the memory chip 1. Therefore, in the process of transmitting the input signal from the through hole D0 of the logic chip to the through hole D0 of the memory chip 4 in sequence, it also needs to pass through the interconnection structure in each memory chip, and the output signal is similar, which will inevitably lead to an increase in parasitic resistance and increase the complexity of the process.

[0060] In particular, Figure 1 and Figure 2 In the chip stacking structure, all chips are facing up with their active surfaces facing up, that is, different memory chips are stacked back to back, and memory chips and logic chips are also stacked back to back, that is, the inactive surface of the upper chip contacts the active surface of the lower chip.

[0061] In summary, on the one hand, Figure 1 The chip stacking structure has too many drive circuits and data selectors, which leads to large load and parasitic capacitance. Figure 2 The chip stacking structure has a large parasitic resistance due to the rotation configuration; on the other hand, Figure 1-Figure 2 There are certain problems with the stacking structure, and it cannot be directly applied to the face-to-face stacking structure. Specifically, if you want to further realize the face-to-face chip stacking structure, one way is to use two sets of masks to make two different chips as the active side up and the active side down. This method has high process complexity and uncontrollable cost; another way is to make an extra set of through holes and connect the two sets of through holes to the same drive circuit in the memory chip, but this will make the internal wiring of the memory chip complicated, which will not only increase the process complexity, but also increase power consumption.

[0062] Therefore, the embodiments of the present disclosure provide a memory chip and a chip stacking structure, which not only have smaller parasitic capacitance and parasitic resistance, but also can realize face-to-face stacking.

[0063] In another embodiment of the present disclosure, see Figure 3 , which shows a schematic diagram of the structure of a memory chip 10 provided in an embodiment of the present disclosure. The memory chip 10 includes 2×2 areas distributed in an array along its active surface. In the subsequent description, the 2×2 areas are respectively referred to as the first area 11, the second area 12, the third area 13 and the fourth area 14. In addition, for the active surface of the memory chip 10, there are a first axis AA' and a second axis BB', the first axis AA' and the second axis BB' are perpendicular to each other and intersect at the center of the active surface, and the first axis AA' is parallel to one of the sides of the memory chip 10, and the second axis BB' is parallel to the other side of the memory chip 10. In particular, Figure 3 It can be regarded as a schematic cross-section of the memory chip 10 along the active surface.

[0064] Please refer to Figure 3 Each area is surrounded by n through hole groups 20 ( Figure 3Only one through-hole group is shown in each area, and the rest are omitted), and n is a natural number. The n through-hole groups 20 of the first area 11 and the n through-hole groups 20 of the second area 12 are symmetrical about the first axis AA', the n through-hole groups 20 of the third area 13 and the n through-hole groups 20 of the fourth area 14 are symmetrical about the first axis AA', and the n through-hole groups 20 of the first area 11 and the n through-hole groups 20 of the fourth area 14 are symmetrical about the second axis BB'. Here, "the n through-hole groups 20 of the first area 11" specifically refers to "the n through-hole groups 20 running through the first area 11 in the memory chip 10", and the rest of the statements are similar.

[0065] It should be noted that the number and position of the through hole groups 20 in each area can be adjusted according to actual conditions, but the number of through hole groups in each of the four areas must be the same and must follow the above-mentioned symmetrical distribution rule. Figure 4 Three through hole groups 20 are shown for each area. Of course, the number of through hole groups 20 can also be 2, 4, 5, 6, 7, etc. Please adapt to other situations.

[0066] In the embodiment of the present disclosure, the number of through holes in each through hole group 20 is 4 and follows the same distribution rule. The following description will be made by taking one of the through hole groups 20 as an example.

[0067] Please refer to Figure 3 For each through-hole group 20 (for example, the through-hole group 20 in the first region 11), there is a third axis CC' and a fourth axis DD', the third axis CC' and the fourth axis DD' are both located on the active surface, the third axis CC' is parallel to the first axis AA', the fourth axis DD' is parallel to the second axis BB', and the third axis CC' and the fourth axis DD' are perpendicular to each other and intersect at the center of the through-hole group 20.

[0068] Each through hole group 20 includes 2×2 through holes distributed in an array, the first through hole D0 and the second through hole D1 are symmetrical about the third axis CC′, the third through hole D2 and the fourth through hole D3 are symmetrical about the third axis CC′, and the first through hole D0 and the fourth through hole D3 are symmetrical about the fourth axis DD′.

[0069] It should be noted that each through hole group 20 has its own third axis CC' and fourth axis DD'. That is, the first through hole D0 and the second through hole D1 of the same through hole group 20 are symmetrical about the third axis CC' of the through hole group 20, the third through hole D2 and the fourth through hole D3 of the same through hole group 20 are symmetrical about the third axis CC' of the through hole group 20, the first through hole D0 and the fourth through hole D3 of the same through hole group 20 are symmetrical about the fourth axis DD' of the through hole group 20, and the second through hole D1 and the third through hole D2 of the same through hole group 20 are symmetrical about the fourth axis DD' of the through hole group 20.

[0070] It should be noted that the through hole may also be called a through silicon via (TSV), which is specifically a vertical interconnection structure that penetrates a silicon wafer / memory chip.

[0071] It should be noted that the above-mentioned memory chip 10 can be specifically applied to DRAM, SDRAM, DDR, LPDDR, etc.

[0072] It should be noted that any through hole penetrates the memory chip along a direction perpendicular to the active surface (ie, the third direction), and different through holes in the same memory chip 10 are electrically isolated.

[0073] It should be noted that, in the embodiment of the present disclosure, the numbering sequence of the regions and the numbering sequence of the through holes in each through hole group 20 do not constitute any limitation.

[0074] In some embodiments, see Figure 3 or Figure 4 , the n first through holes D0 in the first area 11 and the n second through holes D1 in the second area 12 are symmetrical about the first axis AA'; the n third through holes D2 in the third area 13 and the n fourth through holes D3 in the fourth area 14 are symmetrical about the first axis AA'; the n first through holes D0 in the first area 11 and the n fourth through holes D3 in the fourth area 14 are symmetrical about the second axis BB'; the n second through holes D1 in the second area 12 and the n third through holes D2 in the third area 13 are symmetrical about the second axis BB'.

[0075] In some embodiments, see Figure 3 or Figure 4 , the n second through holes D1 in the first area 11 and the n first through holes D0 in the second area 12 are symmetrical about the first axis AA'; the n fourth through holes D3 in the third area 13 and the n third through holes D2 in the fourth area 14 are symmetrical about the first axis AA'; the n second through holes D1 in the first area 11 and the n third through holes D2 in the fourth area 14 are symmetrical about the second axis BB'; the n first through holes D0 in the second area 12 and the n fourth through holes D3 in the third area 13 are symmetrical about the second axis BB'.

[0076] In some embodiments, see Figure 3 or Figure 4, the n third through holes D2 in the first area 11 and the n fourth through holes D3 in the second area 12 are symmetrical about the first axis AA'; the n first through holes D0 in the third area 13 and the n second through holes D1 in the fourth area 14 are symmetrical about the first axis AA'; the n third through holes D2 in the first area 11 and the n second through holes D1 in the fourth area 14 are symmetrical about the first axis AA'; the n fourth through holes D3 in the second area 12 and the n first through holes D0 in the third area 13 are symmetrical about the second axis BB'.

[0077] In some embodiments, see Figure 3 or Figure 4 , the n fourth through holes D3 in the first area 11 and the n third through holes D2 in the second area 12 are symmetrical about the first axis AA'; the n second through holes D1 in the third area 13 and the n first through holes D0 in the fourth area 14 are symmetrical about the first axis AA'; the n fourth through holes D3 in the first area 11 and the n first through holes D0 in the fourth area 14 are symmetrical about the second axis BB'; the n third through holes D2 in the second area 12 and the n second through holes D1 in the third area 13 are symmetrical about the second axis BB'.

[0078] In some embodiments, see Figure 5 , the memory chip 10 further includes 4n first drive circuits 30; the 4n through holes are connected to the 4n first drive circuits 30 in a one-to-one correspondence, and there is only one through hole in each through hole group 20 connected to the first drive circuit 30. That is, for each through hole group 20, only one through hole transmits a signal that enters / outputs from the chip.

[0079] In some embodiments, the memory chip 10 further includes a positioning structure (not shown in the figure), which is located in a reference area to identify the location of the reference area; wherein the reference area is one of the 2×2 areas (the first area, the second area, the third area or the fourth area).

[0080] It should be noted that during the chip manufacturing process, multiple chips need to be prepared at the same time. In order to distinguish different areas in the chip, a positioning structure needs to be made in the first area of ​​each memory chip (it can also be the second area, the third area or the fourth area, but different chips must select the same area as the reference area) so that during subsequent assembly, the position of the reference area can be identified through the positioning structure, and the position of other areas can be determined in combination with the orientation of the active surface of the chip.

[0081] In addition, the memory chip 10 may also include multiple positioning structures, and different positioning structures are located in different areas to identify the absolute position of the area. For example, the memory chip 10 may also include four positioning structures, and each of the first area to the fourth area is distributed with a positioning structure, and the four positioning structures are different from each other, so as to better identify each area, that is, the first area to the fourth area can all be regarded as reference areas.

[0082] Thus, the embodiment of the present disclosure provides a memory chip 10, wherein the through holes have a special symmetry and can be directly applied to a face-to-face stacking structure without two sets of masks or two sets of through holes; in addition, only one through hole in each through hole group is connected to the driving circuit, and there is no need to set a data selector for through hole selection, which can reduce the number of components, thereby reducing the number of components compared to the conventional memory chip 10. Figure 1 The memory chip reduces parasitic capacitance, which not only saves circuit area but also reduces chip manufacturing cost; the subsequent memory chip 10 can also be compared to Figure 2 The memory chip reduces the parasitic resistance (see the subsequent explanation for the specific reasons).

[0083] In yet another embodiment of the present disclosure, see Figure 6 , which shows a chip stacking structure 40 provided by an embodiment of the present disclosure, the chip stacking structure 40 includes at least one stacking unit, each stacking unit includes a first memory chip 41, a second memory chip 42, a third memory chip 43 and a fourth memory chip 44 stacked in sequence along a third direction, the third direction is perpendicular to the active surface of each memory chip; the first memory chip 41, the second memory chip 42, the third memory chip 43 and the fourth memory chip 44 are all the aforementioned memory chips 10; the first memory chip 41 and the second memory chip 42 are stacked in a face-to-face manner, that is, the top surface (that is, the active surface) of the first memory chip 41 is adjacent to the top surface of the second memory chip 42, the second memory chip 42 and the third memory chip 43 are stacked in a back-to-back manner, that is, the back side (that is, the non-active surface) of the second memory chip 42 is adjacent to the back side of the third memory chip 43, and the third memory chip 43 and the fourth memory chip 44 are stacked in a face-to-face manner, that is, the top surface of the third memory chip 43 is adjacent to the top surface of the fourth memory chip 44.

[0084] In one possibility, for two memory chips connected face to face, the through holes aligned along the third direction are connected through a hybrid bonding structure (Hyperbonding, also known as bonding pillars); for two memory chips connected back to back, the through holes aligned along the third direction are connected through a conductive bump (UBump, also known as micro-bump).

[0085] In another possibility, for two memory chips connected face to face or for two memory chips connected back to back, the through holes aligned along the third direction in both are connected through a hybrid bonding structure. That is, the through holes aligned along the third direction between the two memory chips connected face to face are connected through a hybrid bonding structure, and the through holes aligned along the third direction between the two memory chips connected back to back are also connected through a hybrid bonding structure.

[0086] In another possibility, for two memory chips connected face to face or for two memory chips connected back to back, the through holes aligned along the third direction in both are connected through conductive bumps. That is, the through holes aligned along the third direction between the two memory chips connected face to face are connected through conductive bumps, and the through holes aligned along the third direction between the two memory chips connected back to back are also connected through conductive bumps.

[0087] It should be noted that compared with conductive bumps, face-to-face connection using a hybrid bonding structure can make adjacent memory chips fit more closely, with basically no gaps, thereby greatly reducing the height of the chip stacking structure, which is also one of the advantages of face-to-face stacking. Of course, two memory chips connected back to back can also be connected through a hybrid bonding structure, but its connection performance is weaker than that of face-to-face connection.

[0088] In a specific embodiment, please refer to Figure 7 , the first region 11 in the first storage chip 41a, the second region 12 in the second storage chip 42a, the third region 13 in the third storage chip 43a, and the fourth region 14 in the fourth storage chip 44a are aligned along a third direction;

[0089] The second region 12 in the first memory chip 41a, the first region 11 in the second memory chip 42a, the fourth region 14 in the third memory chip 43a, and the third region 13 in the fourth memory chip 44a are aligned along a third direction;

[0090] The third region 13 in the first memory chip 41a, the fourth region 14 in the second memory chip 42a, the first region 11 in the third memory chip 43a, and the second region 12 in the fourth memory chip 44a are aligned along a third direction;

[0091] The fourth region 14 in the first memory chip 41 a , the third region 13 in the second memory chip 42 a , the second region 12 in the third memory chip 43 a , and the first region 11 in the fourth memory chip 44 a are aligned along the third direction.

[0092] It should be noted that the memory chip can be divided into a high-bit transmission area and a low-bit transmission area. Figure 7The arrows in the figure are all located in the high-order transmission area of ​​the memory chip.

[0093] That is to say, after placing the first memory chip 41a, not only is the second memory chip 42a placed face to face on the first memory chip 41a, but also the positions of the high-order transmission region in the second memory chip 42a and the low-order transmission region in the first memory chip 41a along the third direction are substantially the same; thereafter, the third memory chip 43a is placed back to back on the second memory chip 42a, and at the same time, the positions of the high-order transmission region in the third memory chip 43a and the high-order transmission region in the second memory chip 42a along the third direction are substantially the same, but the positions of the specific devices in the two memory chips do not overlap (specifically present a mirror image relationship); thereafter, the fourth memory chip 44a is placed face to face on the third memory chip 43a, and at the same time, the positions of the high-order transmission region in the fourth memory chip 44a and the low-order transmission region in the third memory chip 43a along the third direction are substantially the same, so that the first memory chip 41a, the second memory chip 42a, the third memory chip 43a and the fourth memory chip 44a form a stacking unit.

[0094] It should also be noted that the chip stacking structure 40 may include a plurality of stacking units. Fig. 9After forming the first stacking unit, the fifth memory chip 45a is placed on the fourth memory chip 44a in a back-to-back manner, and the positions of the high-order transmission region in the fifth memory chip 45a and the high-order transmission region in the fourth memory chip 44a along the third direction are substantially the same, but the positions of the specific devices in the two memory chips do not overlap (specifically present a mirror image relationship); thereafter, the sixth memory chip 46a is placed on the fifth memory chip 45a in a face-to-face manner, and it is also necessary to control the positions of the high-order transmission region in the sixth memory chip 46a and the low-order transmission region in the fifth memory chip 45a along the third direction to be substantially the same; thereafter, the seventh memory chip 47a is placed on the fifth memory chip 45a in a back-to-back manner. The fifth memory chip 45a, the sixth memory chip 46a, the seventh memory chip 47a and the eighth memory chip 48a are placed on the seventh memory chip 47a in a face-to-face manner, and the positions of the high-order transmission region in the seventh memory chip 47a and the low-order transmission region in the seventh memory chip 47a along the third direction are approximately the same, but the positions of the specific devices in the two memory chips do not overlap (specifically present a mirror image relationship); thereafter, the eighth memory chip 48a is placed on the seventh memory chip 47a in a face-to-face manner, and the positions of the high-order transmission region in the eighth memory chip 48a and the low-order transmission region in the seventh memory chip 47a are approximately the same along the third direction, so that the fifth memory chip 45a, the sixth memory chip 46a, the seventh memory chip 47a and the eighth memory chip 48a form a stacking unit. In other words, the fifth memory chip 45a of the second stacking unit can also be regarded as the first memory chip 41a of the first stacking unit, the sixth memory chip 46a of the second stacking unit can also be regarded as the second memory chip 42a of the first stacking unit, the seventh memory chip 47a of the second stacking unit can also be regarded as the third memory chip 43a of the first stacking unit, and the eighth memory chip 48a of the second stacking unit can also be regarded as the fourth memory chip 44a of the first stacking unit. Figure 8 , which shows Figure 7 The active surface of each chip in the stacking unit is shown in the figure. In particular, Figure 7 The four through holes in the Figure 8 It is reflected as four through holes encircled by dotted lines.

[0095] On the one hand, please refer to Figure 8 , each through hole in the first region 11 of the first memory chip 41a has the following position characteristics:

[0096] (1) The n first through holes D0 of the first region 11 in the first storage chip 41a, the n second through holes D1 of the second region 12 in the second storage chip 42a, the n third through holes D2 of the third region 13 in the third storage chip 43a, and the n fourth through holes D3 of the fourth region 14 in the fourth storage chip 44a are aligned along the third direction.

[0097] (2) The n second through holes D1 of the first region 11 in the first storage chip 41a, the n first through holes D0 of the second region 12 in the second storage chip 42a, the n fourth through holes D3 of the third region 13 in the third storage chip 43a, and the n third through holes D2 of the fourth region 14 in the fourth storage chip 44a are aligned along the third direction.

[0098] (3) The n third through holes D2 of the first region 11 in the first storage chip 41a, the n fourth through holes D3 of the second region 12 in the second storage chip 42a, the n first through holes D0 of the third region 13 in the third storage chip 43a, and the n second through holes D1 of the fourth region 14 in the fourth storage chip 44a are aligned along the third direction.

[0099] (4) The n fourth through holes D3 of the first region 11 in the first storage chip 41a, the n third through holes D2 of the second region 12 in the second storage chip 42a, the n second through holes D1 of the third region 13 in the third storage chip 43a, and the n first through holes D0 of the fourth region 14 in the fourth storage chip 44a are aligned along the third direction.

[0100] In particular, Figure 7 and Figure 8 Only one through-hole group in one area is shown as an example, but in fact each area has multiple through-hole groups, and the through-hole groups in different areas have similar alignment characteristics. The alignment of the remaining through-holes is not shown. Please refer to the following text description. Figure 7 and Figure 8 Develop adaptive understanding.

[0101] On the other hand, each through hole in the second region 12 of the first memory chip 41a has the following position characteristics:

[0102] (1) the n first through holes D0 of the second region 12 in the first memory chip 41a, the n second through holes D1 of the first region 11 in the second memory chip 42a, the n third through holes D2 of the fourth region 14 in the third memory chip 43a, and the n fourth through holes D3 of the third region 13 in the fourth memory chip 44a are aligned along the third direction;

[0103] (2) the n second through holes D1 in the second region 12 of the first memory chip 41a, the n first through holes D0 in the first region 11 of the second memory chip 42a, the n fourth through holes D3 in the fourth region 14 of the third memory chip 43a, and the n third through holes D2 in the third region 13 of the fourth memory chip 44a are aligned along the third direction;

[0104] (3) the n third through holes D2 of the second region 12 in the first memory chip 41a, the n fourth through holes D3 of the first region 11 in the second memory chip 42a, the n first through holes D0 of the fourth region 14 in the third memory chip 43a, and the n second through holes D1 of the third region 13 in the fourth memory chip 44a are aligned along the third direction;

[0105] (4) The n fourth through holes D3 of the second region 12 in the first storage chip 41a, the n third through holes D2 of the first region 11 in the second storage chip 42a, the n second through holes D1 of the fourth region 14 in the third storage chip 43a, and the n first through holes D0 of the third region 13 in the fourth storage chip 44a are aligned along the third direction.

[0106] On the other hand, each through hole in the third region 13 of the first memory chip 41a has the following position characteristics:

[0107] (1) The n first through holes D0 of the third region 13 in the first storage chip 41a, the n second through holes D1 of the fourth region 14 in the second storage chip 42a, the n third through holes D2 of the first region 11 in the third storage chip 43a, and the n fourth through holes D3 of the second region 12 in the fourth storage chip 44a are aligned along the third direction.

[0108] (2) The n second through holes D1 in the third region 13 of the first storage chip 41a, the n first through holes D0 in the fourth region 14 of the second storage chip 42a, the n fourth through holes D3 in the first region 11 of the third storage chip 43a, and the n third through holes D2 in the second region 12 of the fourth storage chip 44a are aligned along the third direction.

[0109] (3) The n third through holes D2 of the third region 13 in the first storage chip 41a, the n fourth through holes D3 of the fourth region 14 in the second storage chip 42a, the n first through holes D0 of the first region 11 in the third storage chip 43a, and the n second through holes D1 of the second region 12 in the fourth storage chip 44a are aligned along the third direction.

[0110] (4) The n fourth through holes D3 of the third region 13 in the first storage chip 41a, the n third through holes D2 of the fourth region 14 in the second storage chip 42a, the n second through holes D1 of the first region 11 in the third storage chip 43a, and the n first through holes D0 of the second region 12 in the fourth storage chip 44a are aligned along the third direction.

[0111] On the other hand, each through hole in the fourth region 14 of the first memory chip 41a has the following position characteristics:

[0112] (1) The n first through holes D0 of the fourth region 14 in the first storage chip 41a, the n second through holes D1 of the third region 13 in the second storage chip 42a, the n third through holes D2 of the second region 12 in the third storage chip 43a, and the n fourth through holes D3 of the first region 11 in the fourth storage chip 44a are aligned along the third direction.

[0113] (2) The n second through holes D1 of the fourth region 14 in the first storage chip 41a, the n first through holes D0 of the third region 13 in the second storage chip 42a, the n fourth through holes D3 of the second region 12 in the third storage chip 43a, and the n third through holes D2 of the first region 11 in the fourth storage chip 44a are aligned along the third direction.

[0114] (3) The n third through holes D2 in the fourth region 14 of the first memory chip 41a, the n fourth through holes D3 in the third region 13 of the second memory chip 42a, the n first through holes D0 in the second region 12 of the third memory chip 43a, and the n second through holes D1 in the first region 11 of the fourth memory chip 44a are aligned along the third direction.

[0115] (4) The n fourth through holes D3 of the fourth region 14 in the first storage chip 41a, the n third through holes D2 of the third region 13 in the second storage chip 42a, the n second through holes D1 of the second region 12 in the third storage chip 43a, and the n first through holes D0 of the first region 11 in the fourth storage chip 44a are aligned along the third direction.

[0116] so, Figure 7 to Figure 9 A specific chip stacking method is shown. Figure 10 to Figure 12 This is another specific chip stacking method, which is described in detail as follows.

[0117] Please refer to Fig.10 , the first region 11 in the first storage chip 41b, the fourth region 14 in the second storage chip 42b, the third region 13 in the third storage chip 43b, and the second region 12 in the fourth storage chip 44b are aligned along the third direction;

[0118] The second region 12 in the first memory chip 41 b , the third region 13 in the second memory chip 42 b , the fourth region 14 in the third memory chip 43 b , and the first region 11 in the fourth memory chip 44 b are aligned along the first direction;

[0119] The third area 13 in the first memory chip 41b, the second area 12 in the second memory chip 42b, the first area 11 in the third memory chip 43b, and the fourth area 14 in the fourth memory chip 44b are aligned along the third direction; the fourth area 14 in the first memory chip 41b, the first area 11 in the second memory chip 42b, the second area 12 in the third memory chip 43b, and the third area 13 in the fourth memory chip 44b are aligned along the third direction.

[0120] akin, Fig.10 The arrows in the figure are all located in the high-order transmission area of ​​the memory chip.

[0121] That is to say, the positions of the high-order transmission region in the second memory chip 42b and the high-order transmission region in the first memory chip 41b along the third direction are approximately the same, but the positions of the specific devices in the two memory chips do not overlap (specifically present a mirror image relationship); the positions of the high-order transmission region in the third memory chip 43b and the low-order transmission region in the second memory chip 42b along the third direction are approximately the same; the positions of the high-order transmission region in the fourth memory chip 44b and the high-order transmission region in the third memory chip 43b along the third direction are approximately the same, but the positions of the specific devices in the two memory chips do not overlap (specifically present a mirror image relationship).

[0122] Similarly, the number of stacking units can be multiple. Fig.12 After forming the first stacking unit, the fifth to eighth memory chips 45b to 48b continue to be stacked, and the positions of the high-order transmission region in the fifth memory chip 45b and the low-order transmission region in the fourth memory chip 44b along the third direction are substantially the same; the positions of the high-order transmission region in the sixth memory chip 46b and the high-order transmission region in the fifth memory chip 45b along the third direction are substantially the same, but the positions of the specific devices in these two memory chips do not overlap (specifically present a mirror image relationship); the positions of the high-order transmission region in the seventh memory chip 47b and the low-order transmission region in the sixth memory chip 46b along the third direction are substantially the same; the positions of the high-order transmission region in the eighth memory chip 48b and the high-order transmission region in the seventh memory chip 47b along the third direction are substantially the same, but the positions of the specific devices in these two memory chips do not overlap (specifically present a mirror image relationship).

[0123] See also Fig.11 , which shows Fig.10 The active surface of each chip in the stacking unit is shown in the figure. In particular, Fig.10 The four through holes in the Fig.11 It is reflected as four through holes encircled by dotted lines.

[0124] On the one hand, please refer to Fig.11, each through hole in the first region 11 of the first memory chip 41b has the following position characteristics:

[0125] (1) the n first through holes D0 in the first region 11 of the first memory chip 41b, the n fourth through holes D3 in the fourth region 14 of the second memory chip 42b, the n third through holes D2 in the third region 13 of the third memory chip 43b, and the n second through holes D1 in the second region 12 of the fourth memory chip 44b are aligned along the third direction;

[0126] (2) the n second through holes D1 in the first region 11 of the first memory chip 41b, the n third through holes D2 in the fourth region 14 of the second memory chip 42b, the n fourth through holes D3 in the third region 13 of the third memory chip 43b, and the n first through holes D0 in the second region 12 of the fourth memory chip 44b are aligned along the third direction;

[0127] (3) the n third through holes D2 in the first region 11 of the first memory chip 41b, the n second through holes D1 in the fourth region 14 of the second memory chip 42b, the n first through holes D0 in the third region 13 of the third memory chip 43b, and the n fourth through holes D3 in the second region 12 of the fourth memory chip 44b are aligned along the third direction;

[0128] (4) The n fourth through holes D3 of the first region 11 in the first storage chip 41b, the n first through holes D0 of the fourth region 14 in the second storage chip 42b, the n second through holes D1 of the third region 13 in the third storage chip 43b, and the n third through holes D2 of the second region 12 in the fourth storage chip 44b are aligned along the third direction.

[0129] In particular, Fig.10 and Fig.11 Only one through-hole group in one area is shown as an example, but in fact each area has multiple through-hole groups, and the through-hole groups in different areas have similar alignment characteristics. The alignment of the remaining through-holes is not shown. Please refer to the following text description, Fig.10 and Fig.11 Develop adaptive understanding.

[0130] On the other hand, each through hole in the second region 12 of the first memory chip 41b has the following position characteristics:

[0131] (1) the n first through holes D0 of the second region 12 of the first memory chip 41b, the n fourth through holes D3 of the third region 13 of the second memory chip 42b, the n third through holes D2 of the fourth region 14 of the third memory chip 43b, and the n second through holes D1 of the first region 11 of the fourth memory chip 44b are aligned along the third direction;

[0132] (2) the n second through holes D1 in the second region 12 of the first memory chip 41b, the n third through holes D2 in the third region 13 of the second memory chip 42b, the n fourth through holes D3 in the fourth region 14 of the third memory chip 43b, and the n first through holes D0 in the first region 11 of the fourth memory chip 44b are aligned along the third direction;

[0133] (3) the n third through holes D2 of the second region 12 of the first memory chip 41b, the n second through holes D1 of the third region 13 of the second memory chip 42b, the n first through holes D0 of the fourth region 14 of the third memory chip 43b, and the n fourth through holes D3 of the first region 11 of the fourth memory chip 44b are aligned along the third direction;

[0134] (4) The n fourth through holes D3 of the second region 12 in the first storage chip 41b, the n first through holes D0 of the third region 13 in the second storage chip 42b, the n second through holes D1 of the fourth region 14 in the third storage chip 43b, and the n third through holes D2 of the first region 11 in the fourth storage chip 44b are aligned along the third direction.

[0135] On the other hand, each through hole in the third region 13 of the first memory chip 41b has the following position characteristics:

[0136] (1) the n first through holes D0 of the third region 13 of the first memory chip 41b, the n fourth through holes D3 of the second region 12 of the second memory chip 42b, the n third through holes D2 of the first region 11 of the third memory chip 43b, and the n second through holes D1 of the fourth region 14 of the fourth memory chip 44b are aligned along the third direction;

[0137] (2) the n second through holes D1 in the third region 13 of the first memory chip 41b, the n third through holes D2 in the second region 12 of the second memory chip 42b, the n fourth through holes D3 in the first region 11 of the third memory chip 43b, and the n first through holes D0 in the fourth region 14 of the fourth memory chip 44b are aligned along the third direction;

[0138] (3) the n third through holes D2 of the third region 13 of the first memory chip 41b, the n second through holes D1 of the second region 12 of the second memory chip 42b, the n first through holes D0 of the first region 11 of the third memory chip 43b, and the n fourth through holes D3 of the fourth region 14 of the fourth memory chip 44b are aligned along the third direction;

[0139] (4) The n fourth through holes D3 of the third region 13 in the first storage chip 41b, the n first through holes D0 of the second region 12 in the second storage chip 42b, the n second through holes D1 of the first region 11 in the third storage chip 43b, and the n third through holes D2 of the fourth region 14 in the fourth storage chip 44b are aligned along the third direction.

[0140] On the other hand, each through hole in the fourth region 14 of the first memory chip 41b has the following position characteristics:

[0141] (1) the n first through holes D0 of the fourth region 14 in the first memory chip 41b, the n fourth through holes D3 of the first region 11 in the second memory chip 42b, the n third through holes D2 of the second region 12 in the third memory chip 43b, and the n second through holes D1 of the third region 13 in the fourth memory chip 44b are aligned along the third direction;

[0142] (2) the n second through holes D1 of the fourth region 14 of the first memory chip 41b, the n third through holes D2 of the first region 11 of the second memory chip 42b, the n fourth through holes D3 of the second region 12 of the third memory chip 43b, and the n first through holes D0 of the third region 13 of the fourth memory chip 44b are aligned along the third direction;

[0143] (3) the n third through holes D2 in the fourth region 14 of the first memory chip 41b, the n second through holes D2 in the first region 11 of the second memory chip 42b, the n first through holes D0 in the second region 12 of the third memory chip 43b, and the n fourth through holes D3 in the third region 13 of the fourth memory chip 44b are aligned along the third direction;

[0144] (4) The n fourth through holes D3 of the fourth region 14 in the first storage chip 41b, the n first through holes D0 of the first region 11 in the second storage chip 42b, the n second through holes D1 of the second region 12 in the third storage chip 43b, and the n third through holes D2 of the third region 13 in the fourth storage chip 44b are aligned along the third direction.

[0145] so, Figure 10 to Figure 12 The chip stacking structure also meets the usage requirements.

[0146] In some embodiments, see Fig.13 and Fig.14 , which shows a schematic diagram of signal transmission of the chip stacking structure 40. In particular, Fig.13 It is for Figure 7 The chip stacking structure shown is shown, Fig.14 It is for Fig.10In particular, in the following description, the first memory chip 41 may refer to the first memory chip 41a or the first memory chip 41b, and other memory chips are similar.

[0147] like Fig.13 or Fig.14 As shown, each memory chip further includes 4n first drive circuits 30 ( Fig.13 Only one is shown for each memory chip); in each memory chip, 4n first driving circuits 30 are connected to the first ends of 4n first through holes D0 in a one-to-one correspondence; wherein the first ends are located at the active surface of the memory chip.

[0148] That is to say, no matter it is the first storage chip 41, the second storage chip 42, the third storage chip 43 or the fourth storage chip 44, the first driving circuit 30 therein is connected to the first through hole D0, that is, the first storage chip 41, the second storage chip 42, the third storage chip 43 or the fourth storage chip 44 adopts exactly the same structure.

[0149] In some embodiments, see Fig. 9 as well as Fig.12 The chip stacking structure 40 further includes a logic chip 50; the first stacking unit is sequentially stacked on the logic chip 50 along the third direction, and the remaining stacking units are sequentially stacked on the previous stacking unit along the third direction. Here, the first memory chip and the logic chip 50 are stacked back to face, or the first memory chip and the logic chip 50 are stacked back to back.

[0150] See also Fig.13 and Fig.14 , the logic chip 50 includes 16n fifth through holes 502 and 16n second driving circuits 501 .

[0151] For the 16n fifth through holes 502, 4n fifth through holes 502 are aligned with 4n fifth through holes D0 in the first memory chip 41 in a one-to-one correspondence along the third direction, 4n fifth through holes 502 are aligned with 4n second through holes D1 in the first memory chip 41 in a one-to-one correspondence along the third direction, 4n fifth through holes 502 are aligned with 4n third through holes D2 in the first memory chip 41 in a one-to-one correspondence along the third direction, and 4n fifth through holes 502 are aligned with 4n fourth through holes D3 in the first memory chip 41 in a one-to-one correspondence along the third direction;

[0152] The 16n second driving circuits 501 are connected to the first ends of the 16n fifth through holes 502 in a one-to-one correspondence, and the first ends are located on the active surface of the logic chip 50 .

[0153] That is, the arrangement positions of the through holes in the logic chip 50 and the aforementioned memory chip 10 are the same, but each through hole in the logic chip 50 is connected to a driving circuit.

[0154] It should be noted that Fig.13 and Fig.14 This is only an abstract circuit schematic diagram, in which the driving circuit is simply placed next to the through-hole connected to it, without drawing a specific connection relationship. Please combine it with the text description for adaptive understanding.

[0155] The chip stacking structure 40 further includes 16n electrical paths, and one fifth through hole, at least one first through hole D0, at least one second through hole D1, at least one third through hole D2 and at least one fourth through hole D3 aligned along the third direction are connected to form one electrical path.

[0156] It should be noted that if the chip stacking structure 40 includes m stacking units, then one fifth through hole 502, m first through holes D0, m second through holes D1, m third through holes D2 and m fourth through holes D3 aligned along the third direction are connected to form one electrical path, where m is a positive integer.

[0157] So, please refer to Fig.13 or Fig.14 , the input and output signal I / O_CH0 of channel CH0 is transmitted through "through hole D0 in logic chip, through hole D0 in memory chip 0 - through hole D1 in memory chip 1 - through hole D2 in memory chip 2 - through hole D3 in memory chip 3 - through hole D0 in memory chip 4 - through hole D1 in memory chip 5 - through hole D2 in memory chip 6 - through hole D3 in memory chip 7", and the rest of the signals are similar. At this time, the first memory chip 41 can obtain the input and output signal I / O_CH0 through the input end of its own through hole D0, the second memory chip 42 can obtain the input and output signal I / O_CH1 through the input end of its own through hole D0, the third memory chip 43 can obtain the input and output signal I / O_CH4 through the input end of its own through hole D0, and the fourth memory chip 44 can obtain the input and output signal I / O_CH5 through the input end of its own through hole D0... In other words, see Fig.13 or Fig.14 For the chip stacking structure 40, from a physical point of view, the through holes therein are still in a direct connection configuration, but from the absolute position of the through holes on the active surface, the through holes therein can be regarded as a functional rotation configuration, that is, a similar rotation configuration is realized through the physical direct connection configuration. Figure 2 The signal transmission effect (i.e. the rotation transmission effect of through hole D0-through hole D1-through hole D2-through hole D3...). In simple terms, Figure 2The chip stacking structure in the chip stacking process requires a physical spiral structure, in which there must be a lateral interconnection structure. Fig.13 or Fig.14 The chip stacking structure is physically a direct-connection structure, which does not require a lateral interconnection structure. The parasitic resistance is greatly reduced, and the transmission speed and transmission performance are greatly improved.

[0158] In one embodiment, the general preparation process of the chip stacking structure 40 is as follows:

[0159] S801: providing a wafer;

[0160] S802: planning a plurality of chip regions in the wafer, and forming a main structure of the aforementioned memory chip in each chip region;

[0161] S803: cutting the wafer to obtain a plurality of memory chips;

[0162] S804: align 4m memory chips and 1 logic chip along the third direction (please refer to the above alignment rules), and form a conductive bump and / or a hybrid connection structure between the two chips to form a chip stacking structure 40.

[0163] In another embodiment, the general preparation process of the chip stacking structure 40 is as follows:

[0164] S901: Provide 4m wafers;

[0165] S902: planning a plurality of chip regions in each wafer, and forming a main structure of the aforementioned memory chip in each chip region;

[0166] S903: aligning the 4m wafers along a third direction (please refer to the above for the alignment rules); and forming a conductive bump and / or a hybrid connection structure between two adjacent wafers.

[0167] It should be noted that, for two adjacent wafers, there are multiple pairs of memory chips aligned along the third direction, and a conductive bump and / or a hybrid connection structure needs to be formed for each pair of memory chips aligned along the third direction.

[0168] S904: Cutting the 4m wafers to obtain multiple pre-stacked structures;

[0169] S905 : Assembling the plurality of pre-stacked structures and the plurality of logic chips accordingly to form a plurality of chip stacked structures 40 .

[0170] In yet another embodiment, the general preparation process of the chip stacking structure 40 is as follows:

[0171] S1001: Provide 4m+1 wafers;

[0172] S1002: planning a plurality of chip regions in each wafer, and forming the main structure of the aforementioned memory chip in each chip region in 4m wafers; and forming the main structure of the aforementioned logic chip in each chip region in 1 wafer;

[0173] S1003: aligning the 4m+1 wafers along a third direction (please refer to the above for the alignment rules); and forming a conductive bump and / or a hybrid connection structure between two adjacent wafers.

[0174] It should be noted that, for two adjacent wafers, there are multiple pairs of memory chips aligned along the third direction, and a conductive bump and / or a hybrid connection structure needs to be formed for each pair of memory chips aligned along the third direction.

[0175] S1004 : Cut 4m+1 wafers to obtain a plurality of chip stacking structures 40 .

[0176] From the above, it can be seen that the memory chip provided by the embodiment of the present disclosure not only reduces the number of drive circuits and data selectors, thereby reducing parasitic capacitance; in addition, the chip stacking structure formed by the memory chip realizes the signal rotation transmission effect through the direct connection configuration of the through hole, and also reduces the parasitic resistance. Through simulation experiments, it is found that the chip stacking structure provided by this embodiment of the present disclosure has a parasitic capacitance compared to Figure 2 The structure shown has approximately 7% lower parasitic capacitance compared to Figure 2 The structure shown is approximately 95% lower, allowing for more chips to be stacked with better signal transmission quality.

[0177] In yet another embodiment of the present disclosure, see Fig.15 , which shows a schematic diagram of the structure of a memory 70 provided by an embodiment of the present disclosure. Fig.15 As shown, the memory 70 at least includes the aforementioned chip stacking structure 40 .

[0178] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such a process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes one..." does not exclude the presence of other identical elements in the process, method, article or device including the element. The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory chip, characterized in that: The memory chip includes 2×2 areas distributed in an array along its active surface, each of the areas is penetrated by n through-hole groups, where n is a natural number; The n through-hole groups in the first region and the n through-hole groups in the second region are symmetrical about a first axis, the n through-hole groups in the third region and the n through-hole groups in the fourth region are symmetrical about the first axis, and the n through-hole groups in the first region and the n through-hole groups in the fourth region are symmetrical about a second axis; wherein the first axis and the second axis are both located on the active surface, the first axis and the second axis are perpendicular to each other and intersect at the center of the active surface; For each of the through hole groups, it includes 2×2 through holes distributed in an array, the first through hole and the second through hole are symmetrical about the third axis, the third through hole and the fourth through hole are symmetrical about the third axis, and the first through hole and the fourth through hole are symmetrical about the fourth axis; wherein the third axis and the fourth axis are both located on the active surface, and the third axis and the fourth axis are both located on the active surface, and the third axis and the fourth axis are perpendicular to each other and intersect at the center of the through hole group; The first axis and the third axis of each through-hole group are parallel to the first side of the memory chip, and the second axis and the fourth axis of each through-hole group are parallel to the second side of the memory chip.

2. The memory chip according to claim 1, characterized in that: The n first through holes in the first region and the n second through holes in the second region are symmetrical about the first axis; The n third through holes in the third region and the n fourth through holes in the fourth region are symmetrical about the first axis; The n first through holes in the first region and the n fourth through holes in the fourth region are symmetrical about the second axis.

3. The memory chip according to claim 2, characterized in that: The n second through holes in the first region and the n first through holes in the second region are symmetrical about the first axis; The n fourth through holes in the third region and the n third through holes in the fourth region are symmetrical about the first axis; The n second through holes in the first region and the n third through holes in the fourth region are symmetrical about the second axis.

4. The memory chip according to claim 3, characterized in that: The n third through holes in the first region and the n fourth through holes in the second region are symmetrical about the first axis; The n first through holes in the third region and the n second through holes in the fourth region are symmetrical about the first axis; The n third through holes in the first region and the n second through holes in the fourth region are symmetrical about the first axis.

5. The memory chip according to claim 4, characterized in that: The n fourth through holes in the first region and the n third through holes in the second region are symmetrical about the first axis; The n second through holes in the third region and the n first through holes in the fourth region are symmetrical about the first axis; The n fourth through holes in the first region and the n first through holes in the fourth region are symmetrical about the second axis.

6. The memory chip according to any one of claims 1 to 5, characterized in that: Any of the through holes penetrates the memory chip in a direction perpendicular to the active surface, and different through holes in the same memory chip are electrically isolated.

7. The memory chip according to any one of claims 1 to 5, characterized in that: The memory chip further includes 4n first driving circuits; The 4n through holes are connected to the 4n first driving circuits in a one-to-one correspondence, and there is only one through hole in each through hole group connected to the first driving circuit.

8. The memory chip according to any one of claims 1 to 5, characterized in that: The memory chip also includes a positioning structure; The positioning structure is located in a reference area to identify the location of the reference area; wherein the reference area is one of the 2×2 areas.

9. A chip stacking structure, characterized in that: The chip stacking structure includes at least one stacking unit, each of the stacking units includes a first memory chip, a second memory chip, a third memory chip and a fourth memory chip stacked in sequence along a third direction, wherein the third direction is perpendicular to an active surface of each of the memory chips; the first memory chip, the second memory chip, the third memory chip and the fourth memory chip are all memory chips according to any one of claims 1 to 7; The first memory chip and the second memory chip are stacked in a face-to-face manner, the second memory chip and the third memory chip are stacked in a back-to-back manner, and the third memory chip and the fourth memory chip are stacked in a face-to-face manner.

10. The chip stacking structure according to claim 9, characterized in that: The first region in the first memory chip, the second region in the second memory chip, the third region in the third memory chip, and the fourth region in the fourth memory chip are aligned along a third direction; The second area in the first memory chip, the first area in the second memory chip, the fourth area in the third memory chip, and the third area in the fourth memory chip are aligned along a third direction; The third area in the first memory chip, the fourth area in the second memory chip, the first area in the third memory chip, and the second area in the fourth memory chip are aligned along a third direction; The fourth region in the first memory chip, the third region in the second memory chip, the second region in the third memory chip, and the first region in the fourth memory chip are aligned along a third direction.

11. The chip stacking structure according to claim 10, characterized in that: The n first through holes in the first area of ​​the first memory chip, the n second through holes in the second area of ​​the second memory chip, the n third through holes in the third area of ​​the third memory chip, and the n fourth through holes in the fourth area of ​​the fourth memory chip are aligned along a third direction; The n second through holes in the first area of ​​the first memory chip, the n first through holes in the second area of ​​the second memory chip, the n fourth through holes in the third area of ​​the third memory chip, and the n third through holes in the fourth area of ​​the fourth memory chip are aligned along a third direction; The n third through holes in the first area of ​​the first memory chip, the n fourth through holes in the second area of ​​the second memory chip, the n first through holes in the third area of ​​the third memory chip, and the n second through holes in the fourth area of ​​the fourth memory chip are aligned along a third direction; The n fourth through holes in the first area of ​​the first memory chip, the n third through holes in the second area of ​​the second memory chip, the n second through holes in the third area of ​​the third memory chip, and the n first through holes in the fourth area of ​​the fourth memory chip are aligned along a third direction.

12. The chip stacking structure according to claim 11, characterized in that: The n first through holes in the second area of ​​the first memory chip, the n second through holes in the first area of ​​the second memory chip, the n third through holes in the fourth area of ​​the third memory chip, and the n fourth through holes in the third area of ​​the fourth memory chip are aligned along a third direction; The n second through holes in the second area of ​​the first memory chip, the n first through holes in the first area of ​​the second memory chip, the n fourth through holes in the fourth area of ​​the third memory chip, and the n third through holes in the third area of ​​the fourth memory chip are aligned along a third direction; The n third through holes in the second area of ​​the first memory chip, the n fourth through holes in the first area of ​​the second memory chip, the n first through holes in the fourth area of ​​the third memory chip, and the n second through holes in the third area of ​​the fourth memory chip are aligned along a third direction; The n fourth through holes in the second area of ​​the first memory chip, the n third through holes in the first area of ​​the second memory chip, the n second through holes in the fourth area of ​​the third memory chip, and the n first through holes in the third area of ​​the fourth memory chip are aligned along a third direction.

13. The chip stacking structure according to claim 12, characterized in that: The n first through holes in the third region of the first memory chip, the n second through holes in the fourth region of the second memory chip, the n third through holes in the first region of the third memory chip, and the n fourth through holes in the second region of the fourth memory chip are aligned along a third direction; The n second through holes in the third region of the first memory chip, the n first through holes in the fourth region of the second memory chip, the n fourth through holes in the first region of the third memory chip, and the n third through holes in the second region of the fourth memory chip are aligned along a third direction; The n third through holes in the third region of the first memory chip, the n fourth through holes in the fourth region of the second memory chip, the n first through holes in the first region of the third memory chip, and the n second through holes in the second region of the fourth memory chip are aligned along a third direction; The n fourth through holes in the third area of ​​the first memory chip, the n third through holes in the fourth area of ​​the second memory chip, the n second through holes in the first area of ​​the third memory chip, and the n first through holes in the second area of ​​the fourth memory chip are aligned along a third direction.

14. The chip stacking structure according to claim 13, characterized in that: The n first through holes in the fourth region of the first memory chip, the n second through holes in the third region of the second memory chip, the n third through holes in the second region of the third memory chip, and the n fourth through holes in the first region of the fourth memory chip are aligned along a third direction; The n second through holes in the fourth region of the first memory chip, the n first through holes in the third region of the second memory chip, the n fourth through holes in the second region of the third memory chip, and the n third through holes in the first region of the fourth memory chip are aligned along a third direction; The n third through holes in the fourth region of the first memory chip, the n fourth through holes in the third region of the second memory chip, the n first through holes in the second region of the third memory chip, and the n second through holes in the first region of the fourth memory chip are aligned along a third direction; The n fourth through holes in the fourth area of ​​the first memory chip, the n third through holes in the third area of ​​the second memory chip, the n second through holes in the second area of ​​the third memory chip, and the n first through holes in the first area of ​​the fourth memory chip are aligned along a third direction.

15. The chip stacking structure according to claim 9, characterized in that: The first region in the first memory chip, the fourth region in the second memory chip, the third region in the third memory chip, and the second region in the fourth memory chip are aligned along a third direction; The second area in the first memory chip, the third area in the second memory chip, the fourth area in the third memory chip, and the first area in the fourth memory chip are aligned along a first direction; The third region in the first memory chip, the second region in the second memory chip, the first region in the third memory chip, and the fourth region in the fourth memory chip are aligned along a third direction; The fourth region in the first memory chip, the first region in the second memory chip, the second region in the third memory chip, and the third region in the fourth memory chip are aligned along a third direction.

16. The chip stacking structure according to claim 15, characterized in that: The n first through holes in the first area of ​​the first memory chip, the n fourth through holes in the fourth area of ​​the second memory chip, the n third through holes in the third area of ​​the third memory chip, and the n second through holes in the second area of ​​the fourth memory chip are aligned along a third direction; The n second through holes in the first area of ​​the first memory chip, the n third through holes in the fourth area of ​​the second memory chip, the n fourth through holes in the third area of ​​the third memory chip, and the n first through holes in the second area of ​​the fourth memory chip are aligned along a third direction; The n third through holes in the first region of the first memory chip, the n second through holes in the fourth region of the second memory chip, the n first through holes in the third region of the third memory chip, and the n fourth through holes in the second region of the fourth memory chip are aligned along a third direction; The n fourth through holes in the first area of ​​the first memory chip, the n first through holes in the fourth area of ​​the second memory chip, the n second through holes in the third area of ​​the third memory chip, and the n third through holes in the second area of ​​the fourth memory chip are aligned along a third direction.

17. The chip stacking structure according to claim 16, characterized in that: The n first through holes in the second area of ​​the first memory chip, the n fourth through holes in the third area of ​​the second memory chip, the n third through holes in the fourth area of ​​the third memory chip, and the n second through holes in the first area of ​​the fourth memory chip are aligned along a third direction; The n second through holes in the second area of ​​the first memory chip, the n third through holes in the third area of ​​the second memory chip, the n fourth through holes in the fourth area of ​​the third memory chip, and the n first through holes in the first area of ​​the fourth memory chip are aligned along a third direction; The n third through holes in the second area of ​​the first memory chip, the n second through holes in the third area of ​​the second memory chip, the n first through holes in the fourth area of ​​the third memory chip, and the n fourth through holes in the first area of ​​the fourth memory chip are aligned along a third direction; The n fourth through holes in the second area of ​​the first memory chip, the n first through holes in the third area of ​​the second memory chip, the n second through holes in the fourth area of ​​the third memory chip, and the n third through holes in the first area of ​​the fourth memory chip are aligned along a third direction.

18. The chip stacking structure according to claim 17, characterized in that: The n first through holes in the third region of the first memory chip, the n fourth through holes in the second region of the second memory chip, the n third through holes in the first region of the third memory chip, and the n second through holes in the fourth region of the fourth memory chip are aligned along a third direction; The n second through holes in the third region of the first memory chip, the n third through holes in the second region of the second memory chip, the n fourth through holes in the first region of the third memory chip, and the n first through holes in the fourth region of the fourth memory chip are aligned along a third direction; The n third through holes in the third region of the first memory chip, the n second through holes in the second region of the second memory chip, the n first through holes in the first region of the third memory chip, and the n fourth through holes in the fourth region of the fourth memory chip are aligned along a third direction; The n fourth through holes in the third area of ​​the first memory chip, the n first through holes in the second area of ​​the second memory chip, the n second through holes in the first area of ​​the third memory chip, and the n third through holes in the fourth area of ​​the fourth memory chip are aligned along a third direction.

19. The chip stacking structure according to claim 18, characterized in that: The n first through holes in the fourth region of the first memory chip, the n fourth through holes in the first region of the second memory chip, the n third through holes in the second region of the third memory chip, and the n second through holes in the third region of the fourth memory chip are aligned along a third direction; The n second through holes in the fourth region of the first memory chip, the n third through holes in the first region of the second memory chip, the n fourth through holes in the second region of the third memory chip, and the n first through holes in the third region of the fourth memory chip are aligned along a third direction; The n third through holes in the fourth region of the first memory chip, the n second through holes in the first region of the second memory chip, the n first through holes in the second region of the third memory chip, and the n fourth through holes in the third region of the fourth memory chip are aligned along a third direction; The n fourth through holes in the fourth area of ​​the first memory chip, the n first through holes in the first area of ​​the second memory chip, the n second through holes in the second area of ​​the third memory chip, and the n third through holes in the third area of ​​the fourth memory chip are aligned along a third direction.

20. The chip stacking structure according to any one of claims 9 to 19, characterized in that: For two memory chips connected face to face, the through holes aligned along the third direction are connected through a hybrid bonding structure; for two memory chips connected back to back, the through holes aligned along the third direction are connected through a conductive bump; or, For two memory chips connected face to face or for two memory chips connected back to back, through holes aligned along the third direction in both are connected by a hybrid bonding structure; or, For two memory chips connected face to face or for two memory chips connected back to back, through holes aligned along the third direction in both memory chips are connected via conductive bumps.

21. The chip stacking structure according to claim 20, characterized in that: Each of the memory chips further includes 4n first driving circuits; In each of the memory chips, 4n first driving circuits are connected to the first ends of 4n first through holes in a one-to-one correspondence; wherein the first ends are located on the active surface of the memory chip.

22. The chip stacking structure according to claim 21, characterized in that: The chip stacking structure further includes a logic chip; the first stacking unit is stacked on the logic chip along a third direction, and the remaining stacking units are stacked on the previous stacking unit in sequence along the third direction; The logic chip includes 16n fifth through holes and 16n second driving circuits, wherein 4n fifth through holes are aligned with 4n first through holes in the first storage chip in a one-to-one correspondence along a third direction, wherein 4n fifth through holes are aligned with 4n second through holes in the first storage chip in a one-to-one correspondence along the third direction, wherein 4n fifth through holes are aligned with 4n third through holes in the first storage chip in a one-to-one correspondence along the third direction, wherein 4n fifth through holes are aligned with 4n fourth through holes in the first storage chip in a one-to-one correspondence along the third direction; The 16n second driving circuits are connected to the first ends of the 16n fifth through holes in a one-to-one correspondence, and the first ends are located on the active surface of the logic chip.

23. The chip stacking structure according to claim 22, characterized in that: The chip stacking structure also includes 16n electrical paths; If the chip stacking structure includes m stacking units, one fifth through hole, m first through holes, m second through holes, m third through holes and m fourth through holes aligned along the third direction are connected to form one electrical path, where m is a positive integer.

24. A memory, characterized in that: Comprising a chip stacking structure as described in any one of claims 9-23.

Images