Semiconductor packaging structure and semiconductor packaging method

Abstract

The invention provides a semiconductor packaging structure and a semiconductor packaging method, and relates to the technical field of semiconductors. The semiconductor package structure includes: a package substrate; the random access memory chip is bonded with the first connecting part on the packaging substrate; the packaging layer is located on the packaging substrate and wraps the random access memory chip; the rewiring layer is located on the packaging layer; the second conductive wire is at least partially positioned in the packaging layer and is connected with a second connecting part on the packaging substrate and the bottom surface of the rewiring layer; the flash memory chip is positioned on the rewiring layer and is bonded with the top surface of the rewiring layer; the rewiring layer comprises a signal circuit and a reference circuit, the signal circuit is used for performing signal transmission between the flash memory chip and the packaging substrate, and the reference circuit is used for providing a reference plane for signal transmission. The problems of warping, layering and the like of the semiconductor device can be solved, and the signal integrity and the power supply integrity are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure and a semiconductor packaging method. Background Art

[0002] In the semiconductor packaging process, an interposer is usually used as a platform for bonding multiple chips to a packaging substrate, so that the multiple chips are packaged into one device.

[0003] However, there may be a mismatch in thermal expansion coefficients between the interposer and the packaging material. As the semiconductor device generates heat during use, device warping, delamination and other undesirable phenomena are prone to occur, affecting the normal use of the device. Summary of the invention

[0004] The present disclosure provides a semiconductor packaging structure and a semiconductor packaging method to at least to some extent solve the problems of warping, delamination and the like of semiconductor devices.

[0005] According to a first aspect of the present disclosure, there is provided a semiconductor packaging structure, comprising: a packaging substrate; a random access memory chip, bonded to a first connection portion on the packaging substrate; a packaging layer, located on the packaging substrate and covering the random access memory chip; a redistribution layer, located on the packaging layer; a second conductive line, at least partially located within the packaging layer, connecting the second connection portion on the packaging substrate and a bottom surface of the redistribution layer; a flash memory chip, located on the redistribution layer and bonded to a top surface of the redistribution layer; the redistribution layer comprises a signal line and a reference line, the signal line being used for signal transmission between the flash memory chip and the packaging substrate, and the reference line being used for providing a reference plane for signal transmission.

[0006] Optionally, the second connection portion is a pad on the packaging substrate, and the second conductive wire is a bonding wire connecting the second connection portion and a pad on the bottom surface of the redistribution layer.

[0007] Optionally, the ratio of a projection size of the second conductive line on the plane of the packaging substrate to a vertical size of the second conductive line is smaller than a preset ratio value.

[0008] Optionally, the second conductive lines are distributed in multiple directions of the random access memory chip.

[0009] Optionally, the enclosing box of the projection of the connection point between the signal line and the bottom surface of the redistribution layer on the reference plane is located within the enclosing box of the projection of the connection point between the reference line and the bottom surface of the redistribution layer on the reference plane; the reference plane is parallel to the top surface of the packaging substrate.

[0010] Optionally, the reference circuit includes a power circuit and a ground circuit; the bounding box of the projection of the connection point between the signal circuit and the bottom surface of the redistribution layer on the reference plane is located within the bounding box of the projection of the connection point between the ground circuit and the bottom surface of the redistribution layer on the reference plane; the bounding box of the projection of the connection point between the ground circuit and the bottom surface of the redistribution layer on the reference plane is located within the bounding box of the projection of the connection point between the power circuit and the bottom surface of the redistribution layer on the reference plane.

[0011] Optionally, the rewiring layer is a stacked structure formed by a signal layer, a power layer and a ground layer; the signal layer is located between the power layer and the ground layer; the signal line includes a horizontal signal wiring parallel to a reference plane and a vertical signal wiring perpendicular to the reference plane, and the horizontal signal wiring is located in the signal layer; the reference line includes a power line and a ground line; the power line includes a horizontal power wiring parallel to the reference plane and a vertical power wiring perpendicular to the reference plane, and the horizontal power wiring is located in the power layer; the ground line includes a horizontal ground wiring parallel to the reference plane and a vertical ground wiring perpendicular to the reference plane, and the horizontal ground wiring is located in the ground layer; the reference plane is parallel to the top surface of the packaging substrate.

[0012] Optionally, a diameter of the second conductive wire connected to the power line is greater than a diameter of the second conductive wire connected to the ground line.

[0013] Optionally, the second conductive line connected to the ground line is arranged at the periphery of the second conductive line connected to the signal line, and the second conductive line connected to the power signal is arranged at the periphery of the second conductive line connected to the ground signal.

[0014] According to a second aspect of the present disclosure, a semiconductor packaging method is provided, comprising: providing a packaging substrate, a random access memory chip and a flash memory chip to be packaged; bonding the random access memory chip to a first connection portion on the packaging substrate; forming a second conductive wire, the second conductive wire connecting to a second connection portion on the packaging substrate and extending upward; forming a packaging layer on the packaging substrate, covering the random access memory chip and at least partially covering the second conductive wire; forming a redistribution layer on the packaging layer, the second conductive wire connecting to a bottom surface of the redistribution layer; the redistribution layer comprising a signal line and a reference line, the signal line being used for signal transmission between the flash memory chip and the packaging substrate, the reference line being used for providing a reference plane for signal transmission; bonding the flash memory chip to a top surface of the redistribution layer.

[0015] The technical solution disclosed in this disclosure has the following beneficial effects:

[0016] First, instead of using an interposer, a redistribution layer is used to achieve the bonding of the flash memory chip to the package substrate. The redistribution layer is located above the package layer rather than in the package layer. Even if there is a mismatch in the thermal expansion coefficients between the redistribution layer and the package layer, when the semiconductor device is heated, problems such as warping and delamination are not likely to occur. Second, a suitable insulating medium can be used as a carrier in the redistribution layer. Compared with the interposer, there is a greater choice of media to match the thermal expansion coefficient of the package layer, thereby further improving problems such as warping and delamination, and ensuring the performance of the semiconductor device. Third, the line between the flash memory chip and the package substrate includes a second conductive line, a wiring in the redistribution layer, and a bonding portion between the flash memory chip and the redistribution layer. Compared with the line of the existing package structure, the length of the second conductive line is shorter than the wiring from the interposer to the package substrate, and the wiring in the redistribution layer is shorter than the wiring in the interposer. Therefore, this solution can shorten the line length between the flash memory chip and the package substrate, and improve signal integrity and power integrity. Fourthly, setting both the signal line and the reference line in the redistribution layer is conducive to simplifying the packaging structure. The reference line provides a reference plane for signal transmission. It is located in the redistribution layer and can play a good shielding role to avoid electromagnetic coupling between the redistribution layer and external interference sources. Under the action of the reference plane, the signal line can be regarded as a microstrip line with better signal transmission characteristics, which can also improve signal integrity. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a semiconductor packaging structure is shown.

[0018] Figure 2 A schematic diagram of a lead is shown.

[0019] Figure 3 A schematic diagram of a semiconductor package structure in this exemplary embodiment is shown.

[0020] Figure 4A A schematic diagram of a projection and its bounding box in this exemplary embodiment is shown.

[0021] Figure 4B A schematic diagram of another projection and its bounding box in this exemplary embodiment is shown.

[0022] Figure 5 A top view of a redistribution layer in this exemplary embodiment is shown.

[0023] Figure 6 A schematic diagram showing another semiconductor package structure in this exemplary embodiment.

[0024] Fig. 7A A comparison graph of insertion loss values ​​is shown.

[0025] Figure 7B A comparison graph of return loss values ​​is shown.

[0026] Figure 7C A comparison graph of impedance is shown.

[0027] Figure 8 A flowchart of a semiconductor packaging method in this exemplary embodiment is shown.

[0028] The figure markings are as follows: 101, packaging substrate; 1011, first connection part; 1012, second connection part; 102, random access memory chip; 1021, random access memory chip particle; 1022, chip adhesive film; 103, packaging layer; 104, redistribution layer; 1041; insulating layer; 1042, signal line; 1043, reference line; 1044; power line; 1045; ground line; 1046, power layer; 1047, signal layer; 1048, ground layer; 105, second conductive line; 106, flash memory chip; 107, first conductive line. DETAILED DESCRIPTION

[0029] Exemplary embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings.

[0030] The accompanying drawings are schematic diagrams of the present disclosure and are not necessarily drawn to scale. The technical solution of the present disclosure can be implemented in various forms and should not be construed as being limited to the examples set forth herein. The features, structures or characteristics described in the present disclosure may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full description of the embodiments of the present disclosure. However, it will be understood by those skilled in the art that one or more specific details may be omitted when implementing the technical solution of the present disclosure, or one or more specific details may be replaced by other methods, components, structures, etc.

[0031] Figure 1 A schematic diagram of a semiconductor packaging structure is shown. Among them, the interposer is the medium for interconnecting the UFS (Universal Flash Storage) chip and the DRAM (Dynamic Random Access Memory) chip. The UFS chip is bonded to the interposer and then wire-bonded to the packaging substrate. The DRAM chip is wire-bonded to the packaging substrate. The packaging layer covers the DRAM chip and the interposer to protect it.

[0032] The inventors have found that the encapsulation layer is generally made of injection molding materials, such as EMC (Epoxy Molding Compound). The interposer and the encapsulation layer usually have a mismatch in the coefficient of thermal expansion (CTE), that is, the difference in the coefficient of thermal expansion between the two is too large. In this way, when the semiconductor device is heated, the expansion degree of the part of the encapsulation layer that fits the interposer is different from that of other parts, causing the device to warp, or due to the different expansion degrees of the interposer and the encapsulation layer, cracking and delamination occur at the interface between the two, affecting the normal use of the device.

[0033] Figure 1 The thickness of the intermediate packaging layer is relatively large, which affects heat dissipation. In addition, the leads from the interposer to the packaging substrate are concentrated in one direction (for example, the leads from the DRAM chip to the packaging substrate are located on the left side of the DRAM chip, and the leads from the interposer to the packaging substrate are located on the right side), resulting in severe heating in local areas. These two factors will make the above-mentioned warping, delamination and other phenomena more likely to occur.

[0034] The inventors also found that reference Figure 2 As shown, the UFS chip and the packaging substrate are wire-bonded through an interposer. Limited by the wire bonding rules, the bonding wires are wired in a single row in the X direction, resulting in a maximum of two ground bonding wires distributed along the X-axis on both sides of the high-speed signal or the power signal. This has limited improvements in the reference effect of the high-speed signal and the coupling effect between the power ground, and the power signals are concentrated in the X-axis direction and led out side by side, which is not conducive to reducing the PDN (Power Delivery Network) impedance.

[0035] The inventors also found that the line from the UFS chip to the package substrate includes: the bonding part between the UFS chip and the interposer, the wiring inside the interposer, and the bonding part between the interposer and the package substrate. If the line is too long, the signal delay of the UFS chip will be increased, affecting the signal integrity (SI) and power integrity (PI) of the device.

[0036] In view of one or more of the above problems, an exemplary embodiment of the present disclosure first provides a semiconductor package structure. Figure 3As shown, the semiconductor packaging structure may include: a packaging substrate 101; a random access memory chip 102, which forms a bond with a first connection portion 1011 on the packaging substrate 101; a packaging layer 103, which is located on the packaging substrate 101 and covers the random access memory chip 102; a redistribution layer 104, which is located on the packaging layer 103; a second conductive line 105, which is at least partially located in the packaging layer 103, connecting the second connection portion 1012 on the packaging substrate 101 and the bottom surface of the redistribution layer 104; a flash memory chip 106, which is located on the redistribution layer 104 and forms a bond with the top surface of the redistribution layer 104. The redistribution layer 104 includes a signal line 1042 and a reference line 1043, wherein the signal line 1042 is used for signal transmission between the flash memory chip 106 and the packaging substrate 101, and the reference line 1043 is used for providing a reference plane for signal transmission. The semiconductor packaging structure can package the random access memory chip 102 and the flash memory chip 106 in one device to achieve combined storage.

[0037] The following is a detailed description of each part of the semiconductor packaging structure.

[0038] The package substrate 101 is a carrier for packaging the random access memory chip 102 and the flash memory chip 106, and plays the role of electrical connection, protection, support, heat dissipation, assembly, etc. The package substrate 101 is provided with a first connection portion 1011 and a second connection portion 1012, the first connection portion 1011 is a connection portion for electrically connecting the random access memory chip 102, and the second connection portion 1012 is a connection portion for electrically connecting the flash memory chip 106. In one embodiment, the first connection portion 1011 and the second connection portion 1012 may be pads on the package substrate 101.

[0039] The random access memory (RAM) chip may be a DRAM or SRAM (Static Random Access Memory) chip, etc. In one embodiment, the random access memory chip 102 may be a stacked structure formed by a plurality of random access memory chip particles 1021 and a die bonding film 1022 (Die Attatch Film, DAF). The number of random access memory chip particles 1021 may be set according to actual needs, such as 4 DRAM particles may be set in one device.

[0040] The random access memory chip 102 is bonded to the first connection portion 1011 on the package substrate 101. In one embodiment, the random access memory chip 102 may be bonded to the first connection portion 1011 by flip-chip bonding, and the first connection portion 1011 may be a pad corresponding to a solder ball of the random access memory chip 102. In one embodiment, the random access memory chip 102 may be bonded to the first connection portion 1011 by wire bonding, and the first connection portion 1011 may be a pad corresponding to a bonding wire.

[0041] In one embodiment, the semiconductor package structure may further include a first conductive line 107 for electrically connecting the random access memory chip 102 to the package substrate 101. For example, the first conductive line 107 may be a bonding wire for bonding the random access memory chip 102 to the first connection portion 1011, such as Figure 3 Alternatively, the first conductive line 107 may be an electrical connection structure provided outside the bonding portion between the random access memory chip 102 and the package substrate 101, such as a patterned conductive film layer, which can form a more stable electrical connection between the random access memory chip 102 and the package substrate 101.

[0042] The encapsulation layer 103 is located on the encapsulation substrate 101. It should be noted that, in this exemplary embodiment, the direction in which the random access memory chip 102 and the flash memory chip 106 are located relative to the encapsulation substrate 101 is referred to as "upper", and the reverse is referred to as "lower", the top surface refers to the uppermost surface, and the bottom surface refers to the lowermost surface. The encapsulation layer 103 covers the top surface of the encapsulation substrate 101, covers the random access memory chip 102, and covers part or all of the second conductive line 105. The encapsulation layer 103 can be formed by an injection molding process using an injection molding material (such as EMC, etc.).

[0043] The redistribution layer 104 (RDL) is located on the packaging layer 103. Figure 1 Unlike the interposer layer, the redistribution layer 104 does not need to be arranged in the packaging layer 103. The redistribution layer 104 is usually composed of conductive wires (such as signal lines 1042 and reference lines 1043) and an insulating layer 1041 covering the conductive wires. The conductive wires can be made of metals such as aluminum, copper, or their alloys, or non-metallic conductive materials. The conductive wires connect the bottom and top surfaces of the redistribution layer 104 to form an internal passage. The insulating layer 1041 has the functions of isolation, insulation, and protection for the conductive wires, and can be made of insulating dielectric materials such as PI (Polyimide). The redistribution layer 104 can include any number of insulating layers 1041, and different insulating layers 1041 can be made of different materials.

[0044] The second conductive wire 105 connects the second connection portion 1012 on the package substrate 101 and the bottom surface of the redistribution layer 104 to achieve electrical connection between the package substrate 101 and the redistribution layer 104. The second conductive wire 105 may be entirely located within the package layer 103, or the upper end of the second conductive wire 105 may extend outside the package layer 103. Exemplarily, the second conductive wire 105 may be a bonding wire or a patterned conductive film layer.

[0045] The flash memory chip 106 may be a UFS chip or the like, which is located on the redistribution layer 104 and is bonded to the top surface of the redistribution layer 104. Exemplarily, the flash memory chip 106 may be bonded to the top surface of the redistribution layer 104 by flip-chip bonding, and the top surface of the redistribution layer 104 may be provided with a solder pad, and a solder ball is formed on the active surface of the flash memory chip 106, and then the flash memory chip 106 is flipped so that the solder ball is bonded to the solder pad on the top surface of the redistribution layer 104. Alternatively, the flash memory chip 106 may also be bonded to the top surface of the redistribution layer 104 by wire bonding. Thus, the flash memory chip 106 is bonded to the package substrate 101 through the redistribution layer 104, realizing a path from the second connection portion 1012 to the second conductive wire 105, the conductive layer 1041 in the redistribution layer 104, and the flash memory chip 106.

[0046] In this exemplary embodiment, the redistribution layer 104 includes a signal line 1042 and a reference line 1043. The signal line 1042 and the second conductive line 105 connected to the signal line 1042 form a signal transmission path between the flash memory chip 106 and the packaging substrate 101, which can be used to transmit high-speed signals of the flash memory chip 106. The reference line 1043 is used to provide a reference plane for signal transmission. When a high-speed signal is transmitted in the signal line 1042, a backflow is generated in the reference line 1043 through the induction of an electromagnetic field, etc. Therefore, the reference line 1043 can be used as a backflow path for the signal and provide a reference plane for signal transmission. The reference line 1043 can be a power line 1044 and / or a ground line 1045.

[0047] Based on the semiconductor packaging structure in this exemplary embodiment, the following technical effects can be achieved: First, instead of using an intermediate layer, a redistribution layer 104 is used to achieve the bonding of the flash memory chip 106 to the packaging substrate 101. The redistribution layer 104 is located above the packaging layer 103 rather than within the packaging layer 103. Even if there is a mismatch in the thermal expansion coefficients between the redistribution layer 104 and the packaging layer 103, when the semiconductor device is heated, problems such as warping and delamination are not likely to occur. Second, a suitable insulating medium can be used as a carrier in the redistribution layer 104. Compared with the intermediate layer, there is a greater choice of media to match the thermal expansion coefficient of the packaging layer 103, thereby further improving problems such as warping and delamination, and ensuring the performance of the semiconductor device. Third, the circuit between the flash memory chip 106 and the packaging substrate 101 includes the second conductive wire 105, the routing within the redistribution layer 104, and the bonding portion between the flash memory chip 106 and the redistribution layer 104. Compared with Figure 1 The length of the second conductive line 105 is shorter than the line from the interposer to the package substrate, and the line in the redistribution layer 104 is shorter than the line in the interposer. Therefore, this solution can shorten the line length between the flash memory chip 106 and the package substrate 101, and improve signal integrity and power integrity. Fourthly, setting both the signal line 1042 and the reference line 1043 in the redistribution layer 104 is conducive to simplifying the package structure. The reference line 1043 provides a reference plane for signal transmission. It is located in the redistribution layer 104 and can play a good shielding role to avoid electromagnetic coupling between the redistribution layer 104 and external interference sources. Under the action of the reference plane, the signal line 1042 can be regarded as a microstrip line with better signal transmission characteristics, which can also improve signal integrity.

[0048] In one embodiment, the second connection portion 1012 is a pad on the package substrate 101, and the second conductive wire 105 can be a bonding wire, connecting the second connection portion 1012 and the pad on the bottom surface of the redistribution layer 104 to achieve bonding between the two pads. This is conducive to simplifying the bonding process.

[0049] The second conductive line 105 can form a vertical connection between the package substrate 101 and the redistribution layer 104. That is, the second conductive line 105 can be in a form perpendicular to the package substrate 101. Considering that it is difficult to ensure the absolute verticality of the second conductive line 105 in the actual process, in one embodiment, the ratio of the projection size of the second conductive line 105 on the plane of the package substrate 101 to the vertical size of the second conductive line 105 can be less than a preset ratio value. Herein, the plane of the package substrate 101 (such as the top surface of the package substrate 101) can be recorded as the XY plane, and the direction perpendicular to the plane can be recorded as the Z-axis direction. The projection size of the second conductive line 105 on the XY plane can be the maximum size between any two points on the projection figure of the second conductive line 105 on the XY plane, which represents the lateral span of the second conductive line 105, and the vertical size of the second conductive line 105 is the height along the Z axis. The preset ratio value can be determined based on experience and various dimensions in the semiconductor packaging structure. Setting the ratio of the projected size to the vertical size to be less than the preset ratio value (e.g., 0.2-0.3) can ensure that the ratio of the projected size to the vertical size is at a lower level, that is, the lateral span of the second conductive line 105 is smaller than its vertical size, which means that the second conductive line 105 is vertical or nearly vertical. Thus, the length of the second conductive line 105 can be further reduced, which is conducive to simplifying the process and further shortening the line length between the flash memory chip 106 and the packaging substrate 101.

[0050] In one implementation, in order to ensure the vertical shape of the second conductive line 105 , the diameter of the second conductive line 105 may be set to be no less than 50 μm, so that the second conductive line 105 can maintain a certain rigidity and is not easily deviated.

[0051] In one embodiment, the second conductive lines 105 may be distributed in multiple directions of the random access memory chip 102. Exemplarily, the portion of the packaging layer 103 outside the random access memory chip 102 may be divided into four or more regions, such as a region to the east of the random access memory chip 102, a region to the south of the random access memory chip 102, a region to the west of the random access memory chip 102, and a region to the north of the random access memory chip 102 (east, south, west, and north may be four mutually perpendicular directions in the XY plane), and the second conductive lines 105 may be distributed in multiple of these regions. For example, the second conductive lines 105 may be evenly distributed in the four directions of the random access memory chip 102: east, south, west, and north. Figure 1In the structure, the leads between the interposer and the package substrate 101 are usually distributed on one side of the random access memory chip 102 to avoid the influence of the random access memory chip 102. In this exemplary embodiment, the second conductive wire 105 is an electrical connection structure between the package substrate 101 and the bottom surface of the redistribution layer 104. Since the area of ​​the redistribution layer 104 is large and the vertical or nearly vertical bonding structure is not affected by the wire bonding rule, there is a larger space to set the second conductive wire 105, so that it is distributed in multiple directions of the random access memory chip 102. In this way, the distribution of the second conductive wire 105 is relatively dispersed, which is conducive to improving the problem of local heating.

[0052] In one embodiment, the first conductive wire 107 is a bonding wire that bonds the random access memory chip 102 to the first connection portion 1011. The thickness of the packaging layer 103 can be: the distance between the highest point of the first conductive wire 107 and the packaging substrate 101 plus the margin value. Figure 3 As shown, the encapsulation layer 103 needs to cover the random access memory chip 102 and the first conductive line 107, so the thickness of the encapsulation layer 103 is greater than the height of the highest point of the random access memory chip 102 and the first conductive line 107, which is the distance between the highest point of the first conductive line 107 and the encapsulation substrate 101. On this basis, in order to achieve sufficient coverage of the encapsulation layer 103, a certain margin value can be set so that the encapsulation layer 103 is higher than the highest point of the first conductive line 107 by the margin value.

[0053] In one embodiment, if the random access memory chip 102 is flip-chip bonded to the first connection portion 1011 , the thickness of the packaging layer 103 may be: the distance between the highest point of the random access memory chip 102 and the packaging substrate 101 plus a margin value.

[0054] By using the above-mentioned solution for determining the thickness of the encapsulation layer 103, the thickness of the encapsulation layer 103 can be effectively reduced. Figure 1 The packaging layer 103 does not need to cover the intermediate layer, and its thickness is reduced. This can improve the heat dissipation of the device, thereby making the above-mentioned warping, delamination and other phenomena less likely to occur.

[0055] In one embodiment, the bounding box of the projection of the connection point between the signal line 1042 and the bottom surface of the redistribution layer 104 on the reference plane is located within the bounding box of the projection of the connection point between the reference line 1043 and the bottom surface of the redistribution layer 104 on the reference plane. The reference plane is parallel to the top surface of the package substrate 101, that is, the XY plane. Figure 4AThe projection of the connection point between the signal line 1042 and the bottom surface of the redistribution layer 104 on the reference plane and its bounding box A are shown. The connection point between the signal line 1042 and the bottom surface of the redistribution layer 104, that is, the connection point between the signal line 1042 and the second conductive line 105, can be the bottom pad of the redistribution layer 104 connected to the signal line 1042. In this exemplary embodiment, the bounding box refers to the smallest rectangle (or other shape) that encloses the projection. Figure 4A Also shown are the projections of the connection points between the reference line 1043 and the bottom surface of the redistribution layer 104 on the reference plane and their bounding box B. The connection points between the reference line 1043 and the bottom surface of the redistribution layer 104, i.e., the connection points between the reference line 1043 and the second conductive line 105, may be the bottom pads of the redistribution layer 104 to which the reference line 1043 is connected. The bounding box A is located within the bounding box B, which means that on the reference plane, the range of the reference line 1043 is larger than the range of the signal line 1042, the reference line 1043 may be a larger plane, and the signal line 1042 may be a smaller plane, or it can be understood that the bottom pads connected to the reference line 1043 surround the bottom pads connected to the signal line 1042, thereby providing a relatively complete reference plane for the signal line 1042, which is beneficial to reducing the impedance of the return path. The signal current is returned through the reference plane, which can reduce the transmission delay and power consumption of the signal and improve the signal transmission quality.

[0056] In one embodiment, the bounding box of the projection of the connection point between the signal line 1042 and the top surface of the redistribution layer 104 on the reference plane is located within the bounding box of the projection of the connection point between the reference line 1043 and the top surface of the redistribution layer 104 on the reference plane. In other words, among the top surface pads of the redistribution layer 104 (or the solder balls of the flash memory chip 106), the distribution range of the top surface pads (or solder balls) connected to the signal line 1042 is within the distribution range of the top surface pads (or solder balls) connected to the reference line 1043. It can be understood that the top surface pads (or solder balls) connected to the reference line 1043 surround the top surface pads (or solder balls) connected to the signal line 1042, which can also provide a relatively complete reference plane for the signal line 1042, which is conducive to reducing the impedance of the return path, reducing the transmission delay and power consumption of the signal, and improving the signal transmission quality.

[0057] In one embodiment, the reference line 1043 includes a power line 1044 and a ground line 1045. The power line 1044 is used to transmit power between the flash memory chip 106 and the packaging substrate 101, and can provide power supply for the flash memory chip 106. The ground line 1045 is used to connect the flash memory chip 106 to the ground terminal. The enclosing box of the projection of the connection point between the signal line 1042 and the bottom surface of the redistribution layer 104 on the reference plane is located within the enclosing box of the projection of the connection point between the ground line 1045 and the bottom surface of the redistribution layer 104 on the reference plane. The enclosing box of the projection of the connection point between the ground line 1045 and the bottom surface of the redistribution layer 104 on the reference plane is located within the enclosing box of the projection of the connection point between the power line 1044 and the bottom surface of the redistribution layer 104 on the reference plane.

[0058] Figure 4B The projection of the connection point between the signal line 1042 and the bottom surface of the redistribution layer 104 on the reference plane and its enclosing box A, the projection of the connection point between the power line 1045 and the bottom surface of the redistribution layer 104 on the reference plane and its enclosing box B1, and the projection of the connection point between the ground line 1044 and the bottom surface of the redistribution layer 104 on the reference plane and its enclosing box B2 are shown. Enclosing box A is located within enclosing box B2, and enclosing box B2 is located within enclosing box B1. This means that on the reference plane, the range of the power line 1044 is larger than the range of the ground line 1044, and the range of the ground line 1044 is larger than the range of the signal line 1042, or it can be understood that the bottom pad connected to the power line 1044 surrounds the bottom pad connected to the ground line 1044, and the bottom pad connected to the ground line 1044 surrounds the bottom pad connected to the signal line 1042. In addition to providing a relatively complete reference plane for the signal line 1042 , this can also increase the coupling between the power line 1044 and the ground line 1045 , thereby reducing the impedance of the power line 1044 .

[0059] In one embodiment, the bounding box of the projection of the connection point between the signal line 1042 and the top surface of the redistribution layer 104 on the reference plane is located within the bounding box of the projection of the connection point between the ground line 1045 and the top surface of the redistribution layer 104 on the reference plane. In other words, among the top surface pads of the redistribution layer 104 (or the solder balls of the flash memory chip 106), the distribution range of the top surface pads (or solder balls) connected to the signal line 1042 is within the distribution range of the top surface pads (or solder balls) connected to the ground line 1045, and the distribution range of the top surface pads (or solder balls) connected to the ground line 1045 is within the distribution range of the top surface pads (or solder balls) connected to the power line 1044. Figure 5The top view of the redistribution layer 104 is shown, and the middle area is the area bonded to the flash memory chip 106, which is provided with a top pad. It can be understood that the top pad (or solder ball) connected to the power line 1044 surrounds the top pad (or solder ball) connected to the ground line 1045, and the top pad (or solder ball) connected to the ground line 1045 surrounds the top pad (or solder ball) connected to the signal line 1042, which can also provide a relatively complete reference plane for the signal line 1042, increase the coupling between the power line 1044 and the ground line 1045, and reduce the impedance of the power line 1044.

[0060] In one embodiment, reference Figure 6 The redistribution layer 104 in the embodiment may be a stacked structure formed by a signal layer 1047, a power layer 1046 and a ground layer 1048. The signal layer 1047 is located between the power layer 1046 and the ground layer 1048, that is, it may be the middle layer of the redistribution layer 104. Figure 6 It is shown that the power layer 1046 is located at the bottom layer of the redistribution layer 104, thereby reducing the length of the second conductive line 105, reducing the power transmission path, thereby reducing the voltage drop and ensuring the power integrity. The ground layer 1048 is located at the top layer of the redistribution layer 104. The present disclosure does not limit this. For example, the power layer 1046 may also be located at the top layer of the redistribution layer 104, and the ground layer 1048 may also be located at the bottom layer of the redistribution layer 104.

[0061] Signal line 1042 includes horizontal signal wiring parallel to the reference plane (ie Figure 3 or Figure 6 The horizontal section of the signal line 1042 in the middle, where the horizontal section is a plane) and the vertical signal wiring perpendicular to the reference plane (i.e. Figure 3 or Figure 6 The vertical segment of the signal line 1042 may include a vertical segment connected to the bottom surface of the redistribution layer 104 and a vertical segment connected to the top surface of the redistribution layer 104), and the horizontal signal wiring is located in the signal layer 1047. It should be understood that the signal layer 1047 may include horizontal signal wiring and an insulating medium covering the horizontal signal wiring.

[0062] The reference line 1043 includes a power supply line 1044 and a ground line 1045. The power supply line 1044 includes a horizontal power supply wiring (i.e. Figure 6 The horizontal section of the power supply line 1044 in the middle, where the horizontal section is a plane) and the vertical power supply wiring perpendicular to the reference plane (i.e. Figure 6The vertical segment of the power line 1044 may include a vertical segment connected to the bottom surface of the redistribution layer 104 and a vertical segment connected to the top surface of the redistribution layer 104), and the horizontal power wiring is located in the power layer 1046. It should be understood that the power layer 1046 may include horizontal power wiring and an insulating medium covering the horizontal power wiring. The ground line 1045 includes a horizontal ground wiring parallel to the reference plane (i.e. Figure 6 The horizontal section of the ground line 1045 in the middle, where the horizontal section is a plane) and the vertical ground wiring perpendicular to the reference plane (i.e. Figure 6 The vertical segment of the ground line 1045 may include a vertical segment connected to the bottom surface of the redistribution layer 104 and a vertical segment connected to the top surface of the redistribution layer 104), and the horizontal ground wiring is located in the ground layer 1048. It should be understood that the ground layer 1048 may include a horizontal ground wiring and an insulating medium covering the horizontal ground wiring.

[0063] As can be seen from the above, the signal layer 1047 is located between the power layer 1046 and the ground layer 1048, which provides a reference plane in both the upper and lower directions of signal transmission, and can further reduce the impedance of the return path and improve signal integrity.

[0064] like Figure 6 As shown, in some embodiments, the horizontal plane of the power supply line 1044 can be set corresponding to the horizontal plane of the ground line 1045, that is, the two can have the same area, and the areas of both are larger than the area of ​​the signal line 1042, thereby forming a complete reference plane, providing a low-impedance return path, so that the signal current can return through the reference plane, thereby reducing the signal transmission delay and power consumption, and further improving the signal transmission quality.

[0065] like Figure 6 As shown, in some embodiments, the second conductive line 105 connected to the power line 1044 can be defined as a power conductive line, the second conductive line 105 connected to the ground line 1045 can be defined as a ground conductive line, and the second conductive line 105 connected to the signal line 1042 can be defined as a signal conductive line. The diameter of the power conductive line can be greater than the diameter of the ground conductive line, so that the voltage has a smaller voltage drop on the power conductive line to ensure power integrity.

[0066] like Figure 6 As shown, in some embodiments, the ground conductive line can be arranged on the periphery of the signal conductive line, and the power conductive line can be arranged on the periphery of the ground conductive line. Figure 4BAs shown, the projection position of the connection point between the signal line 1042 and the bottom surface of the redistribution layer 104 can be equal to the projection position of the signal conductor; the projection position of the connection point between the power line 1044 and the bottom surface of the redistribution layer 104 can be equal to the projection position of the power conductive line; the projection position of the connection point between the ground line 1045 and the bottom surface of the redistribution layer 104 can be equal to the projection position of the ground conductive line. On the reference plane, the ground conductive line is located at the periphery of the signal conductive line, and the power conductive line is located at the periphery of the ground conductive line. Thus, the ground conductive line provides a return path for the signal conductive line to reduce impedance.

[0067] In this exemplary embodiment, the second connection portion 1012 on the package substrate 101, or the bottom pad of the redistribution layer 104, or the top pad of the redistribution layer 104 can be staggered in the X-axis and Y-axis directions. Thus, the arrangement of the signal line 1042, the power line 1044, and the ground line 1045 can be flexibly set to make their distribution more reasonable, such as Figure 4B In the arrangement shown in FIG. 1 , ground lines 1045 are distributed around the signal line 1042 and the power line 1044. Figure 2 The single-row bonding shown enhances the signal's ability to resist electromagnetic interference, increases mutual capacitance, and reduces capacitive impedance.

[0068] In one embodiment, the semiconductor package structure can refer to Figure 6As shown, it includes: a packaging substrate 101. A random access memory chip 102, which is composed of at least two random access memory chip particles 1021 and at least two chip adhesive films 1022. The random access memory chip 102 is bonded to a first connection portion 1011 on the packaging substrate 101 through a first conductive line 107. A packaging layer 103, located on the packaging substrate 101, covers the random access memory chip 102, the first conductive line 107 and the second conductive line 105. A redistribution layer 104, located on the packaging layer 103, includes a signal line 1042, a power line 1044, a ground line 1045, a power layer 1046, a signal layer 1047, and a ground layer 1048. The horizontal signal wiring in the signal line 1042 is located in the signal layer 1047, and the vertical signal wiring extends to the power layer 1046 and the ground layer 1048, connecting the bottom pad and the top pad of the redistribution layer 104; the horizontal power wiring in the power line 1044 is located in the power layer 1046, and the vertical power wiring extends to the signal layer 1047 and the ground layer 1048, connecting the bottom pad and the top pad of the redistribution layer 104; the horizontal ground wiring in the ground line 1045 is located in the ground layer 1048, and the vertical signal wiring extends to the signal layer 1047 and the power layer 1046, connecting the bottom pad and the top pad of the redistribution layer 104. The power layer 1046, the signal layer 1047, and the ground layer 1048 can all include one or more insulating media to cover the signal line 1042, the power line 1044, and the ground line 1045. The second conductive wire 105 is located in the packaging layer 103 and connects the second connection portion 1012 on the packaging substrate 101 with the bottom pad of the redistribution layer 104. The flash memory chip 106 is located on the redistribution layer 104 and forms a flip-chip bond with the top pad of the redistribution layer 104.

[0069] based on Figure 6 The semiconductor packaging structure shown can achieve better signal integrity and power integrity. Fig. 7A and Figure 7B The improvement of the S parameter of the differential signal, that is, the improvement of the signal integrity of the flash memory chip 106 is shown. Among them, dB[S(3,7)] is the insertion loss value based on the implementation of this exemplary embodiment, and dB[S(2,6)] is the insertion loss value based on the existing structure. Taking 5.8 GHz as an example, dB[S(3,7)] is -0.715 dB, and dB[S(2,6)] is -0.780 dB. dB[S(8,8)] is the return loss value based on the implementation of this exemplary embodiment, and dB[S(6,6)] is the return loss value based on the existing structure. Taking 5.8 GHz as an example, dB[S(8,8)] is -16.058 dB, and dB[S(6,6)] is -13.506 dB. It can be seen that the signal integrity is improved in this exemplary embodiment.

[0070] Figure 7C The figure shows the improvement of the DC impedance of the power supply, that is, the improvement of the power integrity of the flash memory chip 106. The impedance difference between Z(1,1) and Z(2,2) is 5 mΩ. It can be seen that the exemplary embodiment improves the power integrity.

[0071] The exemplary embodiments of the present disclosure also provide a semiconductor packaging method. Figure 8 As shown, the method may include the following steps S810 to S860:

[0072] Step S810 , providing a packaging substrate 101 , a random access memory chip 102 to be packaged, and a flash memory chip 106 .

[0073] In one implementation, a plurality of random access memory chip particles 1021 may be stacked and bonded together through a chip bonding film 1022 to form a random access memory chip 102 with a stacked structure.

[0074] Step S820 , bonding the random access memory chip 102 to the first connection portion 1011 on the package substrate 101 .

[0075] For example, the random access memory chip 102 may be bonded to the first connection portion 1011 on the package substrate 101 by wire bonding or flip-chip bonding.

[0076] Step S830 , forming a second conductive line 105 , wherein the second conductive line 105 is connected to the second connection portion 1012 on the package substrate 101 and extends upward.

[0077] In one embodiment, the second conductive wire 105 may be a bonding wire. Step S630 may specifically include: pressing a solder ball on the second connection portion 1012 on the package substrate 101, pulling the bonding wire into an arc shape and forming a wedge-shaped weak point, then pulling the bonding wire upward to form a vertical or nearly vertical shape, and breaking the wedge-shaped weak point, thereby forming a complete second conductive wire 105.

[0078] Step S840 , forming a packaging layer 103 on the packaging substrate 101 , covering the random access memory chip 102 and at least partially covering the second conductive line 105 .

[0079] For example, the encapsulation layer 103 may be formed by an injection molding process, etc. to cover the random access memory chip 102 and at least partially cover the second conductive line 105. In addition, the first conductive line 107 may also be covered.

[0080] In one embodiment, after forming the packaging layer 103 on the packaging substrate 101, the semiconductor packaging method may further include the following steps:

[0081] The top surface of the packaging layer 103 is ground to expose the top of the second conductive line 105 .

[0082] When the encapsulation layer 103 is formed by a process such as injection molding, the encapsulation layer may extend beyond the top of the second conductive wire 105. The top surface of the encapsulation layer 103 may be polished by a process such as chemical mechanical polishing to expose the top of the second conductive wire 105, so that a redistribution layer 104 is formed on the encapsulation layer 103, and the bottom pad of the redistribution layer 104 may contact the top of the second conductive wire 105 to form a bond.

[0083] Step S850, forming a redistribution layer 104 on the packaging layer 103, and the second conductive line 105 is connected to the bottom surface of the redistribution layer 104; the redistribution layer 104 includes a signal line 1042 and a reference line 1043, the signal line 1042 is used to transmit signals between the flash memory chip 106 and the packaging substrate 101, and the reference line 1043 is used to provide a reference plane for signal transmission.

[0084] Exemplarily, one or more layers of insulating layer 1041 can be first formed, and the insulating layer 1041 can be patterned through photolithography and etching processes to reserve parts of the signal line 1042 and the reference line 1043, and then the signal line 1042 and the reference line 1043 are formed. The bottom of the signal line 1042 and the reference line 1043 can contact the top of the second conductive line 105, and then the top surface of the signal line 1042, the reference line 1043, and the insulating layer 1041 are processed through processes such as chemical mechanical polishing to expose the top surface pad to form the final redistribution layer 104.

[0085] In one implementation, a passivation layer may be formed on the redistribution layer 104 to protect the redistribution layer 104 .

[0086] Step S860 , bonding the flash memory chip 106 to the top surface of the redistribution layer 104 .

[0087] For example, the flash memory chip 106 may be bonded to the top surface of the redistribution layer 104 by wire bonding or flip-chip bonding.

[0088] In one embodiment, the bonding of the flash memory chip 106 to the top surface of the redistribution layer 104 may include the following steps:

[0089] Solder balls are formed on the bottom of the flash memory chip 106 and bonded to pads on the top surface of the redistribution layer 104 .

[0090] Exemplarily, a flip-chip bonding process may be used to flip the flash memory chip 106, and then form solder balls at its bottom (i.e., the top before flipping), and corresponding solder balls may be formed according to the conductive positions in the bottom conductive layer. Pads corresponding to the solder balls are formed on the top surface of the redistribution layer 104, and the bottom solder balls of the flash memory chip 106 may be bonded to the pads to form a connection between the flash memory chip 106 and the redistribution layer 104. Solder ball bonding may make the distribution of solder balls more reasonable and uniform, improve heat dissipation and signal transmission, and help simplify the structure and process.

[0091] It should be understood that the present disclosure is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from the scope thereof. The present application is intended to cover any variation, use or adaptation of the technical solution, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the art that are not disclosed herein. The contents of the specification are to be regarded as exemplary only, and the scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A semiconductor packaging structure, characterized in that: include: Package substrate; A random access memory chip is bonded to the first connection portion on the packaging substrate; A packaging layer, located on the packaging substrate and covering the random access memory chip; A redistribution layer, located on the packaging layer; A second conductive line, at least partially located in the packaging layer, connecting a second connection portion on the packaging substrate and a bottom surface of the redistribution layer; A flash memory chip is located on the redistribution layer and is bonded to the top surface of the redistribution layer; The redistribution layer includes a signal line and a reference line. The signal line is used for signal transmission between the flash memory chip and the packaging substrate, and the reference line is used for providing a reference plane for signal transmission.

2. The semiconductor package structure according to claim 1, wherein: The second connection portion is a pad on the packaging substrate, and the second conductive wire is a bonding wire, connecting the second connection portion and the pad on the bottom surface of the redistribution layer.

3. The semiconductor package structure according to claim 2, characterized in that: The ratio of the projection size of the second conductive line on the plane of the packaging substrate to the vertical size of the second conductive line is smaller than a preset ratio value.

4. The semiconductor package structure according to claim 1, wherein: The second conductive lines are distributed in multiple directions of the random access memory chip.

5. The semiconductor packaging structure according to any one of claims 1 to 4, characterized in that: The enclosing box of the projection of the connection point between the signal line and the bottom surface of the redistribution layer on the reference plane is located within the enclosing box of the projection of the connection point between the reference line and the bottom surface of the redistribution layer on the reference plane; the reference plane is parallel to the top surface of the packaging substrate.

6. The semiconductor package structure according to claim 5, characterized in that: The reference circuit includes a power circuit and a ground circuit; The bounding box of the projection of the connection point between the signal line and the bottom surface of the redistribution layer on the reference plane is located within the bounding box of the projection of the connection point between the ground line and the bottom surface of the redistribution layer on the reference plane; The bounding box of the projection of the connection point between the ground line and the bottom surface of the redistribution layer on the reference plane is located within the bounding box of the projection of the connection point between the power line and the bottom surface of the redistribution layer on the reference plane.

7. The semiconductor package structure according to claim 1, wherein: The redistribution layer is a stacked structure formed by a signal layer, a power layer and a ground layer; the signal layer is located between the power layer and the ground layer; The signal line includes a horizontal signal wiring parallel to a reference plane and a vertical signal wiring perpendicular to the reference plane, wherein the horizontal signal wiring is located in the signal layer; The reference circuit includes a power circuit and a ground circuit; the power circuit includes a horizontal power wiring parallel to the reference plane and a vertical power wiring perpendicular to the reference plane, and the horizontal power wiring is located in the power layer; the ground circuit includes a horizontal ground wiring parallel to the reference plane and a vertical ground wiring perpendicular to the reference plane, and the horizontal ground wiring is located in the ground layer; The reference plane is parallel to the top surface of the packaging substrate.

8. The semiconductor package structure according to claim 7, characterized in that: A diameter of the second conductive line connected to the power line is greater than a diameter of the second conductive line connected to the ground line.

9. The semiconductor package structure according to claim 7 or 8, characterized in that: The second conductive line connected to the ground line is arranged at the periphery of the second conductive line connected to the signal line, and the second conductive line connected to the power signal is arranged at the periphery of the second conductive line connected to the ground signal.

10. A semiconductor packaging method, characterized in that: include: Providing a packaging substrate, a random access memory chip and a flash memory chip to be packaged; Bonding the random access memory chip to a first connection portion on the packaging substrate; forming a second conductive line, wherein the second conductive line is connected to a second connecting portion on the packaging substrate and extends upward; Forming a packaging layer on the packaging substrate, covering the random access memory chip and at least partially covering the second conductive line; forming a redistribution layer on the packaging layer, wherein the second conductive line is connected to a bottom surface of the redistribution layer; The redistribution layer includes a signal line and a reference line, wherein the signal line is used for signal transmission between the flash memory chip and the packaging substrate, and the reference line is used for providing a reference plane for signal transmission; The flash memory chip is bonded to the top surface of the redistribution layer.

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