Recessed polysilicon ESD diode for power MOSFET

Abstract

A protection structure for a power transistor includes one or more pairs of back-to-back pn junction diodes formed in a trench polysilicon layer disposed in a trench formed in a semiconductor substrate. At least a portion of the trench polysilicon layer protrudes over a top surface of the semiconductor substrate. Alternating N-type doped regions and P-type doped regions are formed in the trench polysilicon layer along the length of the trench. When coupled across the gate and source terminals of the power transistor, a protection structure may advantageously be applied to protect the power transistor from high voltage ESD events.

Description

Technical Field

[0001] The present invention relates to a protection circuit for a power semiconductor device, and in particular to an electrostatic discharge protection circuit for a power transistor. Background Art

[0002] Voltage and current transients are the leading cause of integrated circuit failure in electronic systems. Transients are generated by a variety of sources both internal and external to the system. For example, common transient sources include normal switching operations of power supplies, AC line fluctuations, lightning strikes, and electrostatic discharge (ESD). High voltage transient events can permanently damage the materials used to form the integrated circuit, causing integrated circuit failure.

[0003] Power transistors, such as power MOSFETs, are often used in applications that switch voltages from a few volts to thousands of volts. Such power transistors typically include protection circuits integrated therewith to protect the power transistors from handling electrostatic discharge (ESD) during system assembly and human operation in consumer products. For example, the gate terminal of a power transistor may not be able to withstand high energy ESD events. On-chip ESD protection circuits typically include various diode structures that are coupled to protect the input gate of the power MOSFET. The ESD protection circuit provides an electrical path to divert current caused by a high voltage ESD event away from the power MOSFET device, thereby preventing the MOSFET device from being damaged. In some examples, trench polysilicon diodes used as ESD protection diodes have been described, such as in U.S. Patent 8,476,676 and U.S. Patent 9,431,550.

[0004] Figure 1 A schematic diagram showing a power transistor with an ESD protection circuit in some examples. Figure 1, the power transistor 1 or power MOSFET includes a gate terminal G as a control gate input, a drain terminal D usually connected to a power supply, and a source terminal S usually connected to a load. The diode BD represents a body diode formed in the power MOSFET 1, and it should be understood that the body diode BD is a parasitic device of the transistor structure rather than a diode device formed separately. The power MOSFET 1 requires ESD protection for the gate terminal G. In this example, an ESD protection circuit 2 configured as a back-to-back diode string is provided between the gate terminal and the source terminal of the power MOSFET device. More specifically, the ESD protection circuit 2 includes one or more pairs of pn junction diodes connected back to back. In this example, the ESD protection circuit 2 includes a pair of pn junction diodes connected back to back formed by diodes D1 and D2. Diodes D1 and D2 are connected back to back because their anodes are connected together. The cathode of diode D1 is connected to the gate terminal G of the power MOSFET, and the cathode of diode D2 is connected to the source terminal. To achieve protection against high voltage ESD events, the breakdown voltage of diodes D1 and D2 is greater than the maximum operating voltage at the gate terminal, but less than the gate dielectric breakdown voltage. In this way, the power MOSFET 1 operates normally within the operating voltage range, but in the case of a high voltage ESD event, the diode string of D1 and D2 is activated to divert current to protect the gate terminal of the power MOSFET from damage. Multiple pairs of back-to-back diodes are used to support higher operating gate voltages at the power MSOFET. In the case of multiple back-to-back diodes, the cathode of the first diode and the cathode of the last diode are connected to the gate and source terminals, respectively.

[0005] Figure 2 A perspective view of a power transistor and an ESD protection structure formed on a semiconductor substrate in some examples. Specifically, Figure 2 FIG. 4 shows a typical implementation of providing a diode string as an ESD protection circuit for a trench gate power transistor. Figure 2 , the power transistor 10 is formed as a vertical transistor, and a polysilicon gate terminal 14 is disposed in a trench formed in a semiconductor substrate 12. The polysilicon gate 14 is isolated from the semiconductor substrate 12 by a gate dielectric layer 15. A body region 16 such as a P-type doped region is formed in the top of the semiconductor substrate 12. A source region 18 such as a heavily doped N-type doped region or an N+ doped region is formed in the body region 16. The semiconductor substrate 12 forms a drain terminal of the power transistor 10.

[0006] In this configuration, the ESD protection circuit 20 is constructed as back-to-back polysilicon diodes formed on top of the semiconductor substrate 12 in a region separated from the power transistor 10. For example, a polysilicon layer 25 is formed on the semiconductor substrate 12 and isolated from the substrate by a dielectric layer 26 such as a silicon oxide layer. The polysilicon layer 25 is masked and doped to form alternating N-type doped regions 22 and P-type doped regions 24. In most cases, the N-type region 22 is more heavily doped than the P-type region 24. The alternating N-type and P-type doped regions form back-to-back pn junction diodes, as shown by diodes D1, D2, D3, etc. Metal contacts and metal interconnects are used to connect the diode string to the gate and source terminals of the power transistor 10.

[0007] With such a configuration, the ESD rating of the ESD protection circuit 20 is determined by the cross-sectional area of ​​the polysilicon layer 25 at the interface of the NP doped region. If it is desired to increase the ESD rating, the planar area of ​​the polysilicon layer 25 must be made larger, which requires more substrate area to achieve, and is therefore more expensive. In addition, the polysilicon layer 25 formed above the semiconductor substrate 12 increases the step height of the device, requiring the use of thick photoresist, thereby limiting the use of advanced lithography. Increasing the vertical thickness of the polysilicon layer 25 to increase the cross-sectional area of ​​the ESD rating is also undesirable because it will result in a further increase in the height of the step. Summary of the invention

[0008] The object of the present invention is to provide a recessed polysilicon ESD diode for a power MOSFET.

[0009] According to one embodiment of the present invention, a protection structure for a power transistor including a gate terminal, a first current terminal, and a second current terminal includes at least one pair of pn junction diodes connected in a back-to-back configuration, the pn junction diodes being disposed in a first portion of a semiconductor substrate, the pn junction diodes being formed in a first polysilicon layer, the first polysilicon layer being disposed in a first trench formed in a semiconductor substrate, the first polysilicon layer being isolated from the semiconductor substrate by a first dielectric layer formed on a sidewall of the first trench, the first polysilicon layer having alternating doped regions of a first conductivity type and a second conductivity type along a length of the first trench, at least a portion of the first silicon layer being formed above a first surface of the semiconductor substrate. A first doped region of the first conductivity type in the first polysilicon layer is coupled to the gate terminal of the power transistor, and a second doped region of the first conductivity type in the first polysilicon layer is coupled to the second current terminal of the power transistor, the first doped region being separated from the second doped region by a third doped region of the second conductivity type.

[0010] According to another embodiment of the present invention, a method for manufacturing a protection structure of a power transistor including a gate terminal, a first current terminal, and a second current terminal includes forming a first plurality of trenches in a first region of a semiconductor substrate, the first plurality of trenches having a length extending in a first direction; forming a first polysilicon layer in the first plurality of trenches, the first polysilicon layer being isolated from the semiconductor substrate by a first dielectric layer; after forming the first polysilicon layer, forming a second plurality of trenches in a second region of the semiconductor substrate, the second plurality of trenches having a length extending in the first direction; and insulating the semiconductor substrate in the second plurality of trenches and in the first region. forming a second dielectric layer above the first surface of the bottom; forming a second polysilicon layer in the second plurality of trenches and above the second dielectric layer, the second polysilicon being isolated from the semiconductor substrate by the second dielectric layer; removing portions of the second polysilicon layer and the second dielectric layer from the first area of ​​the semiconductor substrate, the remaining portions of the second polysilicon film being formed in the second plurality of trenches, and at least a portion of the second polysilicon in each of the second plurality of trenches being formed above the first surface of the semiconductor substrate; and forming alternating doped regions of the first conductivity type and the second conductivity type in each of the second plurality of trenches, the doped regions being alternately formed along the length of each corresponding trench in the second plurality of trenches.

[0011] These and other advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment of the invention, will be more fully understood from the following description and drawings.

[0012] In summary, compared with the prior art, the recessed polysilicon ESD diode for power MOSFET provided by the present invention has the following beneficial effects:

[0013] The recessed polysilicon ESD diode for power MOSFET of the present invention, first, by forming the ESD diode in the trench polysilicon layer, a protection structure can be realized without the need for a large silicon area. Specifically, the cross-sectional area of ​​the pn junction interface is expanded by providing a portion of the trench polysilicon layer above the surface of the semiconductor substrate. In this way, while increasing the cross-sectional area of ​​the ESD diode to improve the protection level of the protection structure, only a small step height is produced. Second, the manufacturing process enables the trench structure for the ESD diode to be formed after the trench structure for the power transistor, while minimizing the impact on the topography of the power transistor trench formation. This enables the ESD diode manufacturing process to be decoupled from the power transistor manufacturing process, and enables the trench polysilicon layer of the ESD diode to be formed protruding above the surface of the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Various embodiments of the present invention are disclosed in the following detailed description and accompanying drawings. Although the accompanying drawings depict various examples of the present invention, the present invention is not limited to the depicted examples. It should be understood that in the accompanying drawings, the same reference numerals represent the same structural elements. In addition, it should be understood that the descriptions in the drawings are not necessarily to scale.

[0015] Figure 1 A schematic diagram of a power transistor with ESD protection circuitry is shown in some examples.

[0016] Figure 2 A perspective view showing a power transistor and an ESD protection structure formed on a semiconductor substrate in some examples.

[0017] Figure 3 A perspective view showing a power transistor and an ESD protection structure formed in a trench polysilicon layer in an embodiment of the present invention.

[0018] Figure 4 A perspective view showing a power transistor and an ESD protection structure formed in a trench polysilicon layer in an embodiment of the present invention.

[0019] Figure 5 In some embodiments, Figure 3 The ESD protection structure is shown in a cross-sectional view along line AA'.

[0020] Figure 6 A cross-sectional view of an ESD protection structure in an alternative embodiment is shown.

[0021] Figure 7(a) to Figure 7(t) A cross-sectional view showing a manufacturing process for forming a power transistor incorporating an ESD protection structure in an embodiment of the present invention.

[0022] Figure 8 A simplified layout diagram of a power transistor including an ESD protection structure in accordance with an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0023] According to various aspects of the present invention, a protection structure for a power transistor includes one or more pairs of back-to-back pn junction diodes formed in a trench polysilicon layer, wherein the trench polysilicon layer is disposed in a trench formed in a semiconductor substrate. At least a portion of the trench polysilicon layer protrudes above the top surface of the semiconductor substrate. Alternating N-type doped regions and P-type doped regions are formed in the trench polysilicon layer along the length of the trench. When coupled across the gate terminal and source terminal of the power transistor, the protection structure can be advantageously applied to protect the power transistor from ESD events. In this specification, the pn junction diode of the protection structure is sometimes referred to as an ESD diode or a polysilicon ESD diode.

[0024] The protection structure in the embodiments of the present invention achieves many advantages over conventional structures. First, by forming an ESD diode in a trench polysilicon layer, the protection structure can be implemented without requiring a large silicon area. Specifically, the cross-sectional area of ​​the pn junction interface is expanded by providing a portion of the trench polysilicon layer above the surface of the semiconductor substrate. In this way, while increasing the cross-sectional area of ​​the ESD diode to improve the protection level of the protection structure, only a small step height is produced. Second, the manufacturing process enables the trench structure for the ESD diode to be formed after the trench structure for the power transistor, with minimal impact on the topography of the power transistor trench formation. This enables the ESD diode manufacturing process to be decoupled from the power transistor manufacturing process, and enables the trench polysilicon layer of the ESD diode to be formed protruding above the surface of the semiconductor substrate. These and other advantages of the protection structure and manufacturing method will be described in more detail below.

[0025] Figure 3 A perspective view showing a power transistor and an ESD protection structure formed in a trench polysilicon layer in an embodiment of the present invention. Figure 3 , the power transistor 50 (also referred to as a "power MOSFET") is constructed as a vertical transistor having a gate polysilicon layer 54, which is disposed in one or more trenches (herein referred to as "device trenches") forming a gate terminal. The gate polysilicon layer 54 is disposed in a device trench formed in a device region of a semiconductor substrate 52. The gate polysilicon layer 54 is isolated from the semiconductor substrate 52 by a gate dielectric layer 55. In the present embodiment, the power transistor is an N-type field effect transistor, and the semiconductor substrate 52 is a lightly doped N-type epitaxial layer formed on a heavily doped N-type substrate and serves as a drain terminal of the power transistor. An ohmic contact to the drain terminal of the power transistor can be provided from the back side of the semiconductor substrate. A body region 56 is formed in the top of the semiconductor substrate 52. A source region 58 is formed in the body region 56. For example, the body region 56 is a P-type doped region, and the source region 58 is a heavily doped N-type doped region or an N+ doped region. The body region 56 is more lightly doped than the source region 58, but more heavily doped than the semiconductor substrate 52. By configuring in this way, a gate voltage sufficient to invert the body region adjacent to the gate polysilicon layer 54 is applied to the gate terminal, forming a trench region on the sidewalls of the gate polysilicon layer in the body region. The power transistor 50 has a vertical current path between the drain (substrate 52) and the source region 58, through the inverted trench region in the body region 56.

[0026] In an embodiment of the present invention, the ESD protection structure 60 is formed on the same semiconductor substrate 52 as the power transistor 50. The ESD protection structure 60 is configured as a back-to-back polysilicon diode (referred to herein as an "ESD diode") in a trench polysilicon layer 65, which is disposed in a trench (referred to herein as an "ESD trench") formed in an ESD region of the semiconductor substrate 52, separated from a device region where the power transistor 50 is formed. The trench polysilicon layer 65 in the ESD trench is isolated from the semiconductor substrate 52 by a dielectric liner layer 66. In some embodiments, the dielectric liner layer 66 is a thick dielectric layer, such as a silicon oxide (SiO2) layer. The thickness of the dielectric liner layer 66 is selected to achieve a desired ESD protection level for the ESD diode.

[0027] In this specification, for the convenience of reference to the accompanying drawings, a Cartesian coordinate reference system is used, wherein the Z direction is perpendicular to the plane of the semiconductor surface, and the X direction and the Y direction are orthogonal to the Z direction and are orthogonal to each other, as shown in the accompanying drawings. Typically, a groove in a semiconductor substrate refers to a long and narrow groove formed in a semiconductor substrate. In the present embodiment, each ESD groove has a length L extending in a first direction (Y direction) of the semiconductor substrate and a width W extending in a second direction (X direction) of the semiconductor substrate orthogonal to the first direction and on the same plane as the first direction. The length L of the ESD groove is much greater than the width W of the ESD groove. In other words, the length of the ESD groove refers to the long dimension of the groove, and the width of the ESD groove refers to the narrow dimension of the groove. Finally, the ESD groove has a depth in a third direction (Z direction). In an embodiment of the present invention, the depth of the ESD groove is greater than the depth of the device groove forming the power transistor 50.

[0028] In an embodiment of the present invention, the trench polysilicon layer 65 is formed in the ESD trench and also includes a portion of the polysilicon layer extending above the top surface of the semiconductor substrate 52. It is noteworthy that the gate polysilicon layer 54 forming the gate terminal of the power transistor is completely formed in the trench and does not extend above the top surface of the semiconductor substrate 52. However, in an embodiment of the present invention, the trench polysilicon layer 65 forming the ESD diode is formed with a portion extending above the top surface of the semiconductor substrate (in the Z direction). This configuration has the effect of maximizing the cross-sectional area (XZ plane) of the ESD diode, thereby improving the ESD protection level of the ESD diode.

[0029] In order to form an ESD diode, alternating N-type doped regions 62 and P-type doped regions 64 are formed in the trench polysilicon layer 65 to form a pn junction diode connected back to back. In some embodiments, the N-type doped region 62 is more heavily doped than the P-type doped region 64. In an embodiment of the present invention, the N-type doped region and the P-type doped region are alternately formed along the length of each ESD trench, that is, along the Y direction of the ESD trench. An appropriate number of N and P doped regions are used to form a desired diode string in the ESD protection structure. For example, in this illustration, two N-type and two P-type doped regions are provided in each ESD trench, and thereby a diode string of diodes D1, D2 and D3 is formed, as shown in the figure. It can be understood that Figure 3 Only a portion of the power transistor and the ESD protection structure are shown. The complete ESD protection structure may include additional N / P doped regions and / or additional ESD trenches.

[0030] although Figure 3 It is not shown, but it is understood that the first N-type doped region forming the cathode of the first diode in the diode string will be connected to the gate terminal (gate polysilicon layer 54) of the power transistor, for example, through a contact structure and a conductive interconnect. In addition, it is understood that the last N-type doped region forming the cathode of the last diode in the diode string will be similarly connected to the source terminal 58 of the power transistor through a contact structure or a conductive interconnect.

[0031] exist Figure 3 In the illustrated embodiment, the ESD protection structure includes two ESD trenches, each of which is formed with a trench polysilicon layer 65. It should be understood that in other embodiments, a single ESD trench or multiple ESD trenches can be used to construct the ESD protection structure. The N / P doped region formed in the trench polysilicon layer 65 in each ESD trench forms a diode string of pn junction diodes connected back to back. The diode strings formed in the multiple ESD trenches can be connected in series or in parallel to each other, depending on the desired ESD protection voltage and other performance characteristics, such as the resistance of the ESD protection structure.

[0032] In addition, Figure 3 In the illustrated embodiment, the N-type doped regions 62 and the P-type doped regions 64 in the plurality of ESD trenches are arranged horizontally in the first direction (Y direction). That is, the N-doped region 62 in the first ESD trench is aligned with the N-doped region 62 of the adjacent ESD trench, for example, along the line A-A'. The P-doped regions 64 are similarly arranged. In other embodiments, the N-type doped regions 62 and the P-type doped regions 64 may be staggered or offset in the first direction (Y direction), such as Figure 4 shown. Figure 4 1 is a perspective view of a power transistor and an ESD protection structure formed in a trench polysilicon layer in an alternative embodiment of the present invention. To simplify the discussion, Figure 3 and Figure 4 Like reference numerals are used for like elements in the reference Figure 4 The ESD protection structure 70 includes Figure 3 The ESD protection structure 60 is formed in the same manner as the ESD diode in the ESD trench. Figure 4 In the illustrated embodiment, the N-type doped regions 62 and the P-type doped regions 64 in the plurality of ESD trenches are horizontally staggered or offset in a first direction (direction Y). Thus, along line BB', the N-doped region 62 in the first ESD trench is aligned with the P-doped region 64 in the adjacent ESD trench.

[0033] Figure 5 In some embodiments Figure 3 A cross-sectional view of the ESD protection structure along line A-A'. Figure 5 , along the line A-A', the ESD protection structure includes a trench polysilicon layer, and the N-type doped region 62 of the ESD diode is formed in two adjacent ESD trenches. The N-type doped region 62 formed in the ESD trench is isolated from the semiconductor substrate 52 by a dielectric liner layer 66. Figure 5 In the cross-sectional view of FIG. 1 , the ESD protection structure is covered by an interlayer dielectric layer 68 (eg, an LTO or BPSG layer). In the case where the N-type doping region and the P-type doping region are alternately formed, as shown in FIG. Figure 4 As shown, the cross-sectional view along line BB′ will include the trench polysilicon layer having the N-type doped region 62 and the P-type dopant region 64 formed in two adjacent ESD trenches.

[0034] Figure 6 1 shows a cross-sectional view of an ESD protection structure in an alternative embodiment. To simplify the discussion, Figure 3 and Figure 6 Like reference numerals are used for like elements in the reference Figure 6 , ESD protection structure 80 with Figure 3 The ESD protection structure 60 is formed in substantially the same manner as the ESD protection structure 60. In the present embodiment, the trench polysilicon layer 65 in which the N / P doped regions are formed includes a polysilicon capping layer 82, which spans across all ESD trenches to connect the trench polysilicon layers. In some embodiments, the polysilicon capping layer 82 is a portion of the same trench polysilicon layer 65 that is patterned to form a capping layer portion. For example, during an intermediate processing step of depositing the polysilicon layer into the ESD trench, the deposited polysilicon layer is thinned to a certain thickness, such as by chemical mechanical polishing, to leave a bridging portion. The remaining polysilicon layer is then patterned and etched to form the capping layer 82. The polysilicon capping layer 82 effectively increases the cross-sectional area of ​​the ESD diode.

[0035] Figure 7(a) to Figure 7(t)1 is a cross-sectional view illustrating a manufacturing process for forming a power transistor incorporating an ESD protection structure in an embodiment of the present invention. Figure 3 , Figure 4 and Figure 7(a) to Figure 7(t) Like elements in the are given like reference numerals. In particular, the manufacturing process described herein forms the device trench and gate polysilicon layer before forming the ESD trench and trench polysilicon layer for the ESD diode, which has the advantage of allowing the ESD trench polysilicon layer to be formed to extend slightly above the surface of the semiconductor substrate to extend the cross-sectional area of ​​the ESD diode. The manufacturing process also minimizes the topography to enable the use of thin photoresists for pre-lithography of subsequent layers.

[0036] Referring to FIG. 7( a ), the manufacturing process starts with forming a device trench 104 in a device region 102 of a semiconductor substrate 52 . The device trench 104 may be formed by applying a mask to define an area for forming the trench and then performing an anisotropic dry etching process. Referring to FIG. 7( b ), after the device trench is formed, a gate dielectric layer 106 is formed on the surface of the semiconductor substrate 52 by a chemical vapor deposition (CVD) process or thermal growth. In one embodiment, the gate dielectric layer 106 is a silicon dioxide layer (SiO 2 ), and the gate dielectric layer 106 is also referred to as a gate oxide layer. Referring to FIG. 7( c ), a gate polysilicon layer 54 is formed in the device trench 104 . In some embodiments, a doped polysilicon layer is conformally deposited on the semiconductor substrate, and the deposited doped polysilicon layer is etched back so that only the polysilicon layer in the device trench 104 remains, thereby forming a gate polysilicon layer 54 . In some examples, the polysilicon layer may be deposited using a CVD process and etched back using a wet etch or dry etch process.

[0037] Referring to FIG. 7( d ), the gate polysilicon layer 54 is oxidized to form a cap oxide portion 108 on the polysilicon layer in each trench. For example, a dry or wet oxidation process may be used to perform gate polysilicon oxidation. In practice, the cap oxide portion 108 merges with the previously deposited gate oxide layer to form a continuous oxide layer. After the oxidation process, the surface of the semiconductor substrate 52 is substantially planarized. In this specification, for ease of reference, the portion of the oxide layer formed inside the device trench is referred to as the gate dielectric layer or gate oxide layer 106, and the portion of the oxide layer formed on the top of the gate polysilicon layer and the top of the semiconductor substrate is referred to as the cap oxide layer 108. Referring to FIG. 7( e ), for example, a silicon nitride layer 110 is deposited onto the semiconductor substrate 52 using a CVD process. At this stage, the manufacturing process has completed the formation of the trench gate structure for the power transistor. The manufacturing process is now performed to form an ESD trench structure for the ESD protection structure.

[0038] Referring to FIG. 7( f), an ESD mask 112 is applied, which covers and protects the structure formed in the device region 102 and exposes the region in the ESD region 114 where the ESD groove is to be formed. Referring to FIG. 7( g), with the mask 112 thus applied, the silicon nitride layer 110 and the cap oxide layer 108 in the exposed region are etched. Then, the manufacturing process forms an ESD groove 116 in the region exposed by the mask 112. For example, the silicon nitride layer 110 and the cap oxide layer 108 can be etched using a dry etching process of an applicable etching chemistry. The ESD groove 116 can be formed by performing an anisotropic dry etching process. In an embodiment of the present invention, the depth of the ESD groove 116 is deeper than the depth of the device groove. In addition, the width of the ESD groove 116 is wider than the width of the device groove.

[0039] In the present embodiment, the device trench is shown as having a rounded bottom, while the ESD trench 116 is shown as having a square bottom. It should be understood that the exact shape of the device and ESD trenches is a function of the etching process, and rounded or flat corners can be achieved by using different etching conditions. Typically, because the device trench is smaller, the trench typically has a rounded bottom. In addition, a rounded bottom is typically the goal of the gate polysilicon layer to reduce the electric field concentration that may appear at the sharp corners. On the other hand, the ESD trench is wider and deeper than the device trench, and the etching conditions can be conducive to a more open trench bottom. It should be understood that the profile of the ESD trench does not have to be a perfect rectangular trench bottom, and the drawings provided herein are for illustrative purposes only.

[0040] After the ESD trench is formed, any mask or photoresist layer is removed. Referring to FIG. 7( h), a dielectric liner layer 118 is deposited on the semiconductor substrate 52. In one example, the dielectric liner layer 118 is a TEOS oxide layer and is deposited using a CVD process. Referring to FIG. 7( i), a polysilicon layer 120 is deposited on the semiconductor substrate 52, for example using a CVD process. In the present embodiment, the polysilicon layer 120 is referred to as an ESD polysilicon layer. In the present embodiment, the ESD polysilicon layer 120 is deposited as undoped or very lightly doped. After deposition, an ESD implant is applied to dope the ESD polysilicon layer 120. In the present embodiment, the ESD implant introduces a P-type dopant into the ESD polysilicon layer 120. The amount of the ESD implant is selected to adjust the characteristics of the ESD polysilicon layer.

[0041] 7( j), the ESD polysilicon layer 120 is etched back, for example, by using a chemical mechanical polishing (CMP) process. In the present embodiment, the CMP process continues to the top of the dielectric liner layer 118, for example, by using the dielectric liner 118 as an etch stop. Thus, a trench polysilicon layer 65 is formed in the ESD trench. In addition, the trench polysilicon layer 65 has a height extending above the semiconductor substrate.

[0042] In forming the polysilicon capping layer ( Figure 6 ) In the case of the polysilicon portion bridging the trench, a CMP process is performed to etch back only a portion of the ESD polysilicon layer 120 from the top. The thinned ESD polysilicon layer 120 is then patterned and etched to form a polysilicon cap layer, such as Figure 6 shown.

[0043] Referring now to FIG. 7( k ), the dielectric liner layer 118 is etched back from the top, for example by using a dry etching process using the silicon nitride layer 110 as an etch stop layer. Then, referring to FIG. 7( l ), ​​the silicon nitride layer 118 is removed, for example by using a dry etching process. At this stage, a trench polysilicon layer 65 is formed, in which a portion of the polysilicon layer protrudes from the top surface of the semiconductor substrate 52. The amount of protrusion is a function of the dielectric liner layer and the silicon nitride layer that are now removed. The portion of the dielectric liner layer that remains in the ESD trench forms a dielectric liner layer 66 for isolating the trench polysilicon layer 65 from the semiconductor substrate 52.

[0044] At this stage, the gate polysilicon layer 54 and the trench polysilicon layer 65 may be annealed. The annealing process may be performed in a non-reactive environment, such as a high temperature. Referring to FIG. 7( m ), after the polysilicon is annealed, a body mask 122 is applied, which exposes an area for receiving a body implant 124. In this embodiment, the body implant is applied only to the device area. For example, the body implant 124 may be a lightly doped P-type implant. Referring to FIG. 7( n ), a body annealing process is performed on the body implant to anneal and diffuse the implanted dopants to form a body region 56. The annealing process may be performed in a non-reactive environment, such as a high temperature.

[0045] Referring to FIG. 7( o ), after the body annealing process, a source mask 126 is applied, which exposes an area for receiving a source implant 128. For example, the source implant 128 can be a heavily doped N-type implant. In this embodiment, the source implant is applied to the device area and the ESD area. Referring to FIG. 7( p ), a source annealing process is performed on the source implant to anneal and diffuse the implanted dopants to form a source region 58 in the power transistor and an N-type doped region 62 in the ESD diode. The annealing process can be performed in a non-reactive environment, such as a high temperature. Note that FIG. 7( p ) illustrates Figure 4 7( p ) shows an embodiment of an ESD diode in which N and p doped regions are interlaced. Thus, in the cross-sectional view of FIG. 7( p ), the trench polysilicon layer in the leftmost ESD trench is shown as an N-type doped region 62, while the trench polysilicon of the rightmost ESD trench is shown as a p-type doped region 64.

[0046] Referring to FIG. 7( q ), after the source annealing process, the power transistor and ESD diode formed thereby are encapsulated by the interlayer dielectric layer. In this embodiment, a low temperature oxide layer (LTO) 67 is deposited, followed by a borophosphosilicate glass (BPSG) layer 68. For example, a CVD process may be used to deposit these layers. After the BPSG deposition, the semiconductor structure may be planarized.

[0047] 7(r), a contact mask is applied to define the openings to be formed in the interlayer dielectric layer. A contact etching process, such as an anisotropic dry etching process, is then performed using the contact mask to form openings 132 leading to the terminals of the ESD diode and the power transistor. For example, a first contact opening 132a is formed for the N-type doped region 62 of the ESD diode, a second contact opening 132b is formed for the gate polysilicon layer 54, and a third contact opening 132c is formed for the source region 58.

[0048] Referring to FIG. 7( s ), a tungsten plug 134 is formed in the contact opening 132 . For example, the tungsten plug 134 may include a conductive adhesion layer, such as a titanium (Ti) or titanium nitride (TiN) layer, and then a tungsten filling layer, both of which are deposited by a CVD or PVD process. A conductive layer 136 is then deposited on the semiconductor structure. In one embodiment, the conductive layer 136 is an aluminum layer and may be deposited using a PVD process or evaporation. Referring to FIG. 7( t ), a metal mask is applied and the conductive layer 136 is etched using the metal mask to form a metal interconnect. For example, in this illustration, a first metal line 136 a connects the N-doped region 62 of the ESD diode to the gate polysilicon layer 54 , and a second metal line 136 b connects to the source region 58 of the power transistor and is also connected to another N-doped region of the ESD diode. At this stage, the manufacturing process for forming a power transistor and an ESD protection structure is completed.

[0049] Figure 8 FIG. 1 is a simplified layout diagram of a power transistor including an ESD protection structure in an embodiment of the present invention. Figure 8, the power transistor device 200 includes a gate polysilicon layer 54 formed in parallel device trenches 202 in a device region of a semiconductor substrate 52. The gate polysilicon layers 54 in the parallel device trenches 202 are connected together by end polysilicon portions formed in the trenches 204. An ESD protection structure is formed in an ESD trench 206 formed in the ESD region of the semiconductor substrate. For example, the ESD protection structure includes alternating N and P doped regions 62, 64 formed in the ESD trench 206. The ESD protection structure is connected to the power transistor by connecting the N-doped region 62a of the first ESD diode to the gate polysilicon layer, for example, through contacts and interconnects 210, and by connecting the N-doped region 62b of the last ESD diode to the source region 58 of the power transistor. In the power transistor device 200, the gate terminal is provided in a gate pad, and the source terminal is provided in a source pad on the top side of the device, while the drain terminal is provided on the back side of the device. In this embodiment, the diode strings in the two ESD trenches 206 are connected in parallel. Interconnect 210 is connected to the N-doped regions 62a on both diode strings, and interconnect 212 is connected to the N-doped regions 62 on both diode strings. With this configuration, the ESD protection structure is connected to protect the gate terminal of the power transistor 200.

[0050] The drawings provided herein are idealized representations for illustrating embodiments of the invention and are not meant to be actual views of any particular component, structure, or device. The drawings are not drawn to scale, and the dimensions and relative sizes and sizes of layers and regions may be exaggerated for clarity. It is expected that the shapes of the illustrations will vary. For example, an area illustrated as a box shape may generally have rough and / or nonlinear features. The sharp angles shown may be rounded. The same numbers refer to the same components throughout the text.

[0051] In this specification, for ease of description, spatial relative terms may be used herein, for example, "below", "below", "bottom", "above", "top", etc., as shown in the figure to describe the relationship of one element or feature to another element or feature. It should be understood that spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation shown in the figure. For example, if the device in the figure is turned over, the elements described as "below" or "below" other elements or features will be oriented as "above" other elements or features. Therefore, the exemplary term "below" can include directions above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are interpreted accordingly.

[0052] It should be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0053] In this detailed description, a process step described for one embodiment may be used for a different embodiment even if the process step is not explicitly described in the different embodiments. When a method comprising two or more defined steps is referred to herein, the defined steps may be performed in any order or simultaneously unless the context indicates or specific instructions are otherwise provided herein. In addition, unless the context indicates or otherwise provides clear instructions, the method may also include one or more other steps performed before any defined step, between two defined steps, or after all defined steps.

[0054] In this detailed description, various embodiments or examples of the present invention can be implemented in many ways, including as a process; an instrument; a system; and a composition of matter. A detailed description of one or more embodiments of the present invention and drawings illustrating the principles of the present invention are provided above. The present invention is described in conjunction with these embodiments, but the present invention is not limited to any embodiment. Many modifications and variations within the scope of the present invention are possible. The scope of the present invention is limited only by the claims, and the present invention includes many alternatives, modifications and equivalents. In order to provide a comprehensive understanding of the present invention, many specific details are set forth in the specification. These details are provided for illustrative purposes, and the present invention can be practiced according to the claims without some or all of these specific details. For the sake of clarity, technical materials known in the technical field related to the present invention are not described in detail so that the present invention will not be unnecessarily obscured. The present invention is defined by the appended claims.

Claims

1. A protection structure for a power transistor, the power transistor comprising a gate terminal, a first current terminal and a second current terminal, the protection structure comprising: at least one pair of pn junction diodes connected in a back-to-back configuration, the pn junction diodes being provided in a first portion of a semiconductor substrate, the pn junction diodes being formed in a first polysilicon layer disposed in a first trench formed in the semiconductor substrate, the first polysilicon layer being isolated from the semiconductor substrate by a first dielectric layer formed on sidewalls of the first trench, the first polysilicon layer having alternating doped regions of a first conductivity type and a second conductivity type along a length of the first trench, at least a portion of the first polysilicon layer being formed above a first surface of the semiconductor substrate, The first doped region of the first conductivity type in the first polysilicon layer is coupled to the gate terminal of the power transistor, and the second doped region of the first conductivity type in the first silicon layer is coupled to the second current terminal of the power transistor, and the first doped region and the second doped region are separated by at least a third doped region of the second conductivity type.

2. The protective structure according to claim 1, characterized in that: The length of the first trench extends along a first direction in the semiconductor substrate, and the width of the first trench extends in a second direction, the second direction is orthogonal to the first direction and is in the same plane as the first surface of the semiconductor substrate, and the length of the first trench is greater than the width.

3. The protective structure according to claim 1, characterized in that: A power transistor is provided in the second portion of the semiconductor substrate, the power transistor comprising: a second polysilicon layer formed in a second trench formed in the semiconductor substrate, the second polysilicon being isolated from the semiconductor substrate by a second dielectric layer; A body region of a second conductivity type is formed in the semiconductor substrate adjacent to the second trench and close to the first surface; and A source region of the first conductivity type is formed above the body region adjacent to the second trench, wherein the length of the second trench is equal to the length of the first trench.

4. The protective structure according to claim 3, characterized in that: A depth of the first trench extending into the semiconductor substrate opposite to the first surface is greater than a depth of the second trench.

5. The protective structure according to claim 3, characterized in that: The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

6. The protective structure according to claim 3, characterized in that: The thickness of the first dielectric layer is selected so as to provide a predetermined protection voltage of the protection structure.

7. The protective structure according to claim 3, characterized in that: The semiconductor substrate forms a first current terminal of the power transistor, and the source region forms a second current terminal of the power transistor, one of the first current terminal and the second current terminal is coupled to a first power supply voltage, the other of the first current terminal and the second current terminal is configured to drive a load, and the second polysilicon layer is configured as a gate terminal for receiving a control signal.

8. The protective structure according to claim 1, characterized in that: Also included are a plurality of pairs of pn junction diodes, each pair of pn junction diodes being connected in a back-to-back configuration, the plurality of pairs of pn junction diodes being formed in the first polysilicon layer in the first trench as alternating doped regions of the second conductivity type and the first conductivity type along the length of the first trench.

9. The protective structure according to claim 1, characterized in that: It also includes a plurality of pairs of pn junction diodes, each pair of pn junction diodes being connected in a back-to-back configuration, the plurality of pairs of pn junction diodes being formed in a plurality of polysilicon layers provided in a plurality of trenches in the semiconductor substrate, a subset of the plurality of pn junction diodes being formed in a given polysilicon layer in the corresponding trench as alternating doped regions of the first conductivity type and the second conductivity type along the length of the first trench, and at least a portion of each of the plurality of subset polysilicon layers being formed above the first surface of the semiconductor substrate.

10. The protective structure according to claim 9, characterized in that: The lengths of the plurality of trenches extend in a first direction in the semiconductor substrate, and the width of each trench extends in a second direction, the second direction being orthogonal to the first direction and within the same plane as the first surface of the semiconductor substrate, the length of the trench being greater than the width.

11. The protective structure according to claim 10, characterized in that: The alternating doped regions of the first conductivity type and the second conductivity type in a first trench among the plurality of trenches are aligned with the alternating doped regions of the first conductivity type in a second trench among the plurality of trenches in the first direction.

12. The protective structure according to claim 10, characterized in that: The alternating doped regions of the first conductivity type and the second conductivity type in a first trench of the plurality of trenches are offset in the first direction from the alternating doped regions of the first conductivity type in a second trench of the plurality of trenches.

13. The protective structure according to claim 9, characterized in that: The plurality of polysilicon layers of the pn junction diode are connected together by a polysilicon cap layer formed over the plurality of silicon layers over the first surface of the semiconductor substrate.

14. A method for manufacturing a protection structure of a power transistor, characterized in that: The power transistor comprises a gate terminal, a first current terminal and a second current terminal, the method comprising: forming a first plurality of trenches in a first region of a semiconductor substrate, the first plurality of trenches having a length extending in a first direction; forming a first polysilicon layer in the first plurality of trenches, the first polysilicon layer being isolated from the semiconductor substrate by a first dielectric layer; After forming the first polysilicon layer, forming a second plurality of trenches in a second region of the semiconductor substrate, the second plurality of trenches having a length extending in the first direction; forming a second dielectric layer in the second plurality of trenches and over the first surface of the semiconductor substrate in the first region; forming a second polysilicon layer in the second plurality of trenches and over the second dielectric layer, the second polysilicon being isolated from the semiconductor substrate by the second dielectric layer; removing portions of the second polysilicon layer and the second dielectric layer from the first region of the semiconductor substrate, the remaining portions of the second polysilicon film being formed in the second plurality of trenches, and at least a portion of the second polysilicon in each of the second plurality of trenches being formed above the first surface of the semiconductor substrate; and Alternating doped regions of a first conductivity type and a second conductivity type are formed in each trench of the second plurality of trenches, the doped regions being alternately formed along a length of each respective trench of the second plurality of trenches.

15. The method according to claim 14, characterized in that Forming the alternating doped regions of the first and second conductivity types in each trench of the second plurality of trenches comprises: After forming the second polysilicon layer, doping the second polysilicon layer with a dopant of the first conductivity type; Using a mask, patterning a mask layer to cover portions of the second polysilicon layer; using the mask layer, doping exposed portions of the second polysilicon layer with a dopant to have a second conductivity type; and The semiconductor substrate is annealed to form the alternating doped regions.

16. The method according to claim 14, characterized in that Forming the second plurality of trenches includes forming the second plurality of trenches having a depth extending into the semiconductor substrate opposite the first surface that is greater than a depth of the first plurality of trenches.

17. The method according to claim 14, characterized in that The thickness of the second dielectric layer is greater than the thickness of the first dielectric layer.

18. The method according to claim 15, characterized in that Forming the alternating doped regions of the first and second conductivity types in each trench of the second plurality of trenches comprises: Alternating doped regions of the first conductivity type and the second conductivity type are formed in a first trench of the second plurality of trenches, the alternating doped regions being arranged in the first direction.

19. The method according to claim 15, characterized in that Forming the alternating doped regions of the first and second conductivity types in each trench of the second plurality of trenches comprises: Alternating doped regions of the first and second conductivity types are formed in a first trench of the second plurality of trenches, the alternating doped regions being offset in the first direction from alternating dopant regions of the first and second conductivity types in a second trench of the second plurality of trenches.

20. The method of claim 14, wherein: Also includes: removing the second polysilicon layer formed on the first region and the second region of the semiconductor substrate by thinning; and The remaining portion of the second polysilicon layer over the first region of the semiconductor substrate is removed, the remaining portion of the second polysilicon film including portions of the second polysilicon layer connected to the second plurality of trenches.

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