A system and method for solving latchup in anti-reverse connection circuit application

Abstract

The invention discloses a system and method for solving latchup in an anti-reverse connection circuit application, and relates to the technical field of integrated circuits. The system and method include: a high-voltage PMOS tube M0, a high-voltage NMOS tube M1, a high-voltage NMOS tube M2, a POLY resistor Rlatchup and a POLY resistor RM2. The high-voltage PMOS tube M0 is composed of a P-type substrate, an N-type buried layer, a deep high-voltage P well, a deep high-voltage N well and a shallow N well. The high-voltage NMOS tube M1 is composed of a P-type substrate, an N-type buried layer, a deep high-voltage P well, a deep high-voltage N well and a high-voltage N well. The high-voltage NMOS tube M2 is composed of a P-type substrate, an N-type buried layer, a deep high-voltage P well, a deep high-voltage N well and a high-voltage N well. The POLY resistor and the POLY resistor RM2 are composed of conventional P-type POLY resistors. The invention provides a method for solving latchup in an anti-reverse connection circuit application. The system limits the current of the NPN by connecting a POLY resistor in series between the D potential of the high-voltage NMOS tube and the D end of the high-voltage NMOS tube and by connecting a POLY resistor in series on the deep high-voltage P well of the high-voltage NMOS tube, thereby reducing the power consumption from VCC to GND to achieve the purpose of protecting the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a system and method for solving latchup in an anti-reverse connection circuit application. Background Art

[0002] The traditional latch-up effect principle is produced by the NPNP structure composed of the active area of ​​NMOS, shallow P-type isolation ring, shallow N-well and active area of ​​PMOS. When the collector current of one of the transistors suddenly increases to a certain value due to external interference, it will be fed back to the other transistor, so that the two transistors are triggered to turn on, and a low-impedance path will be formed between the power supply and the ground, forming positive feedback to form latch-up, causing electrical overload and device damage.

[0003] Therefore, people need a system and method for solving latchup in anti-reverse connection circuit application to solve the above problems. Summary of the invention

[0004] The object of the present invention is to provide a system and method for solving latchup in anti-reverse connection circuit application, so as to solve the problems raised in the above background technology.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions: a system for solving latchup in anti-reverse connection circuit applications, the system comprising: a high-voltage PMOS tube M0, a high-voltage NMOS tube M1, a high-voltage NMOS tube M2, a POLY resistor Rlatchup and a POLY resistor RM2; wherein the POLY resistor Rlatchup is connected in series between the high-voltage NMOS tube M1 and the high-voltage NMOS tube M2, and the POLY resistor RM2 is connected in series between the high-voltage NMOS tube M1 and the GND;

[0006] A POLY resistor Rlatchup is connected in series between the high-voltage NMOS tube M1 and the high-voltage NMOS tube M2, and a POLY resistor RM2 is connected in series between the deep high-voltage P well (HVPW) of the high-voltage NMOS tube M1 and GND.

[0007] Provide metal layer (METAL1), metal layer (METAL2), metal layer (METAL3), and metal layer (METAL4), including different types of metal routing. For example, metal layer (METAL1), metal layer (METAL2), metal layer (METAL3), and metal layer (METAL4) can be used as connections between high-voltage PMOS tube M0, high-voltage NMOS tube M1, and high-voltage NMOS tube M2, and can also be used as routing for power supply VCC and power supply GND.

[0008] The high-voltage PMOS tube M0 is formed on the P-type substrate P_sub with a deep high-voltage P-well HVPW isolation ring connected to GND, and an N-type buried layer NBL is formed on the P-type substrate P_sub. A deep high-voltage N-well DHVNW and a shallow N-well NW5V are grown on the N-type buried layer as the source terminal S and body terminal B of the high-voltage PMOS tube M0 connected to the power supply VCC. A deep high-voltage P-well HVPW is grown on the N-type buried layer as the drain terminal D of the high-voltage PMOS tube M0 and connected to the source terminal S of the high-voltage NMOS tube M1 as the output terminal OUT; the source terminal S and the drain terminal D of the high-voltage PMOS tube M0 are P+ ion implanted, and the body terminal B is N+ ion implanted;

[0009] The high-voltage NMOS tube M1 forms a deep high-voltage P-well HVPW isolation ring on a P-type substrate P_sub and connects to one end of a POLY resistor RM2; forms an N-type buried layer NBL on the P-type substrate P_sub, grows a deep high-voltage N-well DHVNW on the N-type buried layer as a D potential isolation ring connected to a POLY resistor Rlatchup, forms a deep high-voltage P-well HVPW on the N-type buried layer NBL, forms a source terminal S and a body terminal B in the well and connects to a drain terminal D of the high-voltage PMOS tube M0 as an output terminal OUT; forms a high-voltage N-well HVNW on the N-type buried layer NBL, forms a drain terminal D in the well and connects to the D potential isolation ring of the deep high-voltage N-well DHVNW of the high-voltage NMOS tube M2, the drain terminal D of the high-voltage NMOS tube M2, and one end of the POLY resistor Rlatchup; the source terminal S and the drain terminal D of the high-voltage NMOS tube M1 are N+ ion implanted, and the body terminal B is P+ ion implanted;

[0010] The N-type buried layer NBL of the high-voltage PMOS tube M0, the deep high-voltage P well HVPW of the high-voltage PMOS tube M0 and the N-type buried layer NBL of the high-voltage NMOS tube M1 form an NPN structure; the N-type buried layer NBL of the high-voltage PMOS tube M0, the deep high-voltage P well HVPW of the high-voltage NMOS tube M1 and the N-type buried layer NBL of the high-voltage NMOS tube M1 form an NPN structure.

[0011] One end of the POLY resistor Rlatchup is connected to the deep high-voltage N well DHVNW isolation ring D potential of the high-voltage NMOS tube M1, and the other end is connected to the drain terminal D of the high-voltage NMOS tube M1 and the drain terminal D of the high-voltage NMOS tube M2 and the D potential isolation ring of the deep high-voltage N well DHVNW of the high-voltage NMOS tube M2.

[0012] One end of the POLY resistor RM2 is connected to the deep high-voltage P-well HVPW isolation ring of the high-voltage NMOS tube M1, and the other end of the high-voltage PMOS tube M0 deep high-voltage P-well HVPW isolation ring, the deep high-voltage P-well HVPW isolation ring of the high-voltage NMOS tube M2, the source terminal S, the body terminal D, and the P-type substrate P_sub are connected to GND together;

[0013] The high-voltage NMOS tube M2 forms a deep high-voltage P-well HVPW isolation ring on the P-type substrate P_sub and connects to GND; forms an N-type buried layer NBL on the P-type substrate P_sub, forms a high-voltage N-well HVNW on the N-type buried layer NBL and forms a drain terminal D in the well; grows a D potential isolation ring of the deep high-voltage N-well DHVNW on the N-type buried layer and connects the drain terminal D, the drain terminal D of the high-voltage NMOS tube M1, and one end of the POLY resistor Rlatchup together, forms a deep high-voltage P-well HVPW on the N-type buried layer NBL and forms a source terminal S and a body terminal B in the well and connects to GND; the source terminal S and the drain terminal D of the high-voltage NMOS tube M1 are N+ ion implanted, and the body terminal B is P+ ion implanted;

[0014] One end of the POLY resistor RM2 is connected to the deep high voltage P well HVPW of the high voltage NMOS tube M1, and the other end is connected to GND together with the deep high voltage P well PSUB of the high voltage PMOS tube M0 and the deep high voltage P well PSUB of the high voltage NMOS tube M2.

[0015] The drain terminal D of the high-voltage NMOS transistor M1 is connected with the drain terminal D of the high-voltage NMOS transistor M2 and the D potential of the deep high-voltage N well DHVNW of the high-voltage NMOS transistor M2.

[0016] The drain terminal D of the high-voltage PMOS tube M0 and the source terminal S of the deep high-voltage P well HVPW of the high-voltage NMOS tube M1 are connected together to form the output OUT.

[0017] The high-voltage PMOS tube M0 is composed of a P-type substrate P_sub, an N-type buried layer NBL, a deep high-voltage P-well HVPW, a deep high-voltage N-well DHVNW and a shallow N-well NW5V, wherein the D end is the drain end of the high-voltage PMOS tube M0, the S end is the source end of the high-voltage PMOS tube M0, and the B end is the body end of the high-voltage PMOS tube M0;

[0018] The high-voltage NMOS tube M1 is composed of a P-type substrate P_sub, an N-type buried layer NBL, a deep high-voltage P-well HVPW, a deep high-voltage N-well DHVNW, and a high-voltage N-well HVNW, wherein D is the drain terminal of the high-voltage PMOS tube M0, S is the source terminal of the high-voltage PMOS tube M0, and B is the body terminal of the high-voltage PMOS tube M0;

[0019] The high-voltage NMOS tube M2 is composed of a P-type substrate P_sub, an N-type buried layer NBL, a deep high-voltage P-well HVPW, a deep high-voltage N-well DHVNW, and a high-voltage N-well HVNW, wherein D is the drain terminal of the high-voltage PMOS tube M0, S is the source terminal of the high-voltage PMOS tube M0, and B is the body terminal of the high-voltage PMOS tube M0;

[0020] The POLY resistor Rlatchup and the POLY resistor RM2 are composed of conventional P-type POLY resistors.

[0021] A method for solving latchup in anti-reverse connection circuit application: GND is connected to positive, OUT port is connected to negative, at this time HVNGC1 is pulled to OUT level, HVNGC0 is both at GND level, M1 and M2 are both closed;

[0022] When VCC and GND are connected to 24V high voltage and OUT is a negative voltage, HVNGC1 is higher than OUT in this application, and M1 is turned on, so there will be current flowing to OUT through GND, which will cause negative voltage, causing the parasitic PNP to turn on, and the conduction voltage drop of RM2 to further increase. The parasitic NPN is turned on, and the current from VCC to OUT gradually increases. Although this current will be affected by RM2 and the application conditions (the influence of the load from OUT to GND), under the condition of high voltage, it will form high power, which will lead to bad chips;

[0023] The lower tube will also form a latchup with the P tube. From VCC to GND, it is separated by metal METAL in the layout, and there is enough distance, so it will not cause latchup.

[0024] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: the present invention provides a method for solving latchup in an anti-reverse connection circuit application, the method comprising: a high-voltage PMOS tube (M0), a high-voltage NMOS tube (M1), a high-voltage NMOS tube (M2), a POLY resistor (Rlatchup), and a POLY resistor (RM2). The present invention effectively limits the current of the NPN by connecting a POLY resistor (Rlatchup) in series between the D potential of the high-voltage NMOS tube (M1) and the D end of the high-voltage NMOS tube (M1) and connecting a POLY resistor (RM2) in series on a deep high-voltage P well (HVPW) of the high-voltage NMOS tube (M1), thereby reducing the power consumption from VCC to GND and achieving the purpose of protecting the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0026] Figure 1 A cross-sectional diagram of a layout for solving latchup in an anti-reverse connection circuit application of the present invention;

[0027] Figure 2 This is a schematic diagram of the traditional latchup structure;

[0028] Figure 3 A schematic diagram of the principle structure of solving latchup in an anti-reverse connection circuit application of the present invention;

[0029] Figure 4The present invention is a schematic diagram of a circuit structure for solving latchup in an anti-reverse connection circuit application. DETAILED DESCRIPTION

[0030] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0031] See also Figure 1 and Figure 2 The present invention provides a technical solution: a system for solving latchup in an anti-reverse connection circuit application, the system comprising: a high-voltage PMOS tube M0, a high-voltage NMOS tube M1, a high-voltage NMOS tube M2, a POLY resistor Rlatchup and a POLY resistor RM2; wherein the POLY resistor Rlatchup is connected in series between the high-voltage NMOS tube M1 and the high-voltage NMOS tube M2, and the POLY resistor RM2 is connected in series between the high-voltage NMOS tube M1 and the GND

[0032] A POLY resistor Rlatchup is connected in series between the high-voltage NMOS tube M1 and the high-voltage NMOS tube M2, and a POLY resistor RM2 is connected in series between the deep high-voltage P well (HVPW) of the high-voltage NMOS tube M1 and GND.

[0033] Provide metal layer (METAL1), metal layer (METAL2), metal layer (METAL3), and metal layer (METAL4), including different types of metal routing. For example, metal layer (METAL1), metal layer (METAL2), metal layer (METAL3), and metal layer (METAL4) can be used as connections between high-voltage PMOS tube M0, high-voltage NMOS tube M1, and high-voltage NMOS tube M2, and can also be used as routing for power supply VCC and power supply GND.

[0034] The high-voltage PMOS tube M0 is formed on the P-type substrate P_sub with a deep high-voltage P-well HVPW isolation ring connected to GND, and an N-type buried layer NBL is formed on the P-type substrate P_sub. A deep high-voltage N-well DHVNW and a shallow N-well NW5V are grown on the N-type buried layer as the source terminal S and body terminal B of the high-voltage PMOS tube M0 connected to the power supply VCC. A deep high-voltage P-well HVPW is grown on the N-type buried layer as the drain terminal D of the high-voltage PMOS tube M0 and connected to the source terminal S of the high-voltage NMOS tube M1 as the output terminal OUT; the source terminal S and the drain terminal D of the high-voltage PMOS tube M0 are P+ ion implanted, and the body terminal B is N+ ion implanted;

[0035] The high-voltage NMOS tube M1 forms a deep high-voltage P-well HVPW isolation ring on a P-type substrate P_sub and connects to one end of a POLY resistor RM2; forms an N-type buried layer NBL on the P-type substrate P_sub, grows a deep high-voltage N-well DHVNW on the N-type buried layer as a D potential isolation ring connected to a POLY resistor Rlatchup, forms a deep high-voltage P-well HVPW on the N-type buried layer NBL, forms a source terminal S and a body terminal B in the well and connects to a drain terminal D of the high-voltage PMOS tube M0 as an output terminal OUT; forms a high-voltage N-well HVNW on the N-type buried layer NBL, forms a drain terminal D in the well and connects to the D potential isolation ring of the deep high-voltage N-well DHVNW of the high-voltage NMOS tube M2, the drain terminal D of the high-voltage NMOS tube M2, and one end of the POLY resistor Rlatchup; the source terminal S and the drain terminal D of the high-voltage NMOS tube M1 are N+ ion implanted, and the body terminal B is P+ ion implanted;

[0036] The N-type buried layer NBL of the high-voltage PMOS tube M0, the deep high-voltage P well HVPW of the high-voltage PMOS tube M0 and the N-type buried layer NBL of the high-voltage NMOS tube M1 form an NPN structure; the N-type buried layer NBL of the high-voltage PMOS tube M0, the deep high-voltage P well HVPW of the high-voltage NMOS tube M1 and the N-type buried layer NBL of the high-voltage NMOS tube M1 form an NPN structure.

[0037] One end of the POLY resistor Rlatchup is connected to the deep high-voltage N well DHVNW isolation ring D potential of the high-voltage NMOS tube M1, and the other end is connected to the drain terminal D of the high-voltage NMOS tube M1 and the drain terminal D of the high-voltage NMOS tube M2 and the D potential isolation ring of the deep high-voltage N well DHVNW of the high-voltage NMOS tube M2.

[0038] One end of the POLY resistor RM2 is connected to the deep high-voltage P-well HVPW isolation ring of the high-voltage NMOS tube M1, and the other end of the high-voltage PMOS tube M0 deep high-voltage P-well HVPW isolation ring, the deep high-voltage P-well HVPW isolation ring of the high-voltage NMOS tube M2, the source terminal S, the body terminal D, and the P-type substrate P_sub are connected to GND together;

[0039] The high-voltage NMOS tube M2 forms a deep high-voltage P-well HVPW isolation ring on the P-type substrate P_sub and connects to GND; forms an N-type buried layer NBL on the P-type substrate P_sub, forms a high-voltage N-well HVNW on the N-type buried layer NBL and forms a drain terminal D in the well; grows a D potential isolation ring of the deep high-voltage N-well DHVNW on the N-type buried layer and connects the drain terminal D, the drain terminal D of the high-voltage NMOS tube M1, and one end of the POLY resistor Rlatchup together, forms a deep high-voltage P-well HVPW on the N-type buried layer NBL and forms a source terminal S and a body terminal B in the well and connects to GND; the source terminal S and the drain terminal D of the high-voltage NMOS tube M1 are N+ ion implanted, and the body terminal B is P+ ion implanted;

[0040] One end of the POLY resistor RM2 is connected to the deep high voltage P well HVPW of the high voltage NMOS tube M1, and the other end is connected to GND together with the deep high voltage P well PSUB of the high voltage PMOS tube M0 and the deep high voltage P well PSUB of the high voltage NMOS tube M2.

[0041] The drain terminal D of the high-voltage NMOS transistor M1 is connected with the drain terminal D of the high-voltage NMOS transistor M2 and the D potential of the deep high-voltage N well DHVNW of the high-voltage NMOS transistor M2.

[0042] The drain terminal D of the high-voltage PMOS tube M0 and the source terminal S of the deep high-voltage P well HVPW of the high-voltage NMOS tube M1 are connected together to form the output OUT.

[0043] The high-voltage PMOS tube M0 is composed of a P-type substrate P_sub, an N-type buried layer NBL, a deep high-voltage P-well HVPW, a deep high-voltage N-well DHVNW and a shallow N-well NW5V, wherein the D end is the drain end of the high-voltage PMOS tube M0, the S end is the source end of the high-voltage PMOS tube M0, and the B end is the body end of the high-voltage PMOS tube M0;

[0044] The high-voltage NMOS tube M1 is composed of a P-type substrate P_sub, an N-type buried layer NBL, a deep high-voltage P-well HVPW, a deep high-voltage N-well DHVNW, and a high-voltage N-well HVNW, wherein D is the drain terminal of the high-voltage PMOS tube M0, S is the source terminal of the high-voltage PMOS tube M0, and B is the body terminal of the high-voltage PMOS tube M0;

[0045] The high-voltage NMOS tube M2 is composed of a P-type substrate P_sub, an N-type buried layer NBL, a deep high-voltage P-well HVPW, a deep high-voltage N-well DHVNW, and a high-voltage N-well HVNW, wherein D is the drain terminal of the high-voltage PMOS tube M0, S is the source terminal of the high-voltage PMOS tube M0, and B is the body terminal of the high-voltage PMOS tube M0;

[0046] The POLY resistor Rlatchup and the POLY resistor RM2 are composed of conventional P-type POLY resistors.

[0047] The S end of the high-voltage PMOS tube M0, the N-type buried layer NBL, and the deep high-voltage P well HVPW form a PNP structure.

[0048] A method to solve latchup in anti-reverse connection circuit application: GND is connected to positive, OUT port is connected to negative, then HVNGC1 is pulled to OUT level, HVNGC0 is both at GND level, M1 and M2 are both closed, such as Figure 4 As shown, reverse connection without leakage is achieved;

[0049] When VCC and GND are connected to 24V high voltage and OUT is negative voltage, HVNGC1 is higher than OUT in this application, M1 is turned on, so current will flow through GND to OUT port, causing Figure 1 The P0 point is a negative voltage, which causes the parasitic PNP to turn on. The on-state voltage drop of RM2 is further increased, and the parasitic NPN is turned on. The current from VCC to the OUT port gradually increases. Although this current will be affected by RM2 and the application conditions (the load from the OUT port to GND), under high voltage conditions, high power will be formed, which will lead to a bad chip.

[0050] The lower tube will also form a latchup with the P tube. From VCC to GND, it is separated by metal METAL in the layout, and there is enough distance, so it will not cause latchup.

[0051] Embodiment 1: The system includes: a high-voltage PMOS tube M0, a high-voltage NMOS tube M1, a high-voltage NMOS tube M2, a POLY resistor Rlatchup and a POLY resistor RM2; wherein the POLY resistor Rlatchup is connected in series between the high-voltage NMOS tube M1 and the high-voltage NMOS tube M2, and the POLY resistor RM2 is connected in series between the high-voltage NMOS tube M1 and the GND;

[0052] A POLY resistor Rlatchup is connected in series between the high-voltage NMOS tube M1 and the high-voltage NMOS tube M2, and a POLY resistor RM2 is connected in series between the deep high-voltage P well (HVPW) of the high-voltage NMOS tube M1 and GND.

[0053] Provide metal layer (METAL1), metal layer (METAL2), metal layer (METAL3), and metal layer (METAL4), including different types of metal routing. For example, metal layer (METAL1), metal layer (METAL2), metal layer (METAL3), and metal layer (METAL4) can be used as connections between high-voltage PMOS tube M0, high-voltage NMOS tube M1, and high-voltage NMOS tube M2, and can also be used as routing for power supply VCC and power supply GND.

[0054] The high-voltage PMOS tube M0 is formed on the P-type substrate P_sub with a deep high-voltage P-well HVPW isolation ring connected to GND, and an N-type buried layer NBL is formed on the P-type substrate P_sub. A deep high-voltage N-well DHVNW and a shallow N-well NW5V are grown on the N-type buried layer as the source terminal S and body terminal B of the high-voltage PMOS tube M0 connected to the power supply VCC. A deep high-voltage P-well HVPW is grown on the N-type buried layer as the drain terminal D of the high-voltage PMOS tube M0 and connected to the source terminal S of the high-voltage NMOS tube M1 as the output terminal OUT; the source terminal S and the drain terminal D of the high-voltage PMOS tube M0 are P+ ion implanted, and the body terminal B is N+ ion implanted;

[0055] The high-voltage NMOS tube M1 forms a deep high-voltage P-well HVPW isolation ring on a P-type substrate P_sub and connects to one end of a POLY resistor RM2; forms an N-type buried layer NBL on the P-type substrate P_sub, grows a deep high-voltage N-well DHVNW on the N-type buried layer as a D potential isolation ring connected to a POLY resistor Rlatchup, forms a deep high-voltage P-well HVPW on the N-type buried layer NBL, forms a source terminal S and a body terminal B in the well and connects to a drain terminal D of the high-voltage PMOS tube M0 as an output terminal OUT; forms a high-voltage N-well HVNW on the N-type buried layer NBL, forms a drain terminal D in the well and connects to the D potential isolation ring of the deep high-voltage N-well DHVNW of the high-voltage NMOS tube M2, the drain terminal D of the high-voltage NMOS tube M2, and one end of the POLY resistor Rlatchup; the source terminal S and the drain terminal D of the high-voltage NMOS tube M1 are N+ ion implanted, and the body terminal B is P+ ion implanted;

[0056] The N-type buried layer NBL of the high-voltage PMOS tube M0, the deep high-voltage P well HVPW of the high-voltage PMOS tube M0 and the N-type buried layer NBL of the high-voltage NMOS tube M1 form an NPN structure; the N-type buried layer NBL of the high-voltage PMOS tube M0, the deep high-voltage P well HVPW of the high-voltage NMOS tube M1 and the N-type buried layer NBL of the high-voltage NMOS tube M1 form an NPN structure.

[0057] One end of the POLY resistor Rlatchup is connected to the deep high-voltage N well DHVNW isolation ring D potential of the high-voltage NMOS tube M1, and the other end is connected to the drain terminal D of the high-voltage NMOS tube M1 and the drain terminal D of the high-voltage NMOS tube M2 and the D potential isolation ring of the deep high-voltage N well DHVNW of the high-voltage NMOS tube M2.

[0058] One end of the POLY resistor RM2 is connected to the deep high-voltage P-well HVPW isolation ring of the high-voltage NMOS tube M1, and the other end of the high-voltage PMOS tube M0 deep high-voltage P-well HVPW isolation ring, the deep high-voltage P-well HVPW isolation ring of the high-voltage NMOS tube M2, the source terminal S, the body terminal D, and the P-type substrate P_sub are connected to GND together;

[0059] The high-voltage NMOS tube M2 forms a deep high-voltage P-well HVPW isolation ring on the P-type substrate P_sub and connects to GND; forms an N-type buried layer NBL on the P-type substrate P_sub, forms a high-voltage N-well HVNW on the N-type buried layer NBL and forms a drain terminal D in the well; grows a D potential isolation ring of the deep high-voltage N-well DHVNW on the N-type buried layer and connects the drain terminal D, the drain terminal D of the high-voltage NMOS tube M1, and one end of the POLY resistor Rlatchup together, forms a deep high-voltage P-well HVPW on the N-type buried layer NBL and forms a source terminal S and a body terminal B in the well and connects to GND; the source terminal S and the drain terminal D of the high-voltage NMOS tube M1 are N+ ion implanted, and the body terminal B is P+ ion implanted;

[0060] One end of the POLY resistor RM2 is connected to the deep high voltage P well HVPW of the high voltage NMOS tube M1, and the other end is connected to GND together with the deep high voltage P well PSUB of the high voltage PMOS tube M0 and the deep high voltage P well PSUB of the high voltage NMOS tube M2.

[0061] The drain terminal D of the high-voltage NMOS transistor M1 is connected with the drain terminal D of the high-voltage NMOS transistor M2 and the D potential of the deep high-voltage N well DHVNW of the high-voltage NMOS transistor M2.

[0062] The drain terminal D of the high-voltage PMOS tube M0 and the source terminal S of the deep high-voltage P well HVPW of the high-voltage NMOS tube M1 are connected together to form the output OUT.

[0063] The high-voltage PMOS tube M0 is composed of a P-type substrate P_sub, an N-type buried layer NBL, a deep high-voltage P-well HVPW, a deep high-voltage N-well DHVNW and a shallow N-well NW5V, wherein the D end is the drain end of the high-voltage PMOS tube M0, the S end is the source end of the high-voltage PMOS tube M0, and the B end is the body end of the high-voltage PMOS tube M0;

[0064] The high-voltage NMOS tube M1 is composed of a P-type substrate P_sub, an N-type buried layer NBL, a deep high-voltage P-well HVPW, a deep high-voltage N-well DHVNW, and a high-voltage N-well HVNW, wherein D is the drain terminal of the high-voltage PMOS tube M0, S is the source terminal of the high-voltage PMOS tube M0, and B is the body terminal of the high-voltage PMOS tube M0;

[0065] The high-voltage NMOS tube M2 is composed of a P-type substrate P_sub, an N-type buried layer NBL, a deep high-voltage P-well HVPW, a deep high-voltage N-well DHVNW, and a high-voltage N-well HVNW, wherein D is the drain terminal of the high-voltage PMOS tube M0, S is the source terminal of the high-voltage PMOS tube M0, and B is the body terminal of the high-voltage PMOS tube M0;

[0066] The POLY resistor Rlatchup and the POLY resistor RM2 are composed of conventional P-type POLY resistors.

[0067] When GND is connected to positive and OUT is connected to negative, HVNGC1 is pulled to OUT level, HVNGC0 is at GND level, M1 and M2 are both closed. Figure 4 The diode connected by the blue dotted line has no path, so it can be reverse connected without leakage.

[0068] When VCC and GND are connected to 24V high voltage and OUT is negative voltage, HVNGC1 is higher than OUT in this application, M1 is turned on, so current will flow through GND to OUT port (such as red line), which will cause Figure 1 The P0 point is a negative voltage, which causes the parasitic PNP to turn on. The on-state voltage drop of RM2 is further increased, and the parasitic NPN is turned on. The current from VCC to the OUT port gradually increases. Although this current will be affected by RM2 and the application conditions (the load from the OUT port to GND), under high voltage conditions, high power will be formed, which will lead to a bad chip.

[0069] In addition, the lower tube will also form a latchup with the P tube, from VCC to GND, but there is a metal METAL separation in the layout, and there is enough distance, so it will not cause latchup.

[0070] By connecting the Rlatchup resistor in series, the current of the NPN is limited, thereby reducing the power consumption from VCC to GND to protect the chip. Figure 3 , Figure 4 As shown in the figure, the Rlatchup resistor is connected in series to limit the current of the NPN, thereby reducing the power consumption from VCC to GND to achieve the purpose of protecting the chip. Figure 3 , Figure 4 shown.

[0071] Finally, it should be noted that the above description is only a preferred example of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A system for solving latchup in anti-reverse connection circuit application, characterized in that: The system comprises: a high-voltage PMOS tube M0, a high-voltage NMOS tube M1, a high-voltage NMOS tube M2, a POLY resistor Rlatchup and a POLY resistor RM2; A POLY resistor Rlatchup is connected in series between the high-voltage NMOS tube M1 and the high-voltage NMOS tube M2, and a POLY resistor RM2 is connected in series between the high-voltage NMOS tube M1 and GND; A POLY resistor Rlatchup is connected in series between the D potential of the high-voltage NMOS tube M1 and the D terminal of the high-voltage NMOS tube M1, and a POLY resistor RM2 is connected in series between the deep high-voltage P well (HVPW) of the high-voltage NMOS tube M1 and GND; The high-voltage PMOS tube M0 is formed on the P-type substrate P_sub with a deep high-voltage P-well HVPW isolation ring connected to GND, and an N-type buried layer NBL is formed on the P-type substrate P_sub. A deep high-voltage N-well DHVNW and a shallow N-well NW5V are grown on the N-type buried layer as the source terminal S and body terminal B of the high-voltage PMOS tube M0 connected to the power supply VCC. A deep high-voltage P-well HVPW is grown on the N-type buried layer as the drain terminal D of the high-voltage PMOS tube M0 and connected to the source terminal S of the high-voltage NMOS tube M1 as the output terminal OUT; the source terminal S and the drain terminal D of the high-voltage PMOS tube M0 are P+ ion implanted, and the body terminal B is N+ ion implanted; The high-voltage NMOS tube M1 forms a deep high-voltage P-well HVPW isolation ring on a P-type substrate P_sub and connects to one end of a POLY resistor RM2; forms an N-type buried layer NBL on the P-type substrate P_sub, grows a deep high-voltage N-well DHVNW on the N-type buried layer as a D potential isolation ring connected to a POLY resistor Rlatchup, forms a deep high-voltage P-well HVPW on the N-type buried layer NBL, forms a source terminal S and a body terminal B in the well and connects to a drain terminal D of the high-voltage PMOS tube M0 as an output terminal OUT; forms a high-voltage N-well HVNW on the N-type buried layer NBL, forms a drain terminal D in the well and connects to the D potential isolation ring of the deep high-voltage N-well DHVNW of the high-voltage NMOS tube M2, the drain terminal D of the high-voltage NMOS tube M2, and one end of the POLY resistor Rlatchup; the source terminal S and the drain terminal D of the high-voltage NMOS tube M1 are N+ ion implanted, and the body terminal B is P+ ion implanted; The N-type buried layer NBL of the high-voltage PMOS tube M0, the deep high-voltage P well HVPW of the high-voltage PMOS tube M0 and the N-type buried layer NBL of the high-voltage NMOS tube M1 form an NPN structure; the N-type buried layer NBL of the high-voltage PMOS tube M0, the deep high-voltage P well HVPW of the high-voltage NMOS tube M1 and the N-type buried layer NBL of the high-voltage NMOS tube M1 form an NPN structure; One end of the POLY resistor Rlatchup is connected to the deep high-voltage N well DHVNW isolation ring D potential of the high-voltage NMOS tube M1, and the other end is connected to the drain terminal D of the high-voltage NMOS tube M1 and the drain terminal D of the high-voltage NMOS tube M2 and the D potential isolation ring of the deep high-voltage N well DHVNW of the high-voltage NMOS tube M2; One end of the POLY resistor RM2 is connected to the deep high-voltage P-well HVPW isolation ring of the high-voltage NMOS tube M1, and the other end of the high-voltage PMOS tube M0 deep high-voltage P-well HVPW isolation ring, the deep high-voltage P-well HVPW isolation ring of the high-voltage NMOS tube M2, the source terminal S, the body terminal D, and the P-type substrate P_sub are connected to GND together; The high-voltage NMOS tube M2 forms a deep high-voltage P-well HVPW isolation ring on the P-type substrate P_sub and connects to GND; forms an N-type buried layer NBL on the P-type substrate P_sub, forms a high-voltage N-well HVNW on the N-type buried layer NBL and forms a drain terminal D in the well; grows a D potential isolation ring of the deep high-voltage N-well DHVNW on the N-type buried layer and connects the drain terminal D, the drain terminal D of the high-voltage NMOS tube M1, and one end of the POLY resistor Rlatchup together, forms a deep high-voltage P-well HVPW on the N-type buried layer NBL and forms a source terminal S and a body terminal B in the well and connects to GND; the source terminal S and the drain terminal D of the high-voltage NMOS tube M1 are N+ ion implanted, and the body terminal B is P+ ion implanted; One end of the POLY resistor RM2 is connected to the deep high-voltage P well HVPW of the high-voltage NMOS tube M1, and the other end is connected to GND together with the deep high-voltage P well PSUB of the high-voltage PMOS tube M0 and the deep high-voltage P well PSUB of the high-voltage NMOS tube M2; The drain terminal D of the high-voltage NMOS tube M1 is connected with the drain terminal D of the high-voltage NMOS tube M2 and the D potential of the deep high-voltage N well DHVNW of the high-voltage NMOS tube M2; The drain terminal D of the high-voltage PMOS tube M0 and the source terminal S of the deep high-voltage P well HVPW of the high-voltage NMOS tube M1 are connected together to form the output OUT; The high-voltage PMOS tube M0 is composed of a P-type substrate P_sub, an N-type buried layer NBL, a deep high-voltage P-well HVPW, a deep high-voltage N-well DHVNW and a shallow N-well NW5V, wherein the D end is the drain end of the high-voltage PMOS tube M0, the S end is the source end of the high-voltage PMOS tube M0, and the B end is the body end of the high-voltage PMOS tube M0; The high-voltage NMOS tube M1 is composed of a P-type substrate P_sub, an N-type buried layer NBL, a deep high-voltage P-well HVPW, a deep high-voltage N-well DHVNW, and a high-voltage N-well HVNW, wherein D is the drain terminal of the high-voltage PMOS tube M0, S is the source terminal of the high-voltage PMOS tube M0, and B is the body terminal of the high-voltage PMOS tube M0; The high-voltage NMOS tube M2 is composed of a P-type substrate P_sub, an N-type buried layer NBL, a deep high-voltage P-well HVPW, a deep high-voltage N-well DHVNW, and a high-voltage N-well HVNW, wherein D is the drain terminal of the high-voltage PMOS tube M0, S is the source terminal of the high-voltage PMOS tube M0, and B is the body terminal of the high-voltage PMOS tube M0; The POLY resistor Rlatchup and the POLY resistor RM2 are composed of conventional P-type POLY resistors.

2. A system for solving latchup in anti-reverse connection circuit application according to claim 1, characterized in that: Provide metal layers, including metal trace combinations.

3. A method for solving latchup in a system for solving latchup in an anti-reverse connection circuit application according to any one of claims 1 to 2, characterized in that: When GND is connected to positive and OUT is connected to negative, HVNGC1 is pulled to OUT level, HVNGC0 is at GND level, and M1 and M2 are both closed. When VCC and GND are connected to positive voltage and OUT is negative voltage, HVNGC1 is higher than OUT in this application, M1 is turned on, so current will flow to OUT through GND, causing negative voltage, causing the parasitic PNP to turn on, and the on-state voltage drop of RM2 to further increase, turning on the parasitic NPN, and the current from VCC to OUT gradually increases; At the same time, the lower tube will also form a latchup with the P tube, from VCC to GND, so it is separated by metal METAL in the layout.

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