Silicon-on-insulator semiconductor component, process platform and manufacturing method

Abstract

The invention relates to a silicon-on-insulator semiconductor component, which comprises a substrate; the buried dielectric layer is arranged on the substrate; a first electrode; a second electrode; the drift region is arranged on the buried dielectric layer; a fall structure is formed on the upper surface of the drift region, the fall structure comprises a first side close to the first electrode, a second side close to the second electrode and a transition region between the first side and the second side, and the upper surface of the second side is higher than the lower surface of the first side. The thickness of the drift region on the second side is greater than the thickness of the drift region on the first side; wherein the first electrode and the second electrode are configured as follows: when reverse bias voltage is applied to the component, the voltage applied by the second electrode is greater than that applied by the first electrode. According to the invention, the breakdown point of the device can be controlled below the high-voltage end, so that the drift region can be completely exhausted, and the breakdown voltage of the device can still be improved on the premise of not increasing the thickness of the buried oxide layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a silicon-on-insulator semiconductor component, a silicon-on-insulator semiconductor process platform, and a method for manufacturing the silicon-on-insulator semiconductor component. Background Art

[0002] With the wide application of ultra-large-scale integrated circuits in various fields, the system has higher and higher requirements for the development of high-voltage and high-power semiconductor devices. Integrated high-voltage devices (such as LDMOS, LIGBT and high-voltage diodes, etc.) using silicon on insulator (SOI) technology have the advantages of SOI technology and devices themselves, such as fast working speed, low parasitic effect, high breakdown voltage, simple process preparation and convenient integration, and thus have been widely studied and applied. However, conventional silicon on insulator integrated high-voltage devices are difficult to achieve a breakdown voltage of 1200V and above. Although the thickness of the buried oxide layer is related to the breakdown voltage, a thick buried oxide layer will make the thermal conductivity of the device worse, and when the buried oxide layer is thick enough, it will not contribute to the breakdown voltage, and it will also lead to an increase in cost. Therefore, it is unrealistic to increase the breakdown voltage by continuing to increase the thickness of the buried oxide layer after the breakdown voltage reaches a certain value. Summary of the invention

[0003] Based on this, it is necessary to provide a silicon-on-insulator semiconductor component with a higher breakdown voltage.

[0004] A silicon-on-insulator semiconductor component comprises: a substrate; a buried dielectric layer, arranged on the substrate; a first electrode; a second electrode; a drift region, arranged on the buried dielectric layer; a step structure is formed on the upper surface of the drift region, the step structure comprises a first side close to the first electrode, a second side close to the second electrode, and a transition region between the first side and the second side, the upper surface of the second side is higher than the lower surface of the first side, so that the thickness of the drift region on the second side is greater than the thickness on the first side; wherein the first electrode and the second electrode are configured such that when a reverse bias is applied to the component, the voltage applied by the second electrode is greater than the voltage applied by the first electrode.

[0005] The above-mentioned silicon-on-insulator semiconductor component adopts a structure in which the thickness of the drift region at the low-voltage end of the device is smaller than the thickness of the drift region at the high-voltage end when a reverse bias is applied. In this way, the breakdown point of the device can be controlled below the high-voltage end, so that the drift region can be completely depleted, and the breakdown voltage of the device can still be improved without increasing the thickness of the buried oxide layer.

[0006] In one embodiment, the component is a lateral double diffused metal-oxide-semiconductor field effect transistor, the first electrode is a source, the second electrode is a drain, and the lateral double diffused metal-oxide-semiconductor field effect transistor further includes a gate.

[0007] In one embodiment, the component is a lateral insulated gate bipolar transistor, the first electrode is an emitter, the second electrode is a collector, and the lateral insulated gate bipolar transistor further includes a gate.

[0008] In one embodiment, the component is a diode, the first electrode is an anode, and the second electrode is a cathode.

[0009] In one embodiment, the step structure is a step structure, including a first table located on the first side, a second table located on the second side, and a step wall located in the transition area, and the height difference between the second table and the first table is 3 to 10 microns.

[0010] In one embodiment, the inclination angle of the step wall is 20 degrees to 90 degrees.

[0011] In one embodiment, the drift region has a first conductivity type, and the component also includes a second conductivity type protective layer, the second conductivity type protective layer is located in the drift region and surrounds the corner formed by the first mesa and the step wall and the corner formed by the second mesa and the step wall, the first conductivity type and the second conductivity type are opposite conductivity types.

[0012] It is also necessary to provide a silicon-on-insulator semiconductor process platform, including the silicon-on-insulator semiconductor components described in any of the above embodiments, and also including complementary metal-oxide-semiconductor field effect transistors and / or well resistors.

[0013] It is also necessary to provide a method for manufacturing a silicon-on-insulator semiconductor component, comprising: obtaining a wafer, the wafer comprising a substrate, a buried dielectric layer on the substrate, and a drift region on the buried dielectric layer; forming a step structure on the upper surface of the drift region through photolithography and etching, the step structure comprising a first side, a second side, and a transition region between the first side and the second side, the upper surface of the second side being higher than the lower surface of the first side, so that the thickness of the drift region on the second side is greater than the thickness on the first side; forming a first electrode and a second electrode; the first side is a side close to the first electrode, and the second side is a side close to the second electrode; wherein the first electrode and the second electrode are configured such that when a reverse bias is applied to the component, the voltage applied to the second electrode is greater than the voltage applied to the first electrode.

[0014] The above-mentioned method for manufacturing silicon-on-insulator semiconductor components, the formed components have a structure in which (when a reverse bias is applied) the thickness of the drift region at the low-voltage end of the device is less than the thickness of the drift region at the high-voltage end. In this way, the breakdown point of the device can be controlled below the high-voltage end, so that the drift region can be completely depleted, and the breakdown voltage of the device can still be improved without increasing the thickness of the buried oxide layer.

[0015] In one embodiment, the etching is a reactive ion etching process.

[0016] It is also necessary to provide a method for manufacturing a silicon-on-insulator semiconductor component, comprising: obtaining a wafer, the wafer comprising a substrate, a buried dielectric layer on the substrate, and a first epitaxial layer on the buried dielectric layer; forming a second epitaxial layer in a partial area on the first epitaxial layer, forming a step structure at the junction of the first epitaxial layer and the second epitaxial layer, the step structure comprising a first side on one side of the second epitaxial layer, a second side on one side of the first epitaxial layer, and a transition zone between the first side and the second side; forming a first electrode and a second electrode, the first side being a side close to the first electrode, and the second side being a side close to the second electrode; wherein the first electrode and the second electrode are configured such that when a reverse bias is applied to the component, the voltage applied to the second electrode is greater than the voltage applied to the first electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0018] Figure 1 It is a schematic diagram of the cross-sectional structure of a device in an embodiment in which the silicon-on-insulator semiconductor component is an LDMOS;

[0019] Figure 2a is a schematic cross-sectional view of a SOI LDMOS having a whole protective layer formed thereon in one embodiment, Figure 2b is a schematic cross-sectional view of a SOI LDMOS having protective layers respectively surrounding two corners in one embodiment, Figure 2c is a cross-sectional schematic diagram of a SOI LDMOS formed by a secondary epitaxial growth method in an embodiment;

[0020] Figure 3 is a schematic diagram of a cross-sectional structure of a device in an embodiment in which the silicon-on-insulator semiconductor component is a LIGBT;

[0021] Figure 4is a cross-sectional schematic diagram of a LIGBT formed by a secondary epitaxial growth method in one embodiment;

[0022] Figure 5 is a schematic diagram of a cross-sectional structure of a diode in an embodiment in which the silicon-on-insulator semiconductor component is a diode;

[0023] Figure 6 is a cross-sectional schematic diagram of a diode formed by a secondary epitaxial growth method in one embodiment;

[0024] Figure 7 is a schematic cross-sectional structural diagram of a silicon-on-insulator semiconductor process platform in one embodiment of the present application;

[0025] Figure 8 is a flow chart of a method for manufacturing a silicon-on-insulator semiconductor component in one embodiment of the present application;

[0026] Fig. 9 is a flow chart of a method for manufacturing a silicon-on-insulator semiconductor component in another embodiment of the present application;

[0027] Fig.10 is a flow chart of steps between steps S420 and S430 in an embodiment in which the device to be manufactured is SOI LDMOS;

[0028] Figures 11a to 11e is based on Fig.10 A schematic cross-sectional view of a device during the process of manufacturing SOI LDMOS by the method shown;

[0029] Fig.12 is a flow chart of steps between steps S420 and S430 in one embodiment in which the device to be manufactured is a SOI LIGBT;

[0030] Figures 13a to 13e is based on Fig.12 A schematic cross-sectional view of a device during the process of manufacturing an SOI LIGBT by the method shown;

[0031] Fig.14 is a flow chart of steps between steps S420 and S430 in one embodiment in which the device to be manufactured is a SOI diode;

[0032] Figures 15a to 15d is based on Fig.14 A schematic cross-sectional view of a device during the process of manufacturing an SOI diode according to the method shown;

[0033] Fig.16 is a schematic cross-sectional structure diagram of a silicon-on-insulator semiconductor process platform in one embodiment of forming a drift region step structure by reactive ion etching;

[0034] Fig.17It is a schematic cross-sectional structure diagram of a silicon-on-insulator semiconductor process platform in an embodiment of forming a drift region step structure by secondary epitaxy. DETAILED DESCRIPTION

[0035] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0037] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. "Connection" in this specification should be understood as "electrical connection", "communication connection" and the like if the connected circuits, modules, units, etc. have transmission of electrical signals or data to each other. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

[0038] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0039] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used herein, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It is understood that "at least one" refers to one or more, and "multiple" refers to two or more. "At least part of an element" refers to part or all of an element. It should also be understood that the terms "compose" and / or "comprise" when used in this specification determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0041] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0042] For conventional SOI semiconductor process platforms, integrated high-voltage devices can usually only reach a breakdown voltage of 600V and it is difficult to reach a breakdown voltage of more than 1200V. And the withstand voltage of integrated high-voltage devices cannot be increased to more than 1200V by thickening the top silicon, because simply increasing the thickness of the top silicon cannot solve the problem of longitudinal early breakdown. The exemplary SOI semiconductor process platform adopts a structure of thick buried oxide layer and thin top silicon, which can make the integrated high-voltage device reach a breakdown voltage of 1200V. This is because the breakdown voltage of the device will increase with the increase of the thickness of the buried oxide layer within a certain range, and the thin top silicon limits the energy obtained by the carrier through the longitudinal electric field, making the device less likely to be broken down. However, this solution has obvious disadvantages, because the buried oxide layer of the SOI structure blocks the heat from being conducted to the substrate, which leads to poor heat dissipation of the device, causing the local lattice temperature of the device to rise, causing the electrical parameters of the device to degrade, and these degradation phenomena make the device reliability worse, which is more obvious for devices with thick buried oxide layers.

[0043] The present application proposes a silicon-on-insulator semiconductor component, comprising:

[0044] substrate;

[0045] A buried dielectric layer is disposed on the substrate;

[0046] a first electrode;

[0047] a second electrode;

[0048] A drift region is disposed on the buried dielectric layer; a step structure is formed on the upper surface of the drift region, the step structure includes a first side close to the first electrode, a second side close to the second electrode, and a transition region between the first side and the second side, the upper surface of the second side is higher than the lower surface of the first side, so that the thickness of the drift region on the second side is greater than the thickness on the first side;

[0049] The first electrode and the second electrode are configured such that when a reverse bias is applied to the component, the voltage applied by the second electrode is greater than the voltage applied by the first electrode.

[0050] The above-mentioned silicon-on-insulator semiconductor component adopts a structure in which the thickness of the drift region at the low-voltage end of the device is smaller than the thickness of the drift region at the high-voltage end when a reverse bias is applied. In this way, the breakdown point of the device can be controlled below the high-voltage end, so that the drift region can be completely depleted, and the breakdown voltage of the device can still be improved without increasing the thickness of the buried oxide layer.

[0051] In one embodiment of the present application, the silicon-on-insulator semiconductor device further includes a first electrode lead-out region and a second electrode lead-out region. The first electrode lead-out region and the second electrode lead-out region are disposed on the buried dielectric layer and have P-type doping or N-type doping. The first electrode is located on the first electrode lead-out region and is electrically connected to the first electrode lead-out region; the second electrode is located on the second electrode lead-out region and is electrically connected to the second electrode lead-out region.

[0052] In one embodiment of the present application, the drift region has a first conductivity type, and the component also includes a second conductivity type protective layer, the second conductivity type protective layer is located in the drift region and surrounds the corner formed by the first table and the step wall and the corner formed by the second table and the step wall, the first conductivity type and the second conductivity type are opposite conductivity types.

[0053] Figure 1 The cross-sectional structure diagram of the device in one embodiment in which the silicon-on-insulator semiconductor device is a lateral double-diffused Metal-Oxide-Semiconductor Field Effect Transistor (LDMOS for short). The LDMOS includes a substrate 110, a buried dielectric layer 120, a drift region 130, a first electrode 162, a second electrode 164 and a gate 166. The first electrode 162 is a source electrode, and the second electrode 164 is a drain electrode. The upper surface of the drift region 130 is higher on the side close to the drain electrode (hereinafter referred to as the high side of the drift region) than on the side close to the source electrode (hereinafter referred to as the low side of the drift region), thereby forming a step structure 131.

[0054] The LDMOS further includes a first electrode lead-out region (i.e., source region) 142 located at the lower side of the drift region and a second electrode lead-out region (i.e., drain region) 144 located at the upper side of the drift region. The first electrode 162 (i.e., source) is located on the first electrode lead-out region 142 and is electrically connected to the first electrode lead-out region 142. The second electrode 164 (i.e., drain) is located on the second electrode lead-out region 144 and is electrically connected to the second electrode lead-out region 144. Figure 1 In the illustrated embodiment, the gate 166 extends from the lower side of the drift region to the edge of the first electrode lead-out region 142 , and may overlap with the first electrode lead-out region 142 by a certain area.

[0055] exist Figure 1 In the embodiment shown, the LDMOS further includes a field oxide layer 147 , which extends from the high side of the drift region to the low side of the drift region. A portion of the gate 166 extends onto the field oxide layer 147 .

[0056] exist Figure 1 In the illustrated embodiment, the LDMOS is an N-type LDMOS, the drift region 130 is an N-type drift region, and the LDMOS further includes a P-type body region 132 located at the lower side of the drift region and an N-well 134 located at the upper side of the drift region. The first electrode lead-out region 142 is an N+ region located in the P-type body region 132. The second electrode lead-out region 144 is an N+ region located in the N-well 134.

[0057] exist Figure 1 In the embodiment shown, the LDMOS further includes a body lead region 146 located in the P-type body region 132. The body lead region 146 is a P+ region. The first electrode 162 is electrically connected to the body lead region 146.

[0058] In one embodiment of the present application, the LDMOS further includes an interlayer dielectric (ILD) layer 150. The interlayer dielectric layer 150 covers structures such as the gate 166, the field oxide layer 147, the first electrode lead-out region 142, the second electrode lead-out region 144, and the body lead-out region 146.

[0059] In one embodiment of the present application, the buried dielectric layer 120 is a buried oxide layer, and its material may be silicon dioxide.

[0060] In one embodiment of the present application, the drop structure is a step structure, including a first table located on the first side, a second table located on the second side, and a step wall located in the transition area, and the height difference between the second table and the first table (corresponding to Figure 1 The height difference in the step wall is 3 to 10 microns, and the appropriate height difference can ensure that the drift region is completely depleted. Figure 1 The θ1 in the figure is 20 to 90 degrees, and a suitable θ1 can ensure that the device will not be broken down prematurely at this angle.

[0061] When the LDMOS is reverse biased, a positive voltage is applied to the drain, and the gate 166, the source and the substrate are grounded. The PN junction formed by the P-type body region 132 and the N-type drift region 130 is reverse biased. As the external bias continues to increase, the space charge region in the low-doped drift region 130 expands toward the drain end. The depletion region in the drift region 130 can be extended to the upper surface of the buried oxide layer at most, and the electric field of the depletion region can be almost unaffected by the substrate 110. The presence of the buried oxide layer improves the longitudinal withstand voltage of the device and avoids premature breakdown in the longitudinal direction when the depletion region expands toward the drain end. At the same time, the drift region width at the source end is smaller than the drift region thickness at the drain end, so that when the device works in the reverse withstand voltage state, the depletion region tends to expand toward the drain end, and can be more easily depleted from the source end to the drain end, so that the drift region 130 can be completely depleted before longitudinal breakdown, and the breakdown point is controlled at the junction of the drain end drift region and the buried oxide layer. In this way, the breakdown voltage of the device can be increased without increasing the thickness of the buried oxide layer, so that the breakdown voltage of the device can reach more than 1200V.

[0062] See also Figure 2a In one embodiment of the present application, the LDMOS further includes a protection layer 136. The protection layer 136 is located in the drift region 130, has a conductivity type opposite to that of the drift region 130, and surrounds a corner formed by the first mesa and the step wall and a corner formed by the second mesa and the step wall. The protection layer 136 may be Figure 2a The whole structure shown can also be Figure 2b The structures shown surround the two corners respectively. By forming a protection layer with a conductivity type opposite to that of the drift region 130 at the step corner, it is possible to avoid premature breakdown of the device due to concentration of electric field lines caused by the step corner.

[0063] In some embodiments of the present application, the aforementioned drift region step structure of the silicon-on-insulator semiconductor device can be formed by a reactive ion etching (RIE) method or a secondary epitaxy method. The secondary epitaxy can obtain a more "vertical" drift region step, see Figure 2c . Figure 2c It can be an LDMOS formed by a secondary epitaxial method. Figure 1 The main difference between the structures shown is that the steps are much steeper, and the details of their construction will not be described here; Figure 1 The structure shown can be formed by reactive ion etching. If the drift region step structure proposed in this application is realized by a method of single epitaxy plus reactive ion etching or a method of double epitaxy, a 1200V silicon-on-insulator semiconductor process platform can be realized; if a conventional single epitaxy method is used, a 600V silicon-on-insulator semiconductor process platform can be realized. Therefore, the 1200V process platform proposed in this application is compatible with the 600V process platform and has good compatibility.

[0064] Figure 3 The cross-sectional structure diagram of the device in an embodiment in which the silicon-on-insulator semiconductor component is a lateral insulated gate bipolar transistor (LIGBT for short). The LIGBT includes a substrate 210, a buried dielectric layer 220, a drift region 230, a first electrode 262, a second electrode 264 and a gate 266. The first electrode 262 is an emitter, and the second electrode 264 is a collector. The upper surface of the drift region 230 is higher on the side close to the collector (hereinafter referred to as the high side of the drift region) than on the side close to the emitter (hereinafter referred to as the low side of the drift region), thereby forming a step structure 231.

[0065] Figure 3 The LIGBT in the illustrated embodiment is an N-type LIGBT, the drift region 230 is an N-type drift region, and the LIGBT further includes a P-type first body region 234 and a second body region 236, and an N-well 232. The N-well 232 and the second body region 236 are located at the high side of the drift region, and the first body region 234 is located at the low side of the drift region. A first N+ region 242 and a first P+ region 246 are provided in the first body region 234, and an emitter 262 is electrically connected to the first N+ region 242 and the first P+ region 246. A second P+ region 248 is provided in the N-well 232, a second N+ region 244 is provided in the second body region 236, and a collector 264 is electrically connected to the second N+ region 244, the second P+ region 248 and the second body region 236. Figure 3 In the illustrated embodiment, the gate 266 extends from the lower side of the drift region to the edge of the first N+ region 242 and may overlap with the first N+ region 242. When a reverse bias is applied to the LIGBT, the collector is connected to a high voltage and the emitter is connected to a low voltage or ground.

[0066] exist Figure 3 In the embodiment shown, the LIGBT further includes a field oxide layer 247 extending from the high side of the drift region to the low side of the drift region. A portion of the gate 266 extends onto the field oxide layer 247 .

[0067] In one embodiment of the present application, the LIGBT further includes an interlayer dielectric layer 250. The interlayer dielectric layer 250 covers structures such as the gate 266, the field oxide layer 247, the first N+ region 242, the first P+ region 246, the second N+ region 244, the second P+ region 248, and the second body region 236.

[0068] The step structure of the drift region of LIGBT can also be formed by reactive ion etching or secondary epitaxy. Secondary epitaxy can obtain a more "vertical" drift region step, see Figure 4 . Figure 4 and Figure 3 The main difference is that the step structure is steeper, and its specific structure will not be described in detail. Figure 3 The structure shown can be formed by reactive ion etching, the height difference H2 between the second terrace and the first terrace is 3 to 10 microns, and the inclination angle θ2 of the step wall is 20 to 90 degrees.

[0069] In one embodiment of the present application, the LIGBT further includes a protective layer. The protective layer is located in the drift region, has a conductivity type opposite to that of the drift region, and surrounds a corner formed by the first mesa and the step wall and a corner formed by the second mesa and the step wall. The protective layer can be a whole structure or a structure that surrounds the two corners respectively.

[0070] Figure 5 1 is a schematic diagram of a cross-sectional structure of a diode in an embodiment in which the silicon-on-insulator semiconductor component is a diode. The diode includes a substrate 310, a buried dielectric layer 320, a drift region 330, a first electrode 362, and a second electrode 364. The first electrode 362 is an anode, and the second electrode 364 is a cathode. The upper surface of the drift region 330 is higher on the side close to the cathode (hereinafter referred to as the high side of the drift region) than on the side close to the anode (hereinafter referred to as the low side of the drift region), thereby forming a step structure 331.

[0071] The diode further includes a first electrode lead-out region (i.e., anode region) 342 located at the lower side of the drift region and a second electrode lead-out region (i.e., cathode region) 344 located at the higher side of the drift region. The first electrode 362 (i.e., anode) is located on the first electrode lead-out region 342 and is electrically connected to the first electrode lead-out region 342. The second electrode 364 (i.e., cathode) is located on the second electrode lead-out region 344 and is electrically connected to the second electrode lead-out region 344. When a reverse bias is applied to the diode, the cathode is connected to a high voltage, and the anode is connected to a low voltage or grounded.

[0072] exist Figure 5 In the embodiment shown, the drift region 330 is an N-type drift region, and the diode further includes an N-well 334 located at the high side of the drift region. The second electrode lead region 344 is an N+ region located in the N-well 334. The first electrode lead region 342 is a P+ region located at the low side of the drift region.

[0073] exist Figure 5 In the illustrated embodiment, the diode further includes a field oxide layer 347 extending from the high side of the drift region to the low side of the drift region.

[0074] In one embodiment of the present application, the diode further includes an interlayer dielectric layer 350. The interlayer dielectric layer 350 covers structures such as the field oxide layer 347, the first electrode lead-out region 342, and the second electrode lead-out region 344.

[0075] The step structure of the drift region of the diode can also be formed by reactive ion etching or secondary epitaxy. Secondary epitaxy can obtain a more "vertical" drift region step, see Figure 6 . Figure 6 and Figure 5 The main difference is that the step structure is steeper, and its specific structure will not be described in detail. Figure 5 The structure shown can be formed by reactive ion etching, the height difference H3 between the second terrace and the first terrace is 3 to 10 microns, and the inclination angle θ3 of the step wall is 20 degrees to 90 degrees.

[0076] In one embodiment of the present application, the diode further includes a protective layer. The protective layer is located in the drift region, has a conductivity type opposite to that of the drift region, and surrounds a corner formed by the first mesa and the step wall and a corner formed by the second mesa and the step wall. The protective layer can be a whole structure or a structure that surrounds the two corners respectively.

[0077] The present application also provides a silicon-on-insulator semiconductor process platform, which includes the silicon-on-insulator semiconductor components as described in any of the above embodiments, and also includes low-voltage devices and / or passive devices. In one embodiment of the present application, the low-voltage device can be a complementary metal-oxide-semiconductor field effect transistor (Complementary Metal-Oxide-Semiconductor Field Effect Transistor, referred to as CMOS), and the passive device can be a well resistor. Figure 7 is a schematic cross-sectional structure diagram of a silicon-on-insulator semiconductor process platform in one embodiment of the present application, Figure 7 In the embodiment shown, the silicon-on-insulator semiconductor process platform includes LDMOS, LIGBT, diode, CMOS and well resistor. The structures of LDMOS, LIGBT and diode have been introduced above and will not be repeated here. Different devices are isolated from each other by isolation structures. The height of the upper surface of the drift region of CMOS and well resistor structure is the same as the height of the high side of the drift region.

[0078] The present application accordingly provides a method for manufacturing a silicon-on-insulator semiconductor component, which can be used to manufacture the silicon-on-insulator semiconductor component described in any of the above embodiments. Figure 8 1 is a flow chart of a method for manufacturing a silicon-on-insulator semiconductor component in an embodiment of the present application. In this embodiment, a step structure of a drift region is formed by etching. The manufacturing method comprises the following steps:

[0079] S410, obtaining a wafer.

[0080] The wafer includes a substrate, a buried dielectric layer on the substrate and a drift region on the buried dielectric layer. The drift region can be formed by epitaxy on the buried oxide layer.

[0081] S420, forming a step structure on the upper surface of the drift region by photolithography and etching.

[0082] A certain thickness of drift region (epitaxial layer) is etched in the area exposed by the photoresist, so that the thickness of the epitaxial layer in the etched area is less than the thickness of the epitaxial layer in other parts. That is, the step structure includes a first side, a second side, and a transition area between the first side and the second side. The upper surface of the second side is higher than the lower surface of the first side, so that the thickness of the drift region on the second side is greater than the thickness on the first side.

[0083] In one embodiment of the present application, etching is specifically carried out by using a reactive ion etching process, which has good anisotropy and can obtain a relatively steep transition zone. In addition, the reactive ion etching has a fast etching speed and can accurately control the etching depth.

[0084] S430, forming a first electrode and a second electrode.

[0085] The first side is a side close to the first electrode, and the second side is a side close to the second electrode.

[0086] The above-mentioned method for manufacturing silicon-on-insulator semiconductor components, the formed components have a structure in which (when a reverse bias is applied) the thickness of the drift region at the low-voltage end of the device is less than the thickness of the drift region at the high-voltage end. In this way, the breakdown point of the device can be controlled below the high-voltage end, so that the drift region can be completely depleted, and the breakdown voltage of the device can still be improved without increasing the thickness of the buried oxide layer.

[0087] In one embodiment of the present application, after step S420 and before step S430, a step of forming a protective layer in the drift region at the step structure by ion implantation may also be included. The protective layer surrounds the corner formed by the first table and the step wall and the corner formed by the second table and the step wall. The conductivity type of the protective layer is opposite to the conductivity type of the drift region. The protective layer can be a whole structure or a structure that surrounds the two corners respectively. In an embodiment in which the protective layer is a whole structure, the length of the injection window of the protective layer (the length direction is the length direction of the conductive channel) is 110% to 120% of the length of the transition zone (the length direction is the length direction of the conductive channel). Fig.16 The cross-sectional structure diagram of a silicon-on-insulator semiconductor process platform in an embodiment of forming a drift region step structure by reactive ion etching, in which the protective layer is a whole structure. In an embodiment of the protective layer being a structure that surrounds two corners respectively, the length of each injection window of the protective layer is 5% to 10% of the length of the transition region.

[0088] Fig. 91 is a flow chart of a method for manufacturing a silicon-on-insulator semiconductor device in another embodiment of the present application. In this embodiment, a step structure of a drift region is formed by a secondary epitaxial method, and the steps include:

[0089] S510, obtaining a wafer.

[0090] The wafer comprises a substrate, a buried dielectric layer on the substrate and a first epitaxial layer on the buried dielectric layer.

[0091] S520 , forming a second epitaxial layer in a partial region on the first epitaxial layer.

[0092] A partial area of ​​the surface of the first epitaxial layer can be exposed by photolithography, and then epitaxy is performed to form a second epitaxial layer in the exposed area. In this way, a step structure is formed at the junction of the first epitaxial layer and the second epitaxial layer, and the step structure includes a first side on one side of the second epitaxial layer, a second side on one side of the first epitaxial layer, and a transition area between the first side and the second side.

[0093] S530, forming a first electrode and a second electrode.

[0094] In one embodiment of the present application, the step structure is a step structure, including a first table located on the first side, a second table located on the second side, and a step wall located in the transition zone, the height difference between the second table and the first table is 3 to 10 microns, and the inclination angle of the step wall is 20 degrees to 90 degrees.

[0095] In one embodiment of the present application, after step S520 and before step S530, a step of forming a protective layer in the drift region at the step structure by ion implantation may also be included. The protective layer surrounds the corner formed by the first table and the step wall and the corner formed by the second table and the step wall. The conductivity type of the protective layer is opposite to the conductivity type of the drift region. The protective layer can be a whole structure or a structure that surrounds two corners respectively. In an embodiment in which the protective layer is a whole structure, the length of the injection window of the protective layer (the length direction is the length direction of the conductive channel) is 110% to 120% of the length of the transition zone (the length direction is the length direction of the conductive channel). In an embodiment in which the protective layer is a structure that surrounds two corners respectively, the length of each injection window of the protective layer is 5% to 10% of the length of the transition zone. Fig.17 It is a schematic cross-sectional structure diagram of a silicon-on-insulator semiconductor process platform in an embodiment of forming a drift region step structure by secondary epitaxy. In this embodiment, the protective layer is a structure surrounding two corners.

[0096] Taking the manufacture of SOI LDMOS as an example, the structure after step S420 is completed is as follows Fig.11a See Fig.10The method for manufacturing SOILDMOS further includes the following steps after step S420:

[0097] S421, forming a P-type body region and an N-well.

[0098] The P-type body region 132 and the N-well 134 can be formed by photolithography and ion implantation. Fig.11b The P-type body region 132 is formed on a first side of the step structure, and the N-well 134 is formed on a second side of the step structure.

[0099] S422, forming a field oxide layer.

[0100] A field oxide layer 147 is formed on the surface of the drift region 130, between the P-type body region 132 and the N-well 134. Fig.11c The field oxide layer 147 can be formed by deposition or thermal oxidation.

[0101] S423, forming a gate.

[0102] exist Fig.11d In the illustrated embodiment, the gate 166 extends from the P-type body region 132 to the field oxide layer 147. The gate 166 may be made of polysilicon and may be formed by deposition, photolithography, and etching.

[0103] S424, forming a source region, a drain region and a body lead-out region.

[0104] See also Fig.11e , an N+ source region (i.e., a first electrode lead-out region 142 ) is formed in a P-type body region 132 , an N+ drain region (i.e., a second electrode lead-out region 144 ) is formed in an N-well 134 , and a P+ body lead-out region 146 is formed in the P-type body region 132 .

[0105] S425, forming an interlayer dielectric layer and contact holes.

[0106] Deposit an interlayer dielectric layer 150, and then etch the interlayer dielectric layer 150 to form a contact hole. Then, perform step S430 to form a first electrode 162 and a second electrode 164, and obtain Figure 1 The structure shown. The first electrode 162 is electrically connected to the N+ source region, and the second electrode 164 is electrically connected to the N+ drain region. In addition to being applicable to the embodiment in which the step structure of the drift region is formed by reactive ion etching, the above steps S421 to S425 are also applicable to the embodiment in which the step structure of the drift region is formed by secondary epitaxy, except that the step structure formed by secondary epitaxy is steeper.

[0107] Taking the manufacture of SOI LIGBT as an example, the structure after step S420 is completed is as follows Fig.13a See Fig.12The method for manufacturing SOIL IGBT further includes the following steps after step S420:

[0108] S621, forming a first body region and an N-well.

[0109] The first body region 234 and the N well 232 may be formed by photolithography and ion implantation. Fig.13b The first body region 234 is formed on a first side of the step structure, and the N well 232 is formed on a second side of the step structure.

[0110] S622, forming a field oxide layer.

[0111] A field oxide layer 247 is formed between the surface of the drift region 130, the first body region 234 and the N well 232. Fig.13c The field oxide layer 247 can be formed by deposition or thermal oxidation.

[0112] S623, forming a gate.

[0113] exist Fig.13d In the embodiment shown, the gate 266 extends from the first body region 234 to the field oxide layer 247. The gate 266 may be made of polysilicon and may be formed by deposition, photolithography, and etching.

[0114] S624, forming a first N+ region, a second N+ region, a first P+ region, a second P+ region and a second body region.

[0115] See also Fig.13e The first N+ region 242 and the first P+ region 246 are formed in the first body region 234 . The second P+ region 248 is formed in the N well 232 , and the second N+ region 244 is formed in the second body region 236 .

[0116] S625, forming an interlayer dielectric layer and contact holes.

[0117] Deposit an interlayer dielectric layer 250, and then etch the interlayer dielectric layer 250 to form a contact hole. Then, perform step S430 to form a first electrode 262 and a second electrode 264, and obtain Figure 3 The first electrode 262 is electrically connected to the first N+ region 242 and the first P+ region 246, and the second electrode 264 is electrically connected to the second P+ region 248, the second N+ region 244 and the second body region 236. In addition to being applicable to the embodiment in which the step structure of the drift region is formed by reactive ion etching, the above steps S621 to S625 are also applicable to the embodiment in which the step structure of the drift region is formed by secondary epitaxy, except that the step structure formed by secondary epitaxy will be steeper.

[0118] Taking the manufacture of SOI diode as an example, the structure after step S420 is completed is as follows Fig.15a See Fig.14 The method for manufacturing the SOI diode further includes the following steps after step S420:

[0119] S721, forming an N-well.

[0120] The N well 334 can be formed by photolithography and ion implantation. Fig.15b The N-well 334 is formed on the second side of the step structure.

[0121] S722, forming a field oxide layer.

[0122] A field oxide layer 347 is formed on the surface of the drift region 330. Fig.15c The field oxide layer 347 can be formed by deposition or thermal oxidation.

[0123] S723, forming an anode region and a cathode region.

[0124] See also Fig.15d The N+ cathode region (ie, the second electrode lead-out region 344 ) is located in the N well 334 , and the P+ anode region (ie, the first electrode lead-out region 342 ) is formed on the first side of the step structure.

[0125] S724, forming an interlayer dielectric layer and contact holes.

[0126] Deposit an interlayer dielectric layer 350, and then etch the interlayer dielectric layer 350 to form a contact hole. Then, perform step S430 to form a first electrode 362 and a second electrode 364, and obtain Figure 5 The structure shown. The first electrode 362 is electrically connected to the P+ anode region, and the second electrode 364 is electrically connected to the N+ cathode region. In addition to being applicable to the embodiment in which the step structure of the drift region is formed by reactive ion etching, the above steps S721 to S724 are also applicable to the embodiment in which the step structure of the drift region is formed by secondary epitaxy, except that the step structure formed by secondary epitaxy will be steeper.

[0127] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0128] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0129] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0130] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A silicon-on-insulator semiconductor component, characterized in that: include: substrate; A buried dielectric layer is disposed on the substrate; a first electrode; a second electrode; A drift region is disposed on the buried dielectric layer; a step structure is formed on the upper surface of the drift region, the step structure includes a first side close to the first electrode, a second side close to the second electrode, and a transition region between the first side and the second side, the upper surface of the second side is higher than the lower surface of the first side, so that the thickness of the drift region on the second side is greater than the thickness on the first side; The first electrode and the second electrode are configured such that when a reverse bias is applied to the component, the voltage applied by the second electrode is greater than the voltage applied by the first electrode.

2. The silicon-on-insulator semiconductor device according to claim 1, characterized in that: The component is a lateral double diffused metal-oxide-semiconductor field effect transistor, the first electrode is a source, the second electrode is a drain, and the lateral double diffused metal-oxide-semiconductor field effect transistor also includes a gate.

3. The silicon-on-insulator semiconductor device according to claim 1, characterized in that: The component is a lateral insulated gate bipolar transistor, the first electrode is an emitter, the second electrode is a collector, and the lateral insulated gate bipolar transistor further includes a gate.

4. The silicon-on-insulator semiconductor device according to claim 1, characterized in that: The component is a diode, the first electrode is an anode, and the second electrode is a cathode.

5. The silicon-on-insulator semiconductor device according to any one of claims 1 to 4, characterized in that: The step structure is a step structure, including a first table located on the first side, a second table located on the second side, and a step wall located in the transition zone, the height difference between the second table and the first table is 3 to 10 microns, and / or the inclination angle of the step wall is 20 degrees to 90 degrees.

6. The silicon-on-insulator semiconductor device according to claim 5, characterized in that: The drift region has a first conductivity type, and the component also includes a second conductivity type protection layer, which is located in the drift region and surrounds the corner formed by the first table and the step wall and the corner formed by the second table and the step wall, and the first conductivity type and the second conductivity type are opposite conductivity types.

7. A silicon-on-insulator semiconductor process platform, characterized in that: The silicon-on-insulator semiconductor component comprises the silicon-on-insulator semiconductor component according to any one of claims 1 to 6, and further comprises a complementary metal-oxide-semiconductor field effect transistor and / or a well resistor.

8. A method for manufacturing a silicon-on-insulator semiconductor component, comprising: Obtaining a wafer, wherein the wafer includes a substrate, a buried dielectric layer on the substrate, and a drift region on the buried dielectric layer; Forming a step structure on the upper surface of the drift region by photolithography and etching, wherein the step structure includes a first side, a second side, and a transition region between the first side and the second side, wherein the upper surface of the second side is higher than the lower surface of the first side, so that the thickness of the drift region on the second side is greater than that on the first side; forming a first electrode and a second electrode; the first side is a side close to the first electrode, and the second side is a side close to the second electrode; The first electrode and the second electrode are configured such that when a reverse bias is applied to the component, the voltage applied by the second electrode is greater than the voltage applied by the first electrode.

9. The method for manufacturing a silicon-on-insulator semiconductor component according to claim 8, characterized in that: The etching is a reactive ion etching process.

10. A method for manufacturing a silicon-on-insulator semiconductor component, comprising: Obtaining a wafer, wherein the wafer includes a substrate, a buried dielectric layer on the substrate, and a first epitaxial layer on the buried dielectric layer; Forming a second epitaxial layer on a partial area of ​​the first epitaxial layer, forming a step structure at the junction of the first epitaxial layer and the second epitaxial layer, the step structure comprising a first side on one side of the second epitaxial layer, a second side on one side of the first epitaxial layer, and a transition area between the first side and the second side; forming a first electrode and a second electrode, wherein the first side is a side close to the first electrode, and the second side is a side close to the second electrode; The first electrode and the second electrode are configured such that when a reverse bias is applied to the component, the voltage applied by the second electrode is greater than the voltage applied by the first electrode.

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