Split gate MOSFET

Abstract

A semiconductor power device having an active region, the active region of the device comprising: at least two separate gate trench regions wherein two laterally adjacent separate gate trench regions are separated by a mesa region; and two or more contact regions of a first conductivity type in the mesa region. The contact region of the first conductivity type is in contact with the two adjacent split gate trench regions such that, in use, a channel is formed along one side of each split gate trench region. The device further includes: at least two insulating spacer regions over and aligned with the two or more contact regions of the first conductivity type; and a source contact extending from an upper surface of the device within the mesa region and between the at least two insulating spacer regions.

Description

Technical Field

[0001] The present disclosure relates to a power semiconductor device and a method of manufacturing a power semiconductor device. In particular, but not exclusively, the present disclosure relates to a split-gate metal oxide semiconductor field effect transistor (MOSFET). Background Art

[0002] Trench metal oxide semiconductor field effect transistors (MOSFETs) are well known and used in many applications. In a trench MOSFET, current is conducted vertically from one surface of the MOSFET to the other surface of the MOSFET. Split gate trench MOSFETs have improved performance and efficiency.

[0003] It is desirable to produce MOSFET devices with reduced cell pitches, for example with cell pitches less than 1.0 μm or less than 800 nm, which increases the reliance on lithographic resolution and alignment tolerances. To reduce the cell pitch, other device dimensions may need to be reduced. Lithography and contact-to-trench alignment are limiting factors in achieving such reduced cell pitch and device dimensions.

[0004] Any misalignment of the MOSFET's source contact and deviations in the contact-to-trench distance forces the implanted high dose of p-type dopant (in some examples, boron) into the conducting channel on one side of the cell, while depriving the other side of the cell of p-type dopant. This results in a difference in the threshold voltage (V T ) imbalance, which in turn affects the on-resistance (R ON ) and durability.

[0005] US 6,924,198 B2 relates to a MOSFET with misaligned contacts. US 7,910,439 B2, US 8,951,867 B2 and US 9,735,266 B2 relate to MOSFETs without a split gate structure. Summary of the invention

[0006] Various aspects and preferred features are set out in the appended claims.

[0007] According to a first embodiment, there is provided a semiconductor power device having an active region, the active region of the device comprising:

[0008] a drift region of a first conductivity type;

[0009] A body region of a second conductivity type disposed above the drift region, wherein the second conductivity type is opposite to the first conductivity type;

[0010] at least two split gate trench regions, which are in contact with the body region and the drift region, wherein two laterally adjacent split gate trench regions are separated by a mesa region;

[0011] two or more contact regions of a first conductivity type located in the mesa region and disposed above the body region, wherein the contact regions of the first conductivity type have a higher doping concentration than the doping concentration of the drift region, and wherein the contact regions are in contact with the two adjacent split-gate trench regions such that, in use, a channel is formed along one side of each split-gate trench region and within the body region;

[0012] a contact region of a second conductivity type located in the mesa region and disposed above the body region, wherein the contact region of the second conductivity type has a higher doping concentration than a doping concentration of the body region, and wherein the contact region of the second conductivity type contacts the two or more contact regions of the first conductivity type within the mesa region;

[0013] at least two insulating spacer regions overlying and aligned with the two or more contact regions of the first conductivity type;

[0014] A source contact extends from an upper surface of the device within the mesa region and between the at least two insulating spacer regions, wherein the source contact contacts the two or more contact regions of the first conductivity type and the contact region of the second conductivity type.

[0015] The split gate trench region improves the performance of the device. The insulating spacer region is used to align the contact region of the first conductivity type and the source contact within the mesa region. This improves the reliability and reproducibility of the device.

[0016] The semiconductor device may further include at least two insulating plug regions located above the separation gate trench region and adjacent to the dielectric spacer region. The insulating plug regions allow the insulating spacer region to be formed in a simple and reproducible manner by depositing an insulating layer and etching the insulating layer such that the etching process stops on the mesa region.

[0017] The insulating plug region may be formed of the same material as the insulating spacer region.Both the insulating plug region and the insulating spacer region may include oxide.

[0018] The insulating plug region may be formed of a different material from the insulating spacer region.The insulating plug region may include a nitride, and the insulating spacer region may include an oxide.

[0019] The semiconductor power device may be formed by the following method:

[0020] forming the at least two separation gate trench regions in the semiconductor region, wherein two separation gate trench regions adjacent in the lateral direction are separated by a mesa region;

[0021] etching a gate conductive region in an upper region of each separation gate trench region;

[0022] forming the at least two insulating plug regions on the etched gate conductive region, each insulating plug region being formed in a separation gate trench region; and

[0023] The semiconductor region is etched within the mesa region between two adjacent separation gate trench regions.

[0024] Etching the semiconductor region within the mesa region leaves the insulating plug region. The semiconductor region may be referred to as a semiconductor substrate. In some examples, the semiconductor region may include an initial substrate over which additional semiconductor layers are epitaxially grown.

[0025] The semiconductor power device may be formed by etching a groove in the body region of the second conductivity type in the mesa region. The etched groove may be defined by the insulating spacer region. Since the etched groove is defined by the spacer region, the alignment of the etched groove is highly reliable.

[0026] The contact region of the second conductivity type may be formed by implanting a dopant of the second conductivity type into the body region of the second conductivity type located below the etched groove. Due to the reliability of the position of the etched groove, the implantation of the dopant is also highly reliable.

[0027] The source contact may be formed by depositing a conductive material in the etched groove. Due to the reliability of the position of the etched groove, the position of the source contact is also highly reliable.

[0028] The split gate trench regions may each include:

[0029] a gate conductive region formed in an upper portion of each separation gate trench region;

[0030] a source conductive region formed in a lower portion of each separation gate trench region; and

[0031] An insulating layer is formed along the sidewalls and the lower surface of each separation gate trench region and between the gate conductive region and the source conductive region.

[0032] The semiconductor power device may further include an edge termination region. The edge termination region may be laterally located between the active region and a side surface of the semiconductor device.

[0033] The edge termination region may include a gate terminal having one or more separation gate trench regions.

[0034] The edge termination region may include a source terminal having one or more source trench regions.

[0035] The semiconductor device may include a metal oxide semiconductor field effect transistor (MOSFET).

[0036] According to another aspect of the present disclosure, a method for manufacturing an active region of a semiconductor power device is provided, the method comprising:

[0037] forming at least two separation gate trench regions in the semiconductor region, wherein two separation gate trench regions adjacent in a laterally direction are separated by a mesa region;

[0038] etching a gate conductive region in an upper region of each separation gate trench region;

[0039] forming at least two insulating plug regions on the etched gate conductive region, each insulating plug region being formed in a separation gate trench region; and

[0040] The semiconductor region is etched within the mesa region between two adjacent separation gate trench regions.

[0041] Forming at least two insulating plug regions over the etched gate conductive region in the separation gate trench region may include: forming an insulating region over the entire surface of the active area; and planarizing the insulating region to form the insulating plug regions.

[0042] Etching the gate conductive region may include: etching the gate conductive region so that an upper surface of the gate conductive region is substantially lower than an upper surface of the semiconductor region.

[0043] Etching the semiconductor region may include etching the semiconductor region in the mesa region between two adjacent separation gate trench regions so that the upper surface of the mesa region is substantially lower than the upper surface of the insulating plug region. This allows the etchant process for forming the insulating spacer region to self-terminate on the semiconductor region in the mesa region while leaving the insulating spacer.

[0044] The method also includes: forming at least two insulating spacer regions above the etched mesa region of the semiconductor region and adjacent to the insulating plug region; and etching a groove in the mesa region of the semiconductor region, wherein the groove is defined by the insulating spacer region. This ensures the precise and reliable position of the etched groove.

[0045] Forming at least two insulating spacer regions may include: forming an insulating layer over the at least two insulating plug regions and the mesa region between the at least two separation gate trench regions; and etching the insulating layer using an etching process, wherein the etching process terminates on the upper surface of the semiconductor region within the mesa region.

[0046] The method may further include implanting a dopant of the second conductivity type into the semiconductor substrate beneath the etched recess.

[0047] The method may further include depositing a conductive material in the etched recess to form a source contact.

[0048] According to yet another aspect of the present disclosure, a method for manufacturing a semiconductor power device is provided, comprising: manufacturing an active region of the semiconductor power device as described above; and simultaneously manufacturing an edge termination region.

[0049] The edge termination region may include a gate terminal having one or more separation gate trench regions. The separation gate trench regions of the gate terminal may be formed in the same process as the separation gate trench regions of the active region.

[0050] The edge termination region may include a source terminal having one or more source trench regions. The source trench regions of the source terminal may be formed in the same process as the split gate trench regions of the active region.

[0051] Compared with the devices in the prior art, the device and manufacturing method disclosed in the present invention have the following advantages:

[0052] - The device has the improved performance and efficiency of a split-gate MOSFET while having precisely aligned contacts in the active area;

[0053] - constructing spacers formed of insulating material (e.g., oxides such as silicon dioxide) around the gate plug dielectric. The spacers are used to etch contacts that are precisely aligned with respect to the main trench network;

[0054] - Highly accurate self-alignment of etched recesses for source metal contacts and doped contact regions relative to trenches in the active area of ​​the device enables optimal device performance by balanced current flow in the on-state as well as in the off-state during unclamped current switching events;

[0055] - The manufacturing method is compatible with oxide gate plugs or nitride gate plugs to build spacers;

[0056] - the manufacturing steps can be performed using materials and processing equipment commonly available in MOSFET manufacturing plants;

[0058] - the double recess etch step of the method for forming the plug dielectric can be performed using the same chemistry used for planarizing the gate polysilicon region and etching the source contact recess;

[0059] - The edge termination contacts are fully integrated, enabling simultaneous fabrication of gate terminals in a single set of processing steps

[0060] sub, source-polysilicon terminal and source-mesa terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Some embodiments of the present disclosure will now be described, by way of example only, and with reference to the accompanying drawings, in which:

[0062] Figure 1 schematically illustrates a cross section of a MOSFET according to an embodiment of the present disclosure;

[0063] Figure 2 The steps in the method of manufacturing a MOSFET according to an embodiment of the present disclosure are shown;

[0064] Figure 3 schematically illustrates a cross section of an active region of a MOSFET according to an embodiment of the present disclosure, wherein a spacer is formed over an oxide plug;

[0065] Figure 4 schematically illustrates a cross-section of an active region of an alternative MOSFET according to an embodiment of the present disclosure, wherein a spacer is formed over a nitride plug;

[0066] Figure 5 schematically illustrates a cross section of a gate terminal contact within an edge termination region of a MOSFET according to an embodiment of the present disclosure;

[0067] Figure 6 schematically illustrates a cross section of a source terminal contact within an edge termination region of a MOSFET according to an embodiment of the present disclosure;

[0068] Figure 7 The steps of the method for manufacturing the active region of a MOSFET according to an embodiment of the present disclosure are shown;

[0069] Figure 8Steps of a method of manufacturing an active region of a replacement MOSFET according to an embodiment of the present disclosure are shown, wherein spacers are formed over nitride plugs;

[0070] Fig. 9 The steps of a method for manufacturing a gate terminal contact in an edge termination region of a MOSFET according to an embodiment of the present disclosure are shown; and

[0071] Fig.10 Steps of a method of manufacturing a source terminal contact in an edge termination region of a MOSFET according to an embodiment of the present disclosure are shown. DETAILED DESCRIPTION

[0072] Figure 1 A cross section of an active region 100 of a semiconductor device according to an embodiment of the present disclosure is schematically shown. In the examples described herein, the device is a silicon-based split-gate trench MOSFET. However, those skilled in the art will appreciate that the device may include alternative semiconductor materials; for example, the device may be silicon carbide (SiC) or gallium nitride (GaN-based). The device may also be an insulated gate bipolar transistor (IGBT).

[0073] The active region 100 includes an n-type voltage sustaining region (or n-drift region) 105 formed on or above a semiconductor substrate. In this example, the n-drift region 105 is an epitaxial layer. Although not shown, the device may include a drain or collector region located below the drift region 105. In the example shown, the device includes two gate trenches 120, each extending downward from the upper surface of the n+ contact region 115 into the n-drift region 105. During operation, a conductive channel is formed between the n+ contact region 115 and the drift region 105 by applying a positive voltage to the gate.

[0074] Two gate trenches 120 are formed that are spaced apart from each other in the laterally direction. Although only two gate trenches 120 are shown as an example, it should be understood that the device may include more gate trenches. Each gate trench 120 includes an insulating layer 135 formed along the inner sidewall and lower surface of the gate trench 120. In this example, the insulating layer 135 is an oxide layer (e.g., silicon dioxide), but other insulating materials may also be used. In examples in which the insulating layer 135 is a silicon dioxide liner, the silicon dioxide liner 135 may be thermally grown and / or deposited. In one example, a first portion of the insulating layer 135 is thermally grown (e.g., 5% of the insulating layer), and the remaining portion of the insulating layer 135 is deposited over the thermally grown portion.

[0075] The gate trenches 120 have a split gate structure including a gate conductive polysilicon region 140 formed in an upper portion of each trench 120 and a trench shield 130 (or a source polysilicon region) formed in a lower portion of each trench 120. The gate polysilicon region 140 and the trench shield 130 of each trench are separated by an insulating layer 135.

[0076] Along the upper portion, the insulating layer is thinner and the gate conductive region 140 defines a vertical channel. In the lower portion of the gate trench 120, the insulating layer is thicker than the upper portion, so the conductive source polysilicon region 130 acts as a field plate at source potential and is insulated from the drain region of the device by the thicker insulating layer. The conductive region 140 and the trench shield 130 can be formed of a conductive material such as a metal or doped polysilicon.

[0077] A p-body region 110 is provided above the n-drift region 105 and adjacent to and between the two gate trenches 120. The p-body region 110 is a p-type doped semiconductor and generally extends to a depth in the device that corresponds to the depth of the gate conductive region 140. The depth of the p-body region 110 may be less than the depth of the gate conductive region 140 in order to ensure that the gate conductive region 140 can provide switching along the full length of the p-body region 110. An n+ contact region 115 is provided above the p-body region 110.

[0078] Two adjacent gate trenches 120 are separated by a mesa region. A p+ contact region 145 is formed in the p body region 110 within the mesa region and below the source contact 155 .

[0079] Source contacts 155 are formed in the mesa regions 125 laterally between adjacent trenches 120 and extend from the upper surface of the device toward the p-body region 110. To align the source contacts 155 in the mesa regions, spacers 160 formed of an insulating material are located above the n+ contact regions 115 on either side of each gate trench 120. In addition, the p+ contact regions 145 (also referred to as contact implants) are automatically aligned by the spacers 160.

[0080] Another insulator region (or plug dielectric) 165 is located above the surface of each gate trench 120 between the two spacers 160. The plug dielectric 165 extends or protrudes above the upper surface of the semiconductor substrate. The plug dielectric 165 acts as a spacer or insulator between the gate and source contacts 155 and, due to its thickness, can support the necessary drain-source breakdown voltage (BV) in the edge termination region of the RESURF device. dss ).

[0081] Spacers 160 are formed around plug dielectric 165 and are used to etch a precisely aligned source contact 155 relative to gate trench 120. Spacers 160 built or formed around the protruding or protruding plug dielectric 165 provide consistent alignment of the source 155 contact relative to the gate trench 120 with significantly reduced misalignment and a large process window. In this example, spacers 160 are formed of an oxide region (e.g., silicon dioxide). Plug dielectric 165 can be formed of TEOS.

[0082] Figure 2 (a) to Figure 2 (e) shows a method for manufacturing a split-gate MOSFET (such as Figure 1 The steps in the method are as follows: an active region of a MOSFET shown in FIG. Figure 2 Many of the features shown in Figure 1 The features shown in are similar and therefore have the same reference numerals. It should be understood that Figure 2 The steps shown in show a subset of all the steps for making the device, and the method may also include Figure 2 Additional steps before or after the step, such as Figures 7 to 10 Although Figure 2 (a) to Figure 2 (e) shows the step of fabricating an active area with two gate trenches 120, but it should be understood that the method can be used to fabricate more than two gate trenches.

[0083] Figure 2 (a) shows the first step in manufacturing a split-gate MOSFET as follows:

[0084] - Chemical mechanical planarization (CMP) is used to planarize the conductive polysilicon region 140. This removes excess material and creates a smooth surface on the upper surface of the conductive polysilicon region 140, so that the conductive polysilicon region 140 has an upper surface that is substantially aligned with the upper surface of the mesa region.

[0085] Figure 2 (b) shows the second step of manufacturing a split-gate MOSFET, as follows:

[0086] - A first etching step is performed to etch the conductive polysilicon region 140 within each gate trench 120 so that the conductive polysilicon region 140 is recessed below the upper surface of the device and the mesa region.

[0087] Figure 2 (c) shows the third step of manufacturing a split-gate MOSFET, as follows:

[0088] - Form or deposit a thick oxide layer 170 on the upper surface of the device to fill in the Figure 2 (b) The groove formed in the step shown.

[0089] Figure 2 (d) shows the fourth step of manufacturing a split-gate MOSFET, as follows:

[0090] - Planarizing thick oxide layer 170 using chemical mechanical planarization (CMP) to form insulating plug regions 165. This removes excess material and creates a smooth surface on the upper surface of insulating plug regions 165, so that insulating plug regions 165 have upper surfaces that are substantially aligned with the upper surfaces of the mesa regions.

[0091] Figure 2 (e) shows the fifth step of manufacturing a split-gate MOSFET, as follows:

[0092] The silicon mesa regions 125 located between adjacent gate trenches 120 are etched to form grooves between adjacent insulating plug regions 165 located above adjacent gate trenches 120 .

[0093] This double recess etching process enables the formation of a protruding plug dielectric region 165, which in turn enables the formation of the insulating spacer 160. The plug dielectric region 165 is formed over the gate polysilicon region 140, and is formed of SiO2 or Si3N4 after the gate polysilicon region 140 is formed.

[0094] The double recess etching process includes (i) etching the gate polysilicon 140 within the gate trenches 120, followed by (ii) etching the silicon in the mesa regions 125 between adjacent trenches 120. The insulating spacers 160 are used to align the source contacts 155 in the active area of ​​the device by acting as a hard mask during the steps of etching the recesses for the source contacts 155 and implanting the p+ contact regions 145. The disclosed device and fabrication method eliminate the requirement for strict alignment when etching the recesses for the source metal contacts 155 and implanting the p+ source contact regions 145. This improves the stability and repeatability of the fabricated device.

[0095] Figure 2 (b) and Figure 2 The dry etching step shown in (e) can be performed using a HBr / O2 dry etching chemistry with a Si / dielectric selectivity in the range of 10-50:1. Figure 7 (w) as shown, this can be used in the same way as for Figure 2 (a) shows a dry etch chemistry for planarizing the gate polysilicon region 140 and etching a recess for the source contact 155 .

[0096] Although Figure 2The etching back of the gate polysilicon region 140 shown in (b) allows the micro-topography to be generated on the gate polysilicon region 140, but using Figure 2 (b) and Figure 2 The etching process shown in (e) can achieve a defect-free etching depth of 400nm.

[0097] Using HBr / O2 dry etching chemistry Figure 2 The etching of the epitaxial silicon in the mesa region shown in (e) ensures that the bottom of the etched groove has a smooth finish, that is, essentially free of pits and microstructures. This ensures that Figure 2 The surface finish of the mesa region produced after the etching process of (e) is indistinguishable from the surface finish of the epitaxial growth as delivered.

[0098] The outer sidewalls of the trench 120 are formed of an oxide dielectric and are therefore highly resistant to etching using HBr / O2 dry etching chemistry. However, any microscopic topography can be removed by growing and removing a thin oxide layer (approximately ) to remove or repair.

[0099] Figure 3 1 shows a cross section of an active region 100 of a MOSFET, wherein an insulating spacer 160 is formed over an oxide plug region 165, and Figure 4 A cross section of an active region 100 of an alternative MOSFET is schematically shown, wherein insulating spacers 160 are formed over nitride plug regions 170 . Figure 3 and Figure 4 Many of the features shown in Figure 1 and Figure 2 The features shown in are similar and therefore have the same reference numerals. Figures 3 to 6 Simulated doping concentrations for the illustrated device are shown. Figure 2 The method is compatible with forming the oxide dielectric plug 165 or the nitride dielectric plug 170 before forming the spacer 160 .

[0100] Figure 5 The cross section of the gate terminal in the edge termination region 200 of the MOSFET according to the embodiment of the present disclosure is schematically shown. It should be understood that Figure 5 The edge termination region 200 shown in FIG. 1 may be formed in the same device as the active region 100 of the MOSFET, such as Figures 1 to 4 as shown in . Figure 5 and Figure 6 The edge termination region and edge termination contacts shown may be fully integrated, allowing the gate, source-polysilicon, and source-mesa terminals to be fabricated simultaneously in the same set of processing steps.

[0101] The edge termination region 200 includes an n-type voltage sustaining region (or n-drift region) 205. In this example, the n-drift region 205 is an epitaxial layer. Although not shown, the device may include a drain or collector region located below the drift region 205. The device includes two gate trenches 220, each of which extends downward into the n-drift region 205. Although only two gate trenches 220 are shown as an example, it should be understood that the device may include more than two gate trenches.

[0102] Two gate trenches 220 are formed that are spaced apart from each other in the lateral direction. Although only two gate trenches 220 are shown as an example, it should be understood that the device may include more gate trenches. Each gate trench 220 includes an insulating layer 235 formed along the inner sidewall and lower surface of the gate trench 220. In this example, the insulating layer 235 is an oxide layer (e.g., silicon dioxide), but other insulating materials may also be used. In the example where the insulating layer 235 is a silicon dioxide liner, the silicon dioxide liner 235 may be thermally grown and / or deposited.

[0103] The gate trenches 220 have a split gate structure including a conductive polysilicon region 240 formed in an upper portion of each trench 220 and a trench shield 230 formed in a lower portion of each trench 220. The polysilicon region 240 and the trench shield 230 of each trench are separated by an insulating layer 235. The conductive region 240 and the trench shield 230 may be formed of a conductive material such as metal or doped polysilicon.

[0104] Above the n drift region 205 and adjacent to and between the two gate trenches 220, a p body region 210 is provided. The p body region 210 is a p-type doped semiconductor and typically extends to a depth into the device that corresponds to the depth of the gate conduction region 240.

[0105] Two adjacent gate trenches 220 are separated by a mesa region 225. An insulating layer 260 is formed in the mesa region over the upper surfaces of the gate trenches 220 and the p body region 210. Two gate contacts 255 are formed, each extending through the insulating layer 260 into the conductive polysilicon region 240 of each gate trench 240.

[0106] Figure 6 Schematically illustrates a cross section of a source terminal in an edge termination region 300 of a MOSFET according to an embodiment of the present disclosure. It should be understood that Figure 6 The edge termination region 300 shown in FIG. Figures 1 to 4 The active region 100 of the MOSFET shown in FIG. Figure 5 Another edge termination region 200 shown in FIG. 1 is formed in the same device.

[0107] The edge termination region 300 includes an n-type voltage sustaining region (or n-drift region) 305. In this example, the n-drift region 305 is an epitaxial layer. Although not shown, the device may include a drain or collector region located below the drift region 305. The device includes two auxiliary trenches 320 (or dummy trenches), each of which extends downward into the n-drift region 305. Although only two auxiliary trenches 320 are shown as an example, it should be understood that the device may include more than two auxiliary trenches.

[0108] Two auxiliary trenches 320 are formed that are spaced apart from each other in the lateral direction. Although only two auxiliary trenches 320 are shown as an example, it should be understood that the device may include more auxiliary trenches. Each auxiliary trench 320 includes an insulating layer 335 formed along the inner sidewall and lower surface of the auxiliary trench 320. In this example, the insulating layer 335 is an oxide layer (e.g., silicon dioxide), but other insulating materials may also be used. In the example where the insulating layer 335 is a silicon dioxide liner, the silicon dioxide liner 335 may be thermally grown and / or deposited.

[0109] The auxiliary trench 320 has a trench shield 330 formed through the depth of the auxiliary trench 320. The trench shield 330 may be formed of a conductive material such as metal or doped polysilicon.

[0110] A p-body region 310 is provided above the n-drift region 305 and adjacent to and between the two auxiliary trenches 320. The p-body region 310 is a p-type doped semiconductor. Two adjacent auxiliary trenches 320 are separated by a mesa region. A highly doped p+ contact region 345 is formed within the p-body region 310 within the mesa region.

[0111] An insulating layer 360 is formed in the mesa region 325 over the upper surfaces of the auxiliary trench 320 and the p body region 310. Three source contacts 355 are formed, each extending through the insulating layer 360. Two source contacts 355a extend to the trench shield 330 of each auxiliary trench 340, and a third source contact 355b extends to the p+ contact region 345 in the mesa region.

[0112] Figure 7 (a) to Figure 7 (z) shows an active region 100 (such as a MOSFET) of a fabricated MOSFET according to an embodiment of the present disclosure. Figure 1 and Figure 3 Many features and Figures 1 to 3 The features shown in FIG. 1 are identical and therefore have the same reference numerals. It should be understood that Figure 7 The steps shown in may show a subset of all the steps for making the device, and the method may also include Figure 7It should also be understood that Figure 7 (m) to Figure 7 (q) indicates Figure 2 (e) to Figure 2 (e) shows the same steps. Figure 7 and Figure 8 The steps of fabricating an active area having two gate trenches 120 are shown, but it is understood that the method can be used to fabricate more than two gate trenches.

[0113] Figure 7 The steps of the method shown in are performed in the following order from (a) to (z):

[0114] (a) Two trenches 120 are dry-etched in a semiconductor region. In this example, the semiconductor region includes a substrate with an epitaxial layer on top of the substrate. In the example shown, the semiconductor region includes a silicon region 702 with a nitride layer 704 located on top of the silicon region 702. The nitride layer may be Si3N4 and is used as a hard mask or resist layer to define the trenches during the dry etching process;

[0115] (b) A thin circular oxide layer 706 is formed on the inner wall of each trench 120. The thin circular oxide layer 706 is grown and immediately stripped off. This removes the Figure 7 (a) removes any micro defects on the sidewalls of the trench introduced by the previous dry etching step, and rounds any sharp corners of the trench. In the example shown, the thickness of the thin circular oxide layer 706 is between 100 and within the scope of

[0116] (c) performing a hard mask strip process to remove the nitride layer from the silicon substrate 702;

[0117] (d) thermally growing a thin oxide layer on the inner wall and lower surface of each trench and on the upper surface of the mesa region between adjacent trenches. A thicker oxide layer is deposited on top of the thin oxide layer. A double oxide layer 708 is formed in this two-stage process to control the doping inside the mesa region 125. The thin oxide layer may have a thickness between 20 and 500 nm, and the thick oxide layer may have a thickness between 80 and 1000 nm to provide an oxide liner 708 of 100 to 1500 nm thickness. In the example shown, the thin oxide layer may have a thickness of approximately 44 nm, and the thick oxide layer may have a thickness of approximately 120 nm to provide an oxide liner 708 of approximately 164 nm thickness;

[0118] (e) forming source polysilicon 710 in the two trenches and on the upper surface of the device;

[0119] (f) using chemical mechanical planarization (CMP) to planarize the source polysilicon 710;

[0120] (g) performing an etching process to etch the source polysilicon 710 in the trench so that the source polysilicon 710 is recessed below the upper surface of the trench and a trench shield 130 is formed;

[0121] (h) performing a further etching process to etch back the oxide layer in the mesa region and along the sidewalls of the trench above the source polysilicon, such that a thick oxide liner 708 (having a thickness of approximately 164 nm in this example) remains along the sidewalls adjacent to the source polysilicon 710, but only a thin oxide layer 712 remains along the sidewalls of the mesa region and the trench at a shallower depth than the source polysilicon, wherein the thin oxide layer 712 has a thickness that is significantly less than the thick oxide liner 708;

[0122] (i) depositing another oxide 714 over the source polysilicon in the trench using high density plasma chemical vapor deposition;

[0123] (j) performing a high precision etching process to etch the surface of the further oxide 714 deposited in the trenches above the trench shield 130 in step (i) and remove all of the thin oxide layer 712 along the upper portions of both sidewalls of each trench;

[0124] (k) another thin oxide layer 716 is then formed along the upper portion of the sidewalls of each trench by oxidizing the silicon region;

[0125] (l) depositing a conductive polysilicon region 718 over the device and within each trench;

[0126] (m) planarizing the conductive polysilicon region 718 using chemical mechanical planarization (CMP) or using a planarizing dry etch step;

[0127] (n) performing an etching step to etch the conductive polysilicon region 718 within each gate trench so that the conductive polysilicon region 718 is recessed below the mesa region. This forms the gate polysilicon region 140;

[0128] (o) forming or depositing another thick oxide layer 720 or plug over the upper surface of the device;

[0129] (p) using chemical mechanical planarization (CMP) to planarize the thick oxide layer 720 to form the insulating plug region 165;

[0130] (q) etching the silicon mesa region between adjacent gate trenches to form a groove between the adjacent gate trenches;

[0131] (r) growing or depositing a screen oxide layer 722 over the upper surface of the device;

[0132] (s) implanting p-type dopants into the mesa region below the screen oxide layer 722 to form a p-body region 110;

[0133] (t) implanting n-type dopants into the mesa region above the p-body region 110 and below the shielding oxide layer 722 to form an n+ contact region 115;

[0134] (u) depositing an oxide layer 724, in this example silicon dioxide (e.g., tetraethyl orthosilicate (TEOS)) over the upper surface of the device in a furnace or low pressure chemical vapor deposition (LPCVD) tool. Alternatively, a similar insulating layer (e.g., BPSG glass) may be deposited in a high density plasma CVD tool or undoped silicon glass may be deposited;

[0135] (v) forming spacers by etching the TEOS layer 724 until it ends at the upper surface of the silicon region 702 (in this example, on the upper surface of the n+ contact region 115) and self-terminates. This step etches the TEOS (or other insulator) layer 724 until it reaches an end point when the etching has removed all of the TEOS layer 724 in one area and begins etching the silicon region 702. In an example, this step may self-terminate when the etching process transitions from etching the TEOS layer 724 to etching the silicon region 702;

[0136] (w) etching a trench or recess through the n+ contact region 115 in the mesa region 125, which extends down to the p body region 110. This self-aligned etching process is limited by the spacers 160, and thus the alignment of the recess relative to the trench 120 is defined by the spacers 160. Since the etched recess is defined by the spacers 160, this eliminates the requirement for strict alignment when etching the recess for the source contact 155 and implanting the p+ contact region 145;

[0137] (x) implanting p-type dopants (e.g., boron) under the recess and into the p-body region 110 to form a p+ contact region 145. The p+ contact region 145 (also referred to as a contact implant) is self-aligned by the spacer 160. Annealing the p+ contact region 145 after implantation;

[0138] (y) depositing a metal barrier layer 726 such as titanium or titanium nitride (Ti / TiN) over the surface of the device and annealing it;

[0139] (z) A metal contact layer 728, in this example an aluminum-copper alloy, is formed over the device by sputtering. The metal contact layer 728 extends into the etched recesses.

[0140] Figure 8 The steps of a method for manufacturing an active region 100 of a replacement MOSFET according to an embodiment of the present disclosure are shown, wherein in a case such as Figure 4 Spacers are formed over the nitride plugs in the active area shown in FIG. Many features are similar to Figure 4 The features shown in FIG. 1 are identical and therefore have the same reference numerals. It should be understood that Figure 8 The steps shown in may show a subset of all the steps for making the device, and the method may also include Figure 8 In particular, note that Figure 7 (a) to Figure 7 The steps shown in (l) can be in Figure 8 Before the steps shown in .

[0141] Figure 8 The steps of the method shown in are performed in the following order from (a) to (n):

[0142] (a) planarizing the conductive polysilicon region 718 using chemical mechanical planarization (CMP) or a planarizing dry etch step;

[0143] (b) performing an etching step to etch the conductive polysilicon region 718 in each gate trench so that the conductive polysilicon region 718 is recessed below the mesa region. This forms the gate polysilicon region 140;

[0144] (c) forming or depositing another thick nitride layer 820 or plug over the upper surface of the device;

[0145] (d) using chemical mechanical planarization (CMP) to planarize the thick nitride layer 820 to form an insulating nitride plug region 170;

[0146] (e) etching the silicon mesa region between adjacent gate trenches to form a groove between the adjacent gate trenches;

[0147] (f) growing or depositing a screen oxide layer 722 over the upper surface of the device;

[0148] (g) implanting p-type dopants into the mesa region below the screen oxide layer 722 to form a p-body region 110;

[0149] (h) implanting n-type dopants into the mesa region above the p-body region 110 and below the screen oxide 722 layer to form an n+ contact region 115;

[0150] (i) depositing an oxide layer 724, in this example silicon dioxide (e.g., tetraethyl orthosilicate (TEOS)) over the upper surface of the device in a furnace or low pressure chemical vapor deposition (LPCVD) tool. Alternatively, a similar insulating layer (e.g., BPSG glass) may be deposited in a high density plasma CVD tool or undoped silicon glass may be deposited;

[0151] (j) forming spacers by etching the TEOS layer 724 until it ends at the upper surface of the silicon region 702 (in this example, on the upper surface of the n+ contact region 115) and self-terminates. This step etches the TEOS (or other insulator) layer 724 until it reaches an end point when the etching has removed all of the TEOS layer 724 in one area and begins etching the silicon region 702. In an example, this step may self-terminate when the etching process transitions from etching the TEOS layer 724 to etching the silicon region 702;

[0152] (k) etching a trench or recess through the n+ contact region 115 in the mesa region 125, which extends down to the p body region 110. This self-aligned etching process is limited by the spacers 160, and thus the alignment of the recess relative to the trench 120 is defined by the spacers 160. Since the etched recess is defined by the spacers 160, this eliminates the requirement for strict alignment when etching the recess for the source contact 155 and implanting the p+ contact region 145;

[0153] (1) implanting p-type dopants under the groove and into the p-body region 110 to form a p+ contact region 145. The p+ contact region 145 (also referred to as a contact implant) is automatically aligned by the spacer 160;

[0154] (m) depositing a metal barrier layer 726 such as titanium or titanium nitride (Ti / TiN) over the surface of the device and annealing it;

[0155] (n) Metal contacts 728, in this example an aluminum-copper alloy, are formed over the device by sputtering. The metal contacts 728 extend into the etched recesses.

[0156] Fig. 9 FIG. 2 shows an edge termination region 200 (such as a MOSFET) of an embodiment of the present disclosure. Figure 5 Many features and Figure 5 The features shown in FIG. 1 are identical and therefore have the same reference numerals. It should be understood that Fig. 9 The steps shown in may show a subset of all the steps for making the device, and the method may also include Fig. 9 In particular, note that Figure 7 (a) to Figure 7 The steps shown in (s) can be in Fig. 9 Before the steps shown in . Figure 7 (a) to Figure 7 The steps shown in (u) may be performed in the edge termination region to form Fig. 9 The intermediate device shown in (a), however, may use photolithography or masking to prevent the implantation of n-type dopants within the edge termination region 200 for forming the n+ contact region 115 within the active region.

[0157] Although Fig. 9 The steps of fabricating the edge termination region 200 having two gate trenches are shown, but it should be understood that the method can be used to fabricate more than two gate trenches.

[0158] Fig. 9 The steps of the method shown in are performed in the following order from (a) to (f):

[0159] (a) Deposit an oxide layer 920, in this example silicon dioxide, over the upper surface of the device. The oxide layer 920 may be deposited on the Figure 7 Deposited in the same process as forming the TEOS layer 724 in the active area in the step shown in (u);

[0160] (b) forming a mask 930 defining the location of the gate contacts, and performing an etching process to form two recesses extending through the oxide layer to the conductive polysilicon region of each gate trench;

[0161] (c) implanting p-type dopants (e.g., boron) in each recess to form a gate contact. Figure 7 The p+ contact region 145 shown in (x) is performed in the same step;

[0162] (d) Fig. 9 The gate contact formed in the step shown in (c) is annealed;

[0163] (e) Forming a metal barrier layer 926, such as titanium and / or titanium nitride (Ti / TiN), over the surface of the device:

[0164] (f) Metal contacts 928, in this example an aluminum-copper alloy, are formed over the device.

[0165] It should be understood that Fig. 9 The steps shown in Figure 7 or Figure 8 The steps shown in are performed additionally and / or simultaneously to form the active area and edge termination region of the MOSFET device.

[0166] Fig.10FIG. 1 shows an embodiment of the present disclosure in which a MOSFET edge termination region (such as Figure 6 Many features and Figure 6 The features shown in FIG. 1 are identical and therefore have the same reference numerals. It should be understood that Fig.10 The steps shown in may show a subset of all the steps for making the device, and the method may also include Fig.10 Additional steps before or after the step.

[0167] It should also be understood that Fig.10 (a) to Fig.10 (f) indicates Figure 7 (a) to Figure 7 The same steps as shown in (f) and can be performed simultaneously using the same process.

[0168] Although Fig.10 The steps of fabricating the edge termination region 300 having two source trenches are shown, but it should be understood that the method can be used to fabricate more than two source trenches.

[0169] Fig.10 The steps of the method shown in are performed in the following order from (a) to (z):

[0170] (a) Two trenches 320 are dry-etched in a semiconductor region. In this example, the semiconductor region includes a substrate with an epitaxial layer on top of the substrate. In the example shown, the semiconductor region includes a silicon region 1002 with a nitride layer 1004 located on top of the silicon region 1002. The nitride layer may be Si3N4 and is used as a hard mask or resist layer in the dry etching process to define the trenches;

[0171] (b) A thin circular oxide layer 1006 is formed on the inner wall of each trench. The thin circular oxide layer 1006 is grown and immediately stripped off. This removes the Fig.10 The thin, rounded oxide layer 1006 has a thickness of 100 to 200 μm. within the scope of

[0172] (c) performing a hard mask stripping process to remove the nitride layer from the silicon substrate 1002;

[0173] (d) thermally growing a thin oxide layer on the inner wall and lower surface of each trench and on the upper surface of the mesa region between adjacent trenches. A thicker oxide layer is deposited on top of the thin oxide layer. A double oxide layer 1008 is formed in this two-stage process to control the doping inside the mesa region 325. The thin oxide layer may have a thickness between 20 and 500 nm, and the thick oxide layer may have a thickness between 80 and 1000 nm to provide an oxide liner 1008 of 100 to 1500 nm thickness. In the example shown, the thin oxide layer may have a thickness of approximately 44 nm, and the thick oxide layer may have a thickness of approximately 120 nm to provide an oxide liner 1008 of approximately 164 nm thickness;

[0174] (e) forming source polysilicon 1010 in the two trenches and on the upper surface of the device;

[0175] (f) Chemical mechanical planarization (CMP) is used to planarize the source polysilicon to form Figure 6 The source polysilicon 330 of the device shown;

[0176] (g) An inter-polysilicon oxide (IPO) photolithography resist mask 1030 is formed over the upper surface of the device. The IPO photolithography resist mask 1030 prevents Figure 7 The etching process shown in (g) removes the source polysilicon 330;

[0177] (h) performing a further etching process to etch back the oxide layer in the mesa region and along the sidewalls of the trench above the source polysilicon so that the source polysilicon 330 extends slightly above the oxide layer;

[0178] (i) depositing another oxide 1014 over the surface of the device using high density plasma chemical vapor deposition;

[0179] (j) A gate defining resist mask 1032 is formed over the upper surface of the device to preserve another oxide 1014 in the edge termination region. The gate defining resist mask 1032 prevents Figure 7 The etching process shown in (j) removes another oxide 1014;

[0180] (k) Oxidizing the source polysilicon 330. The source polysilicon 330 is covered by another oxide 1014 and will only undergo a small amount of oxidation, while at the same time in the active area, the silicon region is oxidized to form another thin oxide layer 716, such as Figure 7 As shown in (k);

[0181] (l) forming a gate polysilicon layer 1034 on the upper surface of the device;

[0182] (m) planarizing the gate polysilicon layer using chemical mechanical planarization (CMP);

[0183] (n) An etching step is performed to etch the gate polysilicon region 1034. This can be Figure 7 (m) and Fig.10 The flattening shown in (m) is performed simultaneously;

[0184] (o) forming or depositing a thick oxide layer 1020 or plug over the upper surface of the device;

[0185] (p) planarizing the thick oxide layer 1020 using chemical mechanical planarization (CMP);

[0186] (q) Etching the silicon mesa region between adjacent gate trenches to form recesses between adjacent source trenches. Figure 7 The same steps as shown in (q) are performed;

[0187] (r) growing or depositing a screen oxide layer 1022 over the upper surface of the device;

[0188] (s) implanting p-type dopants into the mesa region below the shielding oxide layer 1020 to form a p-body region 310;

[0189] (t) there is no step of implanting n-type dopants in the edge termination region. In some embodiments, another photolithography mask (not shown) may be located over the edge termination region and prevents implantation of n-type dopants in the edge termination region;

[0190] (u) depositing an oxide layer 724, in this example silicon dioxide (e.g., tetraethyl orthosilicate (TEOS)) over the upper surface of the device in a furnace or low pressure chemical vapor deposition (LPCVD) tool. Alternatively, a similar insulating layer (e.g., BPSG glass) may be deposited in a high density plasma CVD tool or undoped silicon glass may be deposited;

[0191] (v) A mask 1036 is formed to define the location of the source contacts, and an etching process is performed to form three recesses extending through the oxide layer. Because there are no spacers in the edge termination area, the mask 1036 is used to define and form the contacts. In some embodiments, as shown in FIG. Fig. 9 and Fig.10 The contacts formed in the edge termination region shown in are manufactured using a stepper as a separate process step because the functionality of the device is not affected by the alignment of the contacts in the edge termination region;

[0192] (w) implanting a p-type dopant (e.g., boron) into each recess to form a source contact. This is performed using the same steps as shown in Figure (x);

[0193] (x) Fig.10 After the implantation step shown in (x), the p+ source contact is annealed;

[0194] (y) Forming a metal barrier layer 1026, such as titanium or titanium nitride (Ti / TiN), over the surface of the device:

[0195] (z) Metal contacts 1028 (in this example an aluminum-copper alloy) are formed over the device and extend into the etched recesses.

[0196] It should be understood that Fig.10 The steps shown in Figure 7 , Figure 8 and Fig. 9 The steps shown in can be performed additionally or simultaneously to simultaneously form the terminals of the active area and edge termination area of ​​the MOSFET device using the same process.

[0197] Fig. 9 and Fig.10 The edge termination area manufacturing process shown in Figure 7 and Figure 8 This allows the edge termination structure to be fabricated simultaneously with the active area fabricated using the method disclosed herein to allow electrical contact Figure 6 The gate electrode shown in Figure 6 The resulting device is a split-gate RESURF MOSFET.

[0198] In the manufacturing process shown, the contacts of the active cells are self-aligned, while the contacts of the gate electrodes and the source electrodes are step-aligned. Figure 7 (v) and / or Figure 7 A further CMP step or etching process shown in (w) may also remove the TEOS layer 920, 1024 in the edge termination region. In some embodiments, a multi-stage process with photolithography steps is performed: (i) using a first mask to protect the TEOS layer 920, 1024 in the edge termination region; and (ii) using a second mask to form edge termination contacts to the gate and source terminals, such as Fig. 9 (b) and Fig.10 as shown in (v).

[0199] Those skilled in the art will appreciate that in the foregoing description and the appended claims, positional terms such as "above," "overlapping," "below," "lateral," and the like are made with reference to conceptual illustrations of the device, such as those showing standard cross-sectional perspective views and those shown in the accompanying drawings. These terms are used for ease of reference and are not meant to be limiting. Therefore, these terms should be understood to refer to the device in the orientation shown in the drawings.

[0200] It should be understood that all of the above-described doping polarities may be reversed and the resulting device still conform to embodiments of the present invention.

[0201] In this document, dimensions are provided as indicative examples only and are not limiting.

[0202] Although specific embodiments have been described above, the claims are not limited to these embodiments. In view of this disclosure, those skilled in the art will be able to make modifications and substitutions, which are considered to fall within the scope of the appended claims.

[0203] Each feature disclosed may be incorporated into any described embodiment alone or in any appropriate combination with other features disclosed herein.

[0204] Reference Number

[0205] 100 active area 220 gate trench

[0206] 105n drift region 225 table region

[0207] 110p body region 230 source polysilicon 115n+ contact area 235 insulation layer

[0208] 120 gate trench 240 gate conductive area 125 mesa area 255 gate contact 130 Source polysilicon 260 Insulation layer

[0209] 135 Insulation layer 300 Edge termination area 140 gate conductive region 305n drift region

[0210] 145p+contact area 310p body area

[0211] 155 source contact 320 auxiliary trench

[0212] 160 Insulation spacer 325 Table area

[0213] 165 Oxide plug region 330 Source polysilicon 170 Nitride plug region 335 Insulation layer

[0214] 200 edge termination area 345p+ contact area

[0215] 205n drift region 355 source contact 210p body region 360 insulation layer.

Claims

1. A semiconductor power device having an active region, the active region of the device comprising: a drift region of a first conductivity type; A body region of a second conductivity type disposed above the drift region, wherein the second conductivity type is opposite to the first conductivity type; at least two split gate trench regions, which are in contact with the body region and the drift region, wherein two laterally adjacent split gate trench regions are separated by a mesa region; two or more contact regions of a first conductivity type located in the mesa region and disposed above the body region, wherein the contact regions of the first conductivity type have a higher doping concentration than the doping concentration of the drift region, and wherein the contact regions are in contact with the two adjacent split-gate trench regions such that, in use, a channel is formed along one side of each split-gate trench region and within the body region; a contact region of a second conductivity type located in the mesa region and disposed above the body region, wherein the contact region of the second conductivity type has a higher doping concentration than a doping concentration of the body region, and wherein the contact region of the second conductivity type contacts the two or more contact regions of the first conductivity type within the mesa region; at least two insulating spacer regions overlying and aligned with the two or more contact regions of the first conductivity type; A source contact extends from an upper surface of the device within the mesa region and between the at least two insulating spacer regions, wherein the source contact contacts the two or more contact regions of the first conductivity type and the contact region of the second conductivity type. 2 . The semiconductor power device of claim 1 , wherein the semiconductor device further comprises at least two insulating plug regions located above the separation gate trench region and adjacent to a dielectric spacer region.

3. The semiconductor power device according to claim 2, wherein the insulating plug region is formed of the same material as the insulating spacer region; and optionally Wherein the insulating plug region and the insulating spacer region include oxide.

4. The semiconductor power device according to claim 2, wherein the insulating plug region is formed of a different material than the insulating spacer region; and optionally wherein the insulating plug region comprises nitride, and wherein the insulating spacer region comprises oxide.

5. The semiconductor power device according to any one of claims 2 to 4, wherein the semiconductor power device is formed by the following method: forming the at least two separation gate trench regions in the semiconductor region, wherein two separation gate trench regions adjacent in the lateral direction are separated by a mesa region; etching a gate conductive region in an upper region of each separation gate trench region; forming the at least two insulating plug regions on the etched gate conductive region, each insulating plug region being formed in a separation gate trench region; as well as The semiconductor region is etched within the mesa region between two adjacent separation gate trench regions.

6. The semiconductor power device of any preceding claim, wherein the semiconductor power device is formed by etching a recess in the body region of the second conductivity type in the mesa region, wherein the etched recess is defined by the insulating spacer region.

7. The semiconductor power device according to claim 6, wherein the contact region of the second conductivity type is formed by implanting a dopant of the second conductivity type into the body region of the second conductivity type located below the etched groove; and / or The source contact is formed by depositing a conductive material in the etched groove.

8. A semiconductor device according to any preceding claim, wherein the split gate trench regions each comprise: a gate conductive region formed in an upper portion of each separation gate trench region; a source conductive region formed in a lower portion of each separation gate trench region; as well as An insulating layer is formed along the sidewalls and the lower surface of each separation gate trench region and between the gate conductive region and the source conductive region.

9. The semiconductor power device of any preceding claim, further comprising an edge termination region, wherein the edge termination region is laterally located between the active region and a side surface of the semiconductor device. 10 . The semiconductor power device of claim 9 , wherein the edge termination region comprises a gate terminal having one or more split gate trench regions. 11 . The semiconductor power device of claim 9 , wherein the edge termination region comprises a source terminal having one or more source trench regions.

12. A semiconductor power device as claimed in any preceding claim, wherein the semiconductor device comprises a metal oxide semiconductor field effect transistor (MOSFET).

13. A method for manufacturing an active region of a semiconductor power device, the method comprising: forming at least two separation gate trench regions in the semiconductor region, wherein two separation gate trench regions adjacent in a laterally direction are separated by a mesa region; etching a gate conductive region in an upper region of each separation gate trench region; forming at least two insulating plug regions on the etched gate conductive region, each insulating plug region being formed in a separation gate trench region; as well as The semiconductor region is etched within the mesa region between two adjacent separation gate trench regions.

14. The method for manufacturing an active region of a semiconductor power device according to claim 13, wherein forming at least two insulating plug regions above the etched gate conductive region in the separation gate trench region comprises: forming an insulating region over the entire surface of the active region; And planarizing the insulating region to form the insulating plug region.

15. The method for manufacturing an active region of a semiconductor power device according to claim 13 or 14, wherein etching the gate conductive region comprises: The gate conductive region is etched so that an upper surface of the gate conductive region is substantially lower than an upper surface of the semiconductor region.

16. The method for manufacturing an active region of a semiconductor power device according to claim 13, 14 or 15, wherein etching the semiconductor region comprises: The semiconductor region is etched in the mesa region between two adjacent separation gate trench regions so that an upper surface of the mesa region is substantially lower than an upper surface of the insulating plug region.

17. The method for manufacturing an active region of a semiconductor power device according to any one of claims 13 to 16, further comprising forming at least two insulating spacer regions over the etched mesa region of the semiconductor region and adjacent to the insulating plug region; A recess is etched in the mesa region of the semiconductor region, wherein the recess is defined by the insulating spacer region.

18. The method of manufacturing an active region of a semiconductor power device according to claim 17, wherein forming at least two insulating spacer regions comprises: forming an insulating layer over the at least two insulating plug regions and the mesa region between the at least two separation gate trench regions; as well as The insulating layer is etched using an etching process that terminates on an upper surface of the semiconductor region within the mesa region.

19. The method for manufacturing an active region of a semiconductor power device according to claim 17 or 18, wherein the method further comprises: implanting a dopant of a second conductivity type into the semiconductor substrate below the etched recess; and / or A conductive material is deposited in the etched recess to form a source contact.

20. A method of manufacturing a semiconductor power device, comprising: An active region of a semiconductor power device manufactured according to any one of claims 13 to 19; as well as The edge termination area is fabricated simultaneously.

21. The method for manufacturing a semiconductor power device according to claim 20, wherein the edge termination region comprises a gate terminal having one or more separation gate trench regions and / or wherein the edge termination region comprises a source terminal having one or more source trench regions; and The separation gate trench region of the gate terminal and / or the source trench region of the source terminal are / is formed in the same process as the separation gate trench region of the active area.

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