Ring gate bipolar transistor and manufacturing method thereof

Abstract

The invention relates to a gate-all-around bipolar transistor and a manufacturing method thereof, and the method comprises the steps: a substrate which comprises a first well region and a second well region which are adjacent to each other in a first direction, the second well region is provided with a first conductive type, and the first well region is provided with a second conductive type; the first surrounding gate transistor is formed on the first well region; the second surrounding gate transistor is formed on the first well region, and the second surrounding gate transistor is closer to the second well region along the first direction relative to the first surrounding gate transistor; the third surrounding gate transistor is formed on the second well region; a first PN junction is formed between the source electrode or the drain electrode of the first surrounding gate transistor and the first well region, and a second PN junction is formed between the first well region and the second well region, so that a first bipolar junction transistor is formed. According to the ring gate bipolar transistor in the scheme, the bipolar junction transistor is formed through the well region and the source and drain electrodes of the transistor, waste of the device area can be reduced, and the performance of an integrated circuit is improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a gate-all-around bipolar transistor and a method for manufacturing the same. Background Art

[0002] Currently, the bipolar junction transistor (BJT) is a three-terminal semiconductor device consisting of two PN junctions that can amplify or amplify signals. BJT is a transistor that uses electrons and holes as charge carriers and is often used as a current control device.

[0003] In related technologies, with the development of semiconductor manufacturing processes, device structures are becoming more and more diverse, and the requirements for leads are becoming more and more abundant. However, the overall integrated circuit layout of BJTs is mostly arranged according to a general design, which to a certain extent limits the placement and layout design options of BJTs, affects the performance of the device and causes waste of layout area. Summary of the invention

[0004] The present application is proposed to solve the above problems. According to one aspect of the present application, a gate-all-around bipolar transistor is provided, comprising: a substrate, the substrate comprising a first well region and a second well region adjacently arranged along a first direction, the second well region having a first conductivity type, and the first well region having a second conductivity type; a first surround-gate transistor, the first surround-gate transistor being formed on the first well region; a second surround-gate transistor, the second surround-gate transistor being formed on the first well region, the second surround-gate transistor being closer to the second well region along the first direction relative to the first surround-gate transistor; wherein the source and / or drain of the first surround-gate transistor and the second surround-gate transistor have the same conductivity type as the second well region; a third surround-gate transistor, the third surround-gate transistor being formed on the second well region, the source and / or drain of the third surround-gate transistor having the same conductivity type as the first well region; a first PN junction is formed between the source and / or drain of the first surround-gate transistor and the first well region, and a second PN junction is formed between the first well region and the second well region, so as to form a first bipolar junction transistor.

[0005] Exemplarily, a plurality of the first surround-gate transistors and a plurality of the second surround-gate transistors are formed on the first well region, and a plurality of the third surround-gate transistors are formed on the second well region, wherein the number of the third surround-gate transistors is less than the number of the first surround-gate transistors and greater than the number of the second surround-gate transistors.

[0006] Exemplarily, the number of the first surround-gate transistors is greater than twice the number of the second surround-gate transistors.

[0007] Exemplarily, the first surround gate transistor, the second surround gate transistor and the third surround gate transistor each include a gate electrode and a nanostructure, the nanostructure extends along the first direction, the gate electrode extends along a second direction intersecting the first direction and wraps the nanostructure.

[0008] Exemplarily, a first dielectric gate is formed between the first surround-gate transistor and the second surround-gate transistor, and the first dielectric gate is located on the surface of the first well region; a second dielectric gate is formed between the second surround-gate transistor and the third surround-gate transistor, and the second dielectric gate is located at the junction of the first well region and the second well region.

[0009] Exemplarily, it also includes an interconnection member, which includes: a first interconnection member, a second interconnection member and a third interconnection member; the first interconnection member is respectively connected to the source and the drain of the first surround-gate transistor, the second interconnection member is respectively connected to the source and the drain of the second surround-gate transistor, and the third interconnection member is respectively connected to the source and the drain of the third surround-gate transistor.

[0010] Exemplarily, a dielectric layer is also included, and the dielectric layer is formed on the back side of the substrate.

[0011] Exemplarily, it also includes a first connecting component and a second connecting component, wherein the first connecting component is partially located in the first well region and partially located in the dielectric layer, the first end of the first connecting component is connected to the source and / or drain of the first surround-gate transistor, and the second end of the first connecting component is exposed from the dielectric layer; the second connecting component is partially located in the second well region and partially located in the dielectric layer, the first end of the second connecting component is connected to the source and / or drain of the third surround-gate transistor, and the second end of the second connecting component is exposed from the dielectric layer.

[0012] According to another aspect of the present application, an SOI substrate is provided, the SOI substrate comprising a substrate, a dielectric layer, and a device layer arranged in sequence; a first well region and a second well region adjacent to each other along a first direction are formed in the device layer, the second well region has a first conductivity type, and the first well region has a second conductivity type; a first surround-gate transistor and a second surround-gate transistor spaced apart from each other are formed on the first well region, the second surround-gate transistor being closer to the second well region along the first direction relative to the first surround-gate transistor; wherein the source and / or drain of the first surround-gate transistor and the second surround-gate transistor have the same conductivity type as that of the second well region; a third surround-gate transistor is formed on the second well region, the source and / or drain of the third surround-gate transistor having the same conductivity type as that of the first well region, wherein a first PN junction is formed between the source or drain of the first surround-gate transistor and the first well region, and a second PN junction is formed between the first well region and the second well region to form a first bipolar junction transistor; and the substrate is removed.

[0013] Exemplarily, the method also includes forming a first connecting component and a second connecting component, wherein the first connecting component is partially located in the first well region and partially located in the dielectric layer, a first end of the first connecting component is connected to the source and / or drain of the first surround-gate transistor, and a second end of the first connecting component is exposed from the dielectric layer; the second connecting component is partially located in the second well region and partially located in the dielectric layer, a first end of the second connecting component is connected to the source and / or drain of the third surround-gate transistor, and a second end of the second connecting component is exposed from the dielectric layer.

[0014] The all-around gate bipolar transistor in the present application forms different transistors on the first well region and the second well region, the first well region and the second well region have different conductivity types, a first PN junction is formed by the source or drain of the first all-around gate transistor and the first well region, and a second PN junction is formed by the first well region and the second well region. In the solution of the present application, when forming the all-around gate transistor, a bipolar junction transistor is formed by the well region and the source and drain of the transistor, which can reduce the waste of device area and improve the performance of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] By describing the embodiments of the present application in more detail in conjunction with the accompanying drawings, the above and other purposes, features and advantages of the present application will become more apparent. The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0016] Figure 1A top schematic diagram of a gate-all-around bipolar transistor in an embodiment of the present application is shown.

[0017] Figure 2 A first cross-sectional schematic diagram of a gate-all-around bipolar transistor in an embodiment of the present application is shown.

[0018] Figure 3 A second cross-sectional schematic diagram of the gate-all-around bipolar transistor in an embodiment of the present application is shown.

[0019] Figure 4 A flow chart of a method for manufacturing a gate-all-around bipolar transistor in an embodiment of the present application is shown.

[0020] Figure numerals: 100, first well region; 101, first active region; 110, first surround-gate transistor; 111, first gate electrode; 112, first nanostructure; 120, second surround-gate transistor; 121, second gate electrode; 122, second nanostructure; 130, first interconnection member; 140, second interconnection member; 150, first dielectric base gate; 160, second dielectric base gate; 170, first connection member; 171, first internal member; 172, first external member; 200, second well region; 201, second active region; 210, third surround-gate transistor; 220, third interconnection member; 211, third gate electrode; 212, third nanostructure; 230, second connection member; 231, second internal member; 232, second external member; 300, dielectric layer; 400, interlayer dielectric layer. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the present application more obvious, the example embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the example embodiments described herein. Based on the embodiments of the present application described in the present application, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present application.

[0022] like Figure 1 As shown, an embodiment of the present application provides a gate-all-around bipolar transistor, including: a substrate, a first gate-all-around transistor 110 , a second gate-all-around transistor 120 , and a third gate-all-around transistor 210 .

[0023] The substrate includes a first well region 100 and a second well region 200 adjacently arranged along a first direction (X direction in the figure), the second well region 200 has a first conductivity type, and the first well region 100 has a second conductivity type. A first all-around gate transistor 110 is formed on the first well region 100; The second wrap-around gate transistor 120 is formed on the first well region 100, wherein the source and / or drain of the first wrap-around gate transistor 110 and the second wrap-around gate transistor 120 have the same conductivity type as the second well region 200; the third wrap-around gate transistor 210 is formed on the second well region 200, and the source and / or drain of the third wrap-around gate transistor 210 has the same conductivity type as the first well region 100. The second wrap-around gate transistor 120 is closer to the second well region 200 along the first direction than the first wrap-around gate transistor 110.

[0024] A first PN junction is formed between the source or drain of the first surround-gate transistor 110 and the first well region 100 , and a second PN junction is formed between the first well region 100 and the second well region 200 to form a first bipolar junction transistor.

[0025] The all-around gate bipolar transistor in the present application forms different transistors on the first well region and the second well region, the first well region and the second well region have different conductivity types, a first PN junction is formed by the source or drain of the first all-around gate transistor and the first well region, a second PN junction is formed by the first well region and the second well region, and a bipolar junction transistor is formed based on the first PN junction and the second PN junction. In the solution of the present application, when forming the all-around gate transistor, a bipolar junction transistor is formed by the well region and the source and drain of the transistor, which can reduce the waste of device area and improve the performance of the integrated circuit.

[0026] Exemplarily, the substrate may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors. In one example, the substrate of the present application may also be composed of a device layer of an SOI substrate. A first well region 100 and a second well region 200 are formed in the substrate adjacent to each other along a first direction. The first well region 100 and the second well region 200 may be formed in the substrate by, for example, ion implantation.

[0027] Exemplarily, the first conductivity type of the first well region 100 in the embodiment of the present application is N-type, and the second conductivity type of the second well region 200 is P-type. In some embodiments, the conductivity type of the first well region 100 may also be P-type, and the conductivity type of the second well region 200 is N-type, and the conductivity types of the two are opposite. Figure 1 The N-Well and P-Well in the figure represent an N-type well region and a P-type well region, respectively. Figure 1Mos1, Mos2, and Mos3 in it respectively represent the first surround-gate transistor 110, the second surround-gate transistor 120, and the third surround-gate transistor 210. It can be seen from the figure that the number of each type of transistor is multiple, and the number of the third surround-gate transistor 210 is less than that of the first surround-gate transistor 110 and greater than that of the second surround-gate transistor 120. Exemplarily, P-Well is boron-doped silicon (SiB), and N-Well is phosphorus-doped silicon (SiP).

[0028] Mos1-Mos3 are all arranged along the first direction, and the first direction is Figure 1 the X direction in it, and the second direction is Figure 1 the Y direction in it. And the first well region 100 and the second well region 200 have the same width H1 in the Y direction. As Figure 1 shown, the first well region 100 includes two parts. The first part and the second part are respectively used to form the first surround-gate transistor 110 and the second surround-gate transistor 120. The part used to form the second surround-gate transistor 120 is located on both sides of the first part. The two parts of the first well region 100 are respectively represented by W1 and W2, where the width of W1 is greater than the width of W2 (the width in the X direction). The second well region 200 is formed on both sides of the first well region 100, and the width of the second well region 200 is represented by W3, where W2 < W3 < W1. In some embodiments, W1 > 2W2 or W1 > 2W3.

[0029] Figure 2 is Figure 1 a cross-sectional schematic diagram along the AA* direction. As Figure 1-Figure 2 shown, a first active region 101 and a second active region 201 are respectively formed on the first well region 100 and the second well region 200. The first active region 101 and the second active region 201 both extend along the X direction, and the first active region 101 and the second active region 201 are spaced apart in the second direction. Among them, the first active region 101 and the second active region 201 include the source, drain, and channel regions of each surround-gate transistor.

[0030] In some examples, the gate electrodes of each surround-gate transistor span the first active region 101 and the second active region 201 along the first direction.

[0031] Exemplarily, the first surround gate transistor 110, the second surround gate transistor 120 and the third surround gate transistor 210 all include a gate electrode and a nanostructure, at least part of the nanostructure constitutes the channel region in the first active region 101 and / or the second active region 201, the gate electrode is located on the surface of the substrate; the gate electrode extends along the second direction (Y direction) and is arranged at intervals along the first direction, wherein the second direction intersects the first direction, and further, the first direction and the second direction are perpendicular to each other. The channel region in the nanostructure is also the region where the nanostructure is wrapped by the gate electrode.

[0032] The first surround gate transistor 110 includes a first gate electrode 111 and a first nanostructure 112, wherein the first gate electrode 111 is located on the surface of the first well region 100 and extends along the Y direction, and the first nanostructure 112 is located in the first active region 101 and extends along the X direction. In some embodiments, the first nanostructure 112 is a nanosheet or a channel layer, which is composed of semiconductor materials such as silicon, germanium, silicon carbide, silicon phosphide or gallium arsenide. The first nanostructure 112 can be a stacked structure, for example, multiple nanosheets or channel layers or nanowires are stacked along the Z direction and have intervals between each other, wherein the Z direction is perpendicular to the X direction and the Y direction. Exemplarily, a gate dielectric layer (not shown in the figure) is also wrapped outside the first nanostructure 112. Exemplarily, the first gate electrode 111 can be polysilicon or a metal gate, and the metal gate can include a work function metal (such as TiN) and a metal layer. The source and drain of the first surround-gate transistor 110 are located on both sides of the first nanostructure 112. The distribution of the source, drain and gate shown in the figure is exemplary, and the positional relationship between the source and drain on opposite sides of the gate can be selected and set according to actual conditions.

[0033] Exemplarily, the all-around gate bipolar transistor further includes an interconnection member, specifically including a first interconnection member 130, a second interconnection member 140, and a third interconnection member 220. The first interconnection member 130 connects the source and drain of the first all-around gate transistor 110. Exemplarily, the first interconnection member 130 is a conductive material such as a metal wire (such as tungsten). The source and drain of the first all-around gate transistor 110 are connected together through the first interconnection member 130. In some embodiments, the source and drain of the first all-around gate transistor 110 are also connected to the gate of the first all-around gate transistor 110.

[0034] The second surround gate transistor 120 includes a second gate electrode 121 and a second nanostructure 122, the second gate electrode 121 is located on the surface of the first well region 100 and extends along the Y direction, and the second nanostructure 122 is located in the first active region 101 and extends along the X direction. In some embodiments, the second nanostructure 122 is a nanosheet or a channel layer, which is composed of semiconductor materials such as silicon, germanium, silicon carbide, silicon phosphide or gallium arsenide. The second nanostructure 122 can be a stacked structure, such as a multi-layer nanosheet or channel layer or nanowire stacked along the Z direction and spaced apart from each other. Exemplarily, a gate dielectric layer (not shown in the figure) is also wrapped around the outside of the second nanostructure 122. Exemplarily, the second gate electrode 121 can be polysilicon or a metal gate, and the metal gate includes a work function metal (such as TiN) and a metal layer. The source and drain of the second surround gate transistor 120 are located on both sides of the second nanostructure 122.

[0035] Exemplarily, the second interconnection member 140 connects the source and the drain of the second surround-gate transistor 120. Exemplarily, the second interconnection member 140 is a conductive material such as a metal wire (such as tungsten). The source and the drain of the second surround-gate transistor 120 are connected together through the second interconnection member 140. In some embodiments, the source and the drain of the second surround-gate transistor 120 are also connected to the gate of the second surround-gate transistor 120.

[0036] Please continue to refer to Figure 1-Figure 2 The third surround gate transistor 210 includes a third gate electrode 211 and a third nanostructure 212. The third gate electrode 211 is located on the surface of the second well region 200 and extends along the Y direction. The third nanostructure 212 is located in the second active region 201 and extends along the X direction. In some embodiments, the third nanostructure 212 is a nanosheet or a channel layer, which is composed of semiconductor materials such as silicon, germanium, silicon carbide, silicon phosphide or gallium arsenide. The third nanostructure 212 can be a stacked structure, for example, multiple nanosheets or channel layers or nanowires are stacked along the Z direction and have intervals between them. Exemplarily, a gate dielectric layer (not shown in the figure) is also wrapped outside the third nanostructure 212. Exemplarily, the third gate electrode 211 can be polysilicon or a metal gate, and the metal gate includes a work function metal (such as TiN) and a metal layer. The source and drain of the third surround gate transistor 210 are located on the left and right sides of the third nanostructure 212.

[0037] Exemplarily, the third interconnection member 220 connects the source and drain of the third surround-gate transistor 210. Exemplarily, the third interconnection member 220 is a conductive material such as a metal wire (such as tungsten). The source and drain of the third surround-gate transistor 210 are connected together through the third interconnection member 220. In some embodiments, the source and drain of the third surround-gate transistor 210 are also connected to the gate of the third surround-gate transistor 210.

[0038] It should be noted that the connection relationship between the gate, source and drain in the embodiment of the present application is exemplary. In some embodiments, the gate of the first surround-gate transistor 110 can also be connected to the source and drain of the second surround-gate transistor 120 through an interconnection component (or through other connection structures).

[0039] Exemplarily, the semiconductor component further includes a dielectric layer 300 and an interlayer dielectric layer 400, and the dielectric layer 300 and the interlayer dielectric layer 400 provide functions such as insulation and protection. Exemplarily, the dielectric layer 300 and the interlayer dielectric layer 400 are oxides. In some embodiments, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide are used as the material of the dielectric layer. The dielectric layer 300 is located on the first surface (back side) of the substrate, and the interlayer dielectric layer 400 is located on the second surface (front side) of the substrate. The first gate electrode 111, the second gate electrode 121 and the third gate electrode 211 are all located in the interlayer dielectric layer 400, wherein the interlayer dielectric layer 400 covers the first surround gate transistor 110, the second surround gate transistor 120 and the third surround gate transistor 210, that is, covers the first gate electrode 111, the second gate electrode 121 and the third gate electrode 211 and fills the gap between adjacent gate electrodes. Exemplarily, the first interconnection member 130, the second interconnection member 140 and the third interconnection member 220 are also located in the interlayer dielectric layer 400. More specifically, the first interconnection member 130, the second interconnection member 140 and the third interconnection member 220 penetrate the interlayer dielectric layer 400. In some embodiments, the surfaces of the dielectric layer 300 and the interlayer dielectric layer 400 are formed into smooth surfaces through a planarization process such as chemical mechanical polishing (CMP) and / or etching.

[0040] Exemplarily, a first dielectric gate 150 is formed between the first wrap-around gate transistor 110 and the second wrap-around gate transistor 120, and the first dielectric gate 150 extends downward from the interlayer dielectric layer 400 through the first active area 101 and the second active area 201 to the surface of the substrate. The first dielectric gate 150 is used to separate the first wrap-around gate transistor 110 and the second wrap-around gate transistor 120. A second dielectric gate 160 is formed between the second wrap-around gate transistor 120 and the third wrap-around gate transistor 210. The second dielectric gate 160 extends downward from the interlayer dielectric layer 400 through the first active area 101 and the second active area 201 to the surface of the substrate. Exemplarily, a first portion of the second dielectric gate 160 is located at the junction of the first well area 100 and the second well area 200, and another portion is located on the surface of the substrate and in the interlayer dielectric layer 400. The second dielectric gate 160 is used to separate the second wrap-around gate transistor 120 and the third wrap-around gate transistor 210.

[0041] like Figure 2-Figure 3 As shown, Figure 3 for Figure 1 Schematic diagram of another perspective of the cross section along the AA* direction. Exemplarily, the ring-gate bipolar transistor also includes a first connecting component 170 and a second connecting component 230 for connecting to an external circuit. Specifically, a portion of the first connecting component 170 is located in the first well region 100, and another portion extends to the surface of the dielectric layer 300, and a portion of the second connecting component 230 is located in the second well region 200, and another portion extends to the surface of the dielectric layer 300. The first bipolar junction transistor (BJT-A in the figure) is connected to an external circuit through the first connecting component 170 and the second connecting component 230. In the present application, the first connecting component 170 and the second connecting component 230 can be connected to the external circuit on the back side of the device, which can reduce the wiring area on the one hand, and reduce the back-end capacitance on the other hand, thereby improving the performance of the integrated circuit.

[0042] Exemplarily, for the first bipolar junction transistor, it is connected to the external circuit through the first connection component 170 and the second connection component 230. Specifically, the emitter region of the bipolar junction transistor is connected to the external circuit through the first connection component 170. The two parts of the first connection component 170 are respectively a first inner component 171 and a first outer component 172. The first inner component 171 is located in the first well region 100 and connected to the source and / or drain of the first surround gate transistor 110 (that is, the emitter of the first bipolar junction transistor). The first inner component 171 is connected to the first outer component 172. The first outer component 172 is located in the dielectric layer 300 and exposed from the dielectric layer 300, so as to be connected to the external circuit through an electrical conductor or the like. The second connection part 230 includes a second inner part 231 and a second outer part 232. The second inner part 231 is located in the second well region 200 and is used to connect the source and / or drain of the third surround gate transistor 210. The second outer part 232 is located in the dielectric layer 300 and extends to the surface of the dielectric layer 300 at its edge to connect to an external circuit. The first inner part 171 and the second inner part 231 may be a through silicon via (TSV) structure. In some embodiments, the first inner part 171 and the second inner part 231 may be a conductive through hole or a plug connection structure. In some examples, in order to avoid the first inner part 171 and the second inner part 231 from being electrically connected to the well region where they are located, an insulating isolation layer is also provided on the sidewalls of the first inner part 171 and the second inner part 231. The insulating isolation layer may be made of any suitable insulating material, such as silicon nitride, silicon oxide, silicon oxynitride, or a combination of multiple materials. The first external component 172 and the second external component 232 may be conductive via structures (Via) and / or metal wiring layers formed in the dielectric layer 300. The specific formation methods of the above-mentioned through silicon vias, plug connection structures and via structures are conventional technologies in the art and will not be further described in this application.

[0043] Exemplarily, as described above, the second well region 200 and the third surround gate transistor 210 in the embodiment of the present application are arranged on both sides of the first well region 100. Therefore, in addition to forming the first bipolar junction transistor, there is also a second bipolar junction transistor (BJT-B in the figure). Among them, the first bipolar junction transistor and the second bipolar junction transistor are symmetrically arranged. Exemplarily, the third PN junction of the second bipolar junction transistor is formed between the source or drain of the first surround gate transistor 110 and the first well region 100, the second PN junction of the first bipolar junction transistor is formed between the first well region 100 and the second well region 200 located on one side of the first well region 100, and the fourth PN junction of the second bipolar junction transistor is formed between the first well region 100 and the second well region 200 on the other side. The first bipolar junction transistor and the second bipolar junction transistor are PNP transistors. In some embodiments, the first bipolar junction transistor and the second bipolar junction transistor may also be NPN transistors. Figure 3 The lines in the left and right parts are wireframe schematic diagrams of the first and second bipolar junction transistors. It should be noted that the structures of the first connecting component 170 and the second connecting component 230 in the above content are described as examples. The purpose of the first connecting component 170 and the second connecting component 230 is to connect to an external circuit, and the number of them is not used to limit the structure of the ring-gate bipolar transistor.

[0044] In some embodiments, when the all-around gate bipolar transistor has a first connecting component 170 and a second connecting component 230, an interconnection component located on the front side of the device may not be provided, or an interconnection component may be partially provided and a connecting component may be partially provided, for example, the source and drain of a portion of the all-around gate transistor are led out through the interconnection component located on the front side of the device, while the source and drain of another portion of the all-around gate transistor are led out through the connecting component located on the back side of the device.

[0045] The ring-gate bipolar transistor in the present application forms different transistors on the first well region 100 and the second well region 200. The first well region 100 and the second well region 200 have different conductivity types. The first PN junction is formed by the source or drain of the first surround-gate transistor 110 and the first well region 100, and the second PN junction is formed by the first well region 100 and the second well region 200. The surround-gate transistor in the present application has the characteristics of good power performance and area scaling, which can improve the performance of the integrated circuit and reduce the area of ​​the device. In addition, after forming the PN junction, the ring-gate bipolar transistor can be connected to the external circuit through the back side, reducing the back-end capacitance to improve performance, and at the same time can reduce the waste of device area.

[0046] like Figure 4 As shown, the embodiment of the present application also provides a method for manufacturing a gate-all-around bipolar transistor, which is used to prepare the above-mentioned gate-all-around bipolar transistor, and the method includes the following steps: S410, providing an SOI substrate, wherein the SOI substrate includes a base, a dielectric layer, and a device layer arranged in sequence.

[0047] S420, forming a first well region and a second well region adjacent to each other along a first direction in the device layer, wherein the second well region has a first conductivity type and the first well region has a second conductivity type. In this step, the first well region and the second well region can be formed by respectively performing ion implantation on regions in the device layer that are intended to be used as the first well region and the second well region.

[0048] S430, forming a first surround-gate transistor and a second surround-gate transistor spaced apart from each other on the first well region, the second surround-gate transistor being closer to the second well region along the first direction than the first surround-gate transistor; wherein the source and / or drain of the first surround-gate transistor and the second surround-gate transistor have the same conductivity type as the second well region.

[0049] S440. Form a third surround-gate transistor on the second well region, wherein the source and / or drain of the third surround-gate transistor has the same conductivity type as that of the first well region, wherein a first PN junction is formed between the source or drain of the first surround-gate transistor and the first well region, and a second PN junction is formed between the first well region and the second well region to form a first bipolar junction transistor.

[0050] S450, removing the substrate. By removing the substrate, the dielectric layer can be exposed, and the thickness of the back side of the device can be reduced, which is conducive to making subsequent connection components on the back side of the device. It is worth mentioning that the specific manufacturing method of each surround gate transistor can adopt any suitable method, which is not specifically limited here.

[0051] After the base is removed from the SOI substrate, the dielectric layer and the device layer are retained, and the device layer is used as the substrate of the ring-gate bipolar transistor mentioned above.

[0052] Exemplarily, the method further includes: forming a first connection component and a second connection component. The first connection component is partially located in the first well region and partially located in the dielectric layer, a first end of the first connection component is connected to the source and / or drain of the first surround-gate transistor, and a second end of the first connection component is exposed from the dielectric layer; the second connection component is partially located in the second well region and partially located in the dielectric layer, a first end of the second connection component is connected to the source and / or drain of the third surround-gate transistor, and a second end of the second connection component is exposed from the dielectric layer.

[0053] In some examples, internal components of each connecting component may be formed at a predetermined position in advance, and then each surround gate transistor may be prepared. Thereafter, after removing the substrate, external components connected to each internal component may be formed in the dielectric layer.

[0054] The gate-all-around bipolar transistor in the present application forms different transistors on the first well region 100 and the second well region 200. The first well region 100 and the second well region 200 have different conductivity types. A first PN junction is formed by the source or drain of the first surround-gate transistor 110 and the first well region 100, and a second PN junction is formed by the first well region 100 and the second well region 200. After forming the PN junction, the gate-all-around bipolar transistor in the present application can be connected to an external circuit through the back side, reducing the back-end capacitance to improve performance, and at the same time can reduce the waste of device area.

[0055] It is worth mentioning that some details of the manufacturing method of this embodiment can also be referred to the relevant description of the ring-gate bipolar transistor in the previous text, which will not be repeated here.

[0056] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application to this. Those of ordinary skill in the art may make various changes and modifications therein without departing from the scope and spirit of the present application. All these changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0057] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0058] Similarly, it should be understood that in order to streamline the present application and help understand one or more of the various inventive aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present application should not be interpreted as reflecting the following intention: the claimed application requires more features than the features clearly stated in each claim. More specifically, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with features less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby explicitly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present application.

[0059] Those skilled in the art will understand that, except for mutually exclusive features, all features disclosed in this specification (including the accompanying claims, abstract and drawings) and all processes or units of any method or device disclosed in this specification may be combined in any combination. Unless otherwise explicitly stated, each feature disclosed in this specification (including the accompanying claims, abstract and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0060] In addition, those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims, any one of the claimed embodiments may be used in any combination.

[0061] The above is only a specific implementation or description of a specific implementation of the present application, and the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A gate-all-around bipolar transistor, characterized in that: include: A substrate, the substrate comprising a first well region and a second well region adjacently arranged along a first direction, the second well region having a first conductivity type, and the first well region having a second conductivity type; a first surround-gate transistor, wherein the first surround-gate transistor is formed on the first well region; a second wrap-around gate transistor, the second wrap-around gate transistor being formed on the first well region, the second wrap-around gate transistor being closer to the second well region along the first direction than the first wrap-around gate transistor; wherein the source and / or drain of the first wrap-around gate transistor and the second wrap-around gate transistor have the same conductivity type as the second well region; a third surround-gate transistor, wherein the third surround-gate transistor is formed on the second well region, and a source and / or a drain of the third surround-gate transistor has the same conductivity type as that of the first well region; A first PN junction is formed between the source or drain of the first surround-gate transistor and the first well region, and a second PN junction is formed between the first well region and the second well region to form a first bipolar junction transistor.

2. The gate-all-around bipolar transistor according to claim 1, characterized in that: A plurality of the first surround-gate transistors and a plurality of the second surround-gate transistors are formed on the first well region, and a plurality of the third surround-gate transistors are formed on the second well region. The number of the third surround-gate transistors is less than the number of the first surround-gate transistors and greater than the number of the second surround-gate transistors.

3. The gate-all-around bipolar transistor according to claim 2, characterized in that: The number of the first surround-gate transistors is greater than twice the number of the second surround-gate transistors.

4. The gate-all-around bipolar transistor according to claim 1, characterized in that: The first surround-gate transistor, the second surround-gate transistor and the third surround-gate transistor each include a gate electrode and a nanostructure, the nanostructure extends along the first direction, and the gate electrode extends along a second direction intersecting the first direction and wraps the nanostructure.

5. The gate-all-around bipolar transistor according to claim 4, characterized in that A first dielectric base gate is formed between the first surround gate transistor and the second surround gate transistor, and the first dielectric base gate is located on the surface of the first well region; A second dielectric base gate is formed between the second surround-gate transistor and the third surround-gate transistor, and the second dielectric base gate is located at the junction of the first well region and the second well region.

6. The gate-all-around bipolar transistor according to any one of claims 1 to 5, characterized in that: Also included is an interconnection member, the interconnection member comprising: a first interconnection member, a second interconnection member, and a third interconnection member; The first interconnection member connects the source and drain of the first all-around gate transistor, respectively, the second interconnection member connects the source and drain of the second all-around gate transistor, respectively, and the third interconnection member connects the source and drain of the third all-around gate transistor, respectively.

7. The gate-all-around bipolar transistor according to any one of claims 1 to 5, characterized in that: A dielectric layer is also included, and the dielectric layer is formed on the back side of the substrate.

8. The gate-all-around bipolar transistor according to claim 7, characterized in that: It also includes a first connecting component and a second connecting component, wherein the first connecting component is partially located in the first well region and partially located in the dielectric layer, the first end of the first connecting component is connected to the source and / or drain of the first surround-gate transistor, and the second end of the first connecting component is exposed from the dielectric layer; the second connecting component is partially located in the second well region and partially located in the dielectric layer, the first end of the second connecting component is connected to the source and / or drain of the third surround-gate transistor, and the second end of the second connecting component is exposed from the dielectric layer.

9. A method for manufacturing a gate-all-around bipolar transistor, characterized in that: The method comprises: Providing an SOI substrate, wherein the SOI substrate comprises a base, a dielectric layer, and a device layer arranged in sequence; forming a first well region and a second well region adjacent to each other along a first direction in the device layer, wherein the second well region has a first conductivity type and the first well region has a second conductivity type; forming a first surround-gate transistor and a second surround-gate transistor spaced apart from each other on the first well region, wherein the second surround-gate transistor is closer to the second well region along the first direction than the first surround-gate transistor; wherein the source and / or drain of the first surround-gate transistor and the second surround-gate transistor have the same conductivity type as the second well region; forming a third surround-gate transistor on the second well region, wherein the source and / or drain of the third surround-gate transistor has the same conductivity type as that of the first well region, wherein a first PN junction is formed between the source or drain of the first surround-gate transistor and the first well region, and a second PN junction is formed between the first well region and the second well region, so as to form a first bipolar junction transistor; The substrate is removed.

10. The method according to claim 9, characterized in that The method further comprises: A first connecting component and a second connecting component are formed, wherein the first connecting component is partially located in the first well region and partially located in the dielectric layer, a first end of the first connecting component is connected to the source and / or drain of the first surround-gate transistor, and a second end of the first connecting component is exposed from the dielectric layer; the second connecting component is partially located in the second well region and partially located in the dielectric layer, a first end of the second connecting component is connected to the source and / or drain of the third surround-gate transistor, and a second end of the second connecting component is exposed from the dielectric layer.

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