Semiconductor device

Abstract

A semiconductor device includes: a semiconductor base body having a first main surface and a second main surface, the first main surface and the second main surface being spaced apart in a first direction, the semiconductor base body including an insulated gate bipolar transistor region, the insulated gate bipolar transistor region including a first region, the first region including a first region, and the second region including a second region; a first sub-drift layer and a second sub-drift layer are arranged in the first region, and the first sub-drift layer is closer to the first main surface than the second sub-drift layer in the first direction; the depth direction of the grooves reaches the drift layer, the number of the grooves is multiple, and at least one of the grooves extends into the first sub-drift layer of the first region. Therefore, when the semiconductor device is turned off in the forward direction, the first sub-drift layer and the second sub-drift layer in the first region can form a blocking junction, and the blocking junction can mainly bear an electric field and also can assist in depleting carriers, so that the peak voltage can be reduced, and the reverse voltage resistance and the breakdown voltage resistance can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] In the prior art, in the initial forward conduction stage of a reverse-conducting insulated gate bipolar transistor, there is a positive feedback process in which the current increases continuously and the resistance decreases continuously during the conversion process of the device from a unipolar conduction state to a bipolar conduction state, which is called the voltage foldback phenomenon. The voltage foldback phenomenon slows down the turn-on speed of the reverse-conducting insulated gate bipolar transistor device, and in severe cases, it may cause the reverse-conducting insulated gate bipolar transistor device to be unable to turn on, causing damage to the reliability and performance of the device.

[0003] In the related art, in order to eliminate the voltage foldback phenomenon in the reverse conducting insulated gate bipolar transistor, a common method is to increase the width of the P-type collector region. However, an excessively large P-type collector region will cause uneven current distribution inside the device, thereby reducing the voltage resistance of the device. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a semiconductor device that can improve voltage resistance.

[0005] According to an embodiment of the present invention, a semiconductor device comprises: a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, wherein the first main surface and the second main surface are arranged at intervals in a first direction; a drift layer, wherein the drift layer is arranged on the semiconductor substrate and located between the first main surface and the second main surface, wherein the semiconductor substrate comprises an insulated gate bipolar transistor region and a fast recovery diode region, wherein the insulated gate bipolar transistor region is arranged circumferentially around the outside of the fast recovery diode region; wherein the drift layer comprises a first drift layer and a second drift layer, wherein the second drift layer is of a first conductivity type and is located between the first and second main surfaces. a first main surface of the first main surface and a second main surface of the second main surface; a first sub-drift layer is disposed in the insulated gate bipolar transistor region, wherein the first drift layer is located in the insulated gate bipolar transistor region and includes a first sub-drift layer of a first conductivity type and a second sub-drift layer of a second conductivity type; the insulated gate bipolar transistor region includes a first region and a second region, wherein the first region is adjacent to the fast recovery diode region, and the second region is away from the fast recovery diode region; the first sub-drift layer and the second sub-drift layer are disposed in the first region, and the first sub-drift layer is closer to the first main surface in the first direction than the second sub-drift layer; the first sub-drift layer and the second sub-drift layer are also disposed in the second region, In the second region, the second sub-drift layer is closer to the first main surface in the first direction than the first sub-drift layer; a base layer of the second conductivity type, the base layer is arranged on the side of the drift layer facing the first main surface, and the surface of the base layer on the side away from the drift layer constitutes a part of the first main surface; an emitter metal layer, the emitter metal layer is arranged on the first main surface; a groove, the depth direction of the groove penetrates the base layer from the first main surface and reaches the drift layer, the groove is multiple, the multiple grooves are arranged at intervals in the second direction, and at least one of the multiple grooves extends into the first region In the first sub-drift layer; a collector layer of the second conductivity type and a cathode layer of the first conductivity type, the collector layer is arranged on the side of the first drift layer facing the second main surface, the side of the collector layer away from the drift layer constitutes at least a part of the second main surface, and the collector layer is located in the insulated gate bipolar transistor region; the cathode layer is arranged on the side of the second drift layer facing the second main surface, the side of the cathode layer away from the drift layer constitutes at least a part of the second main surface, and the cathode layer is located in the fast recovery diode region; a collector metal layer, the collector metal layer is arranged on the second main surface.

[0006] Therefore, by arranging a first sub-drift layer of the first conductivity type and a second sub-drift layer of the second conductivity type in the first region of the insulated gate bipolar transistor region, and the first sub-drift layer is closer to the first main surface than the second sub-drift layer, when the semiconductor device is forward turned off, the first sub-drift layer and the second sub-drift layer in the first region can form a blocking junction, and the blocking junction can not only mainly bear the electric field but also assist in depleting carriers, thereby reducing the peak voltage and improving the reverse voltage resistance and breakdown voltage resistance.

[0007] In some examples of the present invention, a boundary between the first sub-drift layer and the second sub-drift layer in the first region and a boundary between the first sub-drift layer and the second sub-drift layer in the second region are flush with each other.

[0008] In some examples of the present invention, the depths of the first sub-drift layer and the second sub-drift layer in the first region in the first direction are equal and are both D1, and the depths of the first sub-drift layer and the second sub-drift layer in the second region in the first direction are equal and are both D2, and D1 and D2 satisfy the relationship: D1=D2.

[0009] In some examples of the present invention, the semiconductor device also includes a first dielectric isolation layer, which is arranged between the insulated gate bipolar transistor region and the fast recovery diode region, and the depth direction of the first dielectric isolation layer extends from the second main surface toward the first main surface. The first dielectric isolation layer passes through between the collector layer and the cathode layer and reaches the drift layer.

[0010] In some examples of the present invention, the first dielectric isolation layer is a silicon dioxide isolation layer.

[0011] In some examples of the present invention, one end of the first dielectric isolation layer facing the first main surface does not extend beyond the second sub-drift layer in the first region and the first sub-drift layer in the second region.

[0012] In some examples of the present invention, the semiconductor device also includes a second dielectric isolation layer, the collector metal layer includes a first collector metal layer and a second collector metal layer, the first collector metal layer is located in the insulated gate bipolar transistor region, the second collector metal layer is arranged in the fast recovery diode region, the first collector metal layer and the second collector metal layer are spaced apart, and the second dielectric isolation layer is arranged between the first collector metal layer and the second collector metal layer and corresponds to the first dielectric isolation layer.

[0013] In some examples of the present invention, the semiconductor device also includes a floating layer of a second conductive type, which is arranged in the second drift layer, and the depth direction of the floating layer extends from a side of the second drift layer adjacent to the second main surface toward the first main surface, and the floating layer is in contact with the cathode layer.

[0014] In some examples of the present invention, there are a plurality of floating layers, and the plurality of floating layers are spaced apart by the drift layer.

[0015] In some examples of the present invention, one end of the first dielectric isolation layer adjacent to the first main surface protrudes beyond one end of the floating layer adjacent to the first main surface.

[0016] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0018] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0019] Figure 2 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0020] Figure 3 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0021] Figure 4 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0022] Figure 5 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0023] Figure 6 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0024] Figure 7 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0025] Figure 8 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0026] Fig. 9 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0027] Fig.10 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0028] Fig.11 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0029] Fig.12 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0030] Fig.13 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0031] Reference numerals:

[0032] 100. Semiconductor devices;

[0033] 1. semiconductor substrate; 101. first main surface; 102. second main surface; 103. insulated gate bipolar transistor region; 1031. first region; 1032. second region; 104. fast recovery diode region;

[0034] 2. drift layer; 201. first drift layer; 2011. first sub-drift layer; 2012. second sub-drift layer; 202. second drift layer;

[0035] 3. Base layer; 4. Emitter metal layer; 5. Groove;

[0036] 601, collector layer; 602, cathode layer;

[0037] 7. Collector metal layer; 701. First collector metal layer; 702. Second collector metal layer;

[0038] 8. First dielectric isolation layer; 9. Second dielectric isolation layer; 10. Floating layer; 11. Gate pad; 12. Emitter region; 13. Contact hole region; 14. Carrier storage layer;

[0039] 15. Gate; 1501. Gate oxide layer;

[0040] 16. Buffer layer. DETAILED DESCRIPTION

[0041] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0042] Reference below Figure 1-Figure 13A semiconductor device 100 according to an embodiment of the present invention is described. The semiconductor device 100 is, for example, a reverse-conducting insulated gate bipolar transistor. In the following description, N and P represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is set to N type and the second conductivity type is set to P type for description. Similarly, the first conductivity type can also be set to P type and the second conductivity type can be set to N type.

[0043] Combination Figure 1 As shown, the semiconductor device 100 according to the present invention may mainly include: a semiconductor substrate 1, a drift layer 2, a base layer 3 of a second conductive type, an emitter metal layer 4, a groove 5, a collector layer 601, a cathode layer 602 and a collector metal layer 7, wherein the semiconductor substrate 1 has a first main surface 101 and a second main surface 102 opposite to the first main surface 101, and the first main surface 101 and the second main surface 102 are spaced apart in a first direction, which can provide a stable and reliable setting position for other structures in the semiconductor device 100.

[0044] In the embodiment of the present invention, the drift layer 2 is arranged on the semiconductor substrate 1 and is located between the first main surface 101 and the second main surface 102, so that a transmission channel can be provided for the current in the semiconductor device 100. The semiconductor device 100 has an insulated gate bipolar transistor region 103 and a fast recovery diode region 104. The insulated gate bipolar transistor region 103 and the fast recovery diode region 104 are reversely connected in parallel in the semiconductor device 100, so that the insulated gate bipolar transistor has a reverse conduction function. The insulated gate bipolar transistor region 103 is circumferentially arranged on the outside of the fast recovery diode region 104, and is spaced from the fast recovery diode region 104. The transition region is located between the fast recovery diode region 104 and the insulated gate bipolar transistor region 103, which can prevent the currents flowing through the insulated gate bipolar transistor region 103 and the fast recovery diode region 104 from affecting each other, thereby ensuring the normal operation of the reverse conducting insulated gate bipolar transistor.

[0045] Further, the drift layer 2 includes a first drift layer 201 and a second drift layer 202, the second drift layer 202 is of the first conductivity type and is located in the fast recovery diode region 104, and the first drift layer 201 is located in the insulated gate bipolar transistor region 103, so as to respectively constitute the basic structure of the fast recovery diode region 104 and the basic structure of the insulated gate bipolar transistor region 103. In the insulated gate bipolar transistor region 103, the drift layer 2 is responsible for carrying the main current, and therefore, the distribution of the electric field has an important influence on the performance of the semiconductor device 100.

[0046] Furthermore, the first drift layer 201 includes a first sub-drift layer 2011 of a first conductivity type and a second sub-drift layer 2012 of a second conductivity type, and the insulated gate bipolar transistor region 103 includes a first region 1031 and a second region 1032 , the first region 1031 is adjacent to the fast recovery diode region 104 , and the second region 1032 is far away from the fast recovery diode region 104 .

[0047] Furthermore, a first sub-drift layer 2011 and a second sub-drift layer 2012 are provided in the first region 1031, and the first sub-drift layer 2011 is closer to the first main surface 101 in the first direction than the second sub-drift layer 2012. In the embodiment of the present invention, the first conductivity type is N-type, and the second conductivity type is P-type, so that in the first region 1031 of the insulated gate bipolar transistor region 103 close to the fast recovery diode region 104, the first sub-drift layer 2011 and the second sub-drift layer 2012 can form a blocking junction.

[0048] Furthermore, the first sub-drift layer 2011 and the second sub-drift layer 2012 are also provided in the second region 1032. In the second region 1032, the second sub-drift layer 2012 is closer to the first main surface 101 in the first direction than the first sub-drift layer 2011. Accordingly, in the second region 1032 of the insulated gate bipolar transistor region 103 away from the fast recovery diode region 104, the first sub-drift layer 2011 and the second sub-drift layer 2012 may also form a PN junction.

[0049] In the embodiment of the present invention, the base layer 3 is arranged on the side of the drift layer 2 facing the first main surface 101, the surface of the base layer 3 away from the drift layer 2 constitutes a part of the first main surface 101, the emitter metal layer 4 is arranged on the first main surface 101, and the collector metal layer 7 is arranged on the second main surface 102. In this way, the basic structure of the insulated gate bipolar transistor region 103 and the fast recovery diode region 104 in the semiconductor device 100 can be formed, and the forward conduction characteristics of the insulated gate bipolar transistor region 103 and the reverse recovery characteristics of the fast recovery diode region 104 can be guaranteed.

[0050] Furthermore, an emitter region 12 and a contact hole region 13 are also provided in the base layer 3, wherein the emitter region 12 and the contact hole region 13 both constitute at least a portion of the first main surface 101, and the emitter region 12 is electrically connected to the emitter metal layer 4 so that the emitter region 12 and the emitter metal layer 4 have the same electric potential.

[0051] In the embodiment of the present invention, the depth direction of the groove 5 penetrates the base layer 3 from the first main surface 101 and reaches the drift layer 2. There are multiple grooves 5, and the multiple grooves 5 are arranged at intervals in the second direction. At least one of the multiple grooves 5 extends into the first sub-drift layer 2011 of the first region 1031, so that the electron flow channel in the insulated gate bipolar transistor region 103 can be normally opened. It should be noted that the depth direction of the groove 5 in the embodiment of the present invention is Figure 1 The first direction in .

[0052] In an embodiment of the present invention, a groove 5 is provided in the insulated gate bipolar transistor region 103. The groove 5 in this region is an active groove, and an active gate is provided inside the groove. The active groove can extend the active gate of the insulated gate bipolar transistor region 103 from the first main surface 101 to the first drift layer 201. The active gate is electrically connected to the gate pad 11 of the semiconductor device 100, so that the active gate and the gate pad 11 can have the same potential.

[0053] In the active trench, the active gate is spaced apart from the inner wall of the active trench, an active gate insulating film is arranged between the active gate and the active trench, and the active gate is arranged opposite to the emitter region 12, the base layer 3 and the first drift layer 201 through the active gate insulating film, so as to ensure the normal operation of the insulated gate bipolar transistor region 103.

[0054] In the semiconductor device 100 of the embodiment of the present invention, a groove 5 is provided in both the fast recovery diode region 104 and the transition region. The groove 5 in this region is a virtual groove, a virtual gate is provided inside the virtual groove, the virtual gate and the inner wall of the virtual groove are spaced apart, and a virtual gate insulating film is provided between the virtual gate and the virtual groove.

[0055] In the embodiment of the present invention, the collector layer 601 is arranged on the side of the first drift layer 201 facing the second main surface 102, the side of the collector layer 601 away from the drift layer 2 constitutes at least part of the second main surface 102, and the collector layer 601 is located in the insulated gate bipolar transistor region 103. The cathode layer 602 is arranged on the side of the second drift layer 202 facing the second main surface 102, the side of the cathode layer 602 away from the drift layer 2 constitutes at least part of the second main surface 102, and the cathode layer 602 is located in the fast recovery diode region 104. In this way, the basic structure of the insulated gate bipolar transistor region 103 and the fast recovery diode region 104 can be formed.

[0056] According to an embodiment of the present invention, at the initial forward conduction stage of the reverse conducting insulated gate bipolar transistor, after the gate voltage opens the channel on the active gate side of the semiconductor device 100, the carriers flow from the emitter region 12 of the first conductivity type through the first region 1031 along the first direction, reach the side of the collector layer 601 close to the drift layer 2, and finally flow out from the cathode layer 602 in the fast recovery diode region 104. In this process, only electrons, one type of carrier, participate in conduction. At this time, the reverse conducting insulated gate bipolar transistor is in a unipolar conduction state.

[0057] In the unipolar conduction state, carriers will generate a voltage drop on the path they flow through. When this voltage drop is greater than the built-in potential of the PN junction formed by the collector layer 601 and the drift layer 2, the PN junction formed by the collector layer 601 of the second conductivity type and the first sub-drift layer 2011 of the first conductivity type in the drift layer 2 is turned on, and holes are injected from the collector layer 601 into the drift layer 2, and then flow out from the base layer 3 after passing through the drift layer 2. In this process, both electrons and holes are involved in conduction. At this time, the reverse conducting insulated gate bipolar transistor is in a bipolar conduction state.

[0058] During the process of the reverse conducting insulated gate bipolar transistor switching from the unipolar conduction state and the bipolar conduction state, due to the injection of a large amount of holes, the reverse conducting insulated gate bipolar transistor will produce a conductivity modulation effect, resulting in a decrease in the on-resistance of the semiconductor device 100. At this time, there is a negative resistance region in the current-voltage output characteristic curve of the semiconductor device 100 where the current increases and the voltage decreases, which is called the voltage foldback phenomenon.

[0059] Furthermore, by setting a second sub-drift layer 2012 of the second conductivity type in the second region 1032 of the insulated gate bipolar transistor region 103 near the first main surface 101, the area of ​​the effective drift region in the insulated gate bipolar transistor region 103 can be reduced, and more holes can be accumulated to attract the movement of electrons on the side of the collector layer 601 close to the drift layer 2, thereby making it easier to turn on the semiconductor device 100. As a result, the reverse conducting insulated gate bipolar transistor can be accelerated from the unipolar conduction state to the bipolar conduction state, thereby reducing or even eliminating the voltage foldback phenomenon.

[0060] Furthermore, when the semiconductor device 100 is forward-turned off, the blocking junction is reverse biased, and the electric field is mainly borne by the blocking junction. At the same time, when turned off, the first sub-drift layer 2011 and the second sub-drift layer 2012 in the first region 1031 can assist in depleting carriers and reducing the peak electric field of the semiconductor device 100, thereby improving the reverse voltage resistance and breakdown voltage resistance of the semiconductor device 100.

[0061] Combination Figure 1As shown, when the semiconductor device 100 is subjected to high voltage, the first sub-drift layer 2011 and the second sub-drift layer 2012 in the first region 1031 and the second region 1032 are mutually depleted and a lateral electric field is generated. In the embodiment of the present invention, the junction of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the first region 1031 and the junction of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the second region 1032 are flush with each other, and such an arrangement can ensure the uniformity of the electric field in the insulated gate bipolar transistor region 103.

[0062] According to some embodiments of the present invention, Figure 1 As shown, the depths of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the first region 1031 in the first direction are equal and are both D1, and the depths of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the second region 1032 in the first direction are equal and are both D2, and D1 and D2 satisfy the relationship: D1=D2.

[0063] Specifically, under the condition that the junction of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the first region 1031 is ensured to be flush with the junction of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the second region 1032, the depths of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the first region 1031 in the first direction can be set to be equal, and the depths of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the second region 1032 in the first direction can be set to be equal.

[0064] According to some other embodiments of the present invention, the depths of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the first region 1031 in the first direction may not be equal. Similarly, the depths of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the second region 1032 in the first direction may not be equal.

[0065] It should be noted that the blocking junction in the first region 1031 bears the main electric field, and the depth of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the first direction can be specifically set according to the electric field distribution calculation, and it is still necessary to make the junction of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the second region 1032 flush with the junction of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the first region 1031.

[0066] Furthermore, the size of the first region 1031 in the second direction and the size of the second region 1032 in the second direction can be specifically set based on the electric field distribution calculation to ensure that the active trench extends from the first main surface 101 to the first region 1031 in the first direction, so that the active trench is arranged opposite to the first sub-drift layer 2011 in the first region 1031 to ensure that the electron flow channel in the insulated gate bipolar transistor region is normally opened.

[0067] Combination Figure 1 As shown, the semiconductor device 100 further includes a first dielectric isolation layer 8, which is disposed between the insulated gate bipolar transistor region 103 and the fast recovery diode region 104. The depth direction of the first dielectric isolation layer 8 extends from the second main surface 102 toward the first main surface 101, and the first dielectric isolation layer 8 penetrates between the collector layer 601 and the cathode layer 602, and reaches the drift layer 2. It should be noted that the depth direction of the first dielectric isolation layer 8 in the embodiment of the present invention is Figure 1 The first direction in

[0068] Specifically, after the gate voltage opens the channel, the carriers reach the side of the collector layer 601 close to the drift layer 2 from the emitter region 12. At this time, the first dielectric isolation layer 8 can block the carriers on the side of the collector layer 601 close to the drift layer 2 in the first direction from flowing to the side of the cathode layer 602 close to the drift layer 2. This can increase the resistance of the collector layer 601 on the side close to the drift layer 2 in the first direction, thereby increasing the voltage drop on the carrier flow path on the side of the collector layer 601 on the side close to the drift layer 2 in the first direction, and thus speeding up the bipolar conduction rate of the insulated gate bipolar transistor region 103, so that the insulated gate bipolar transistor region 103 quickly enters the bipolar conduction state from the unipolar conduction state, so as to reduce or even eliminate the voltage foldback phenomenon.

[0069] According to an embodiment of the present invention, the first dielectric isolation layer 8 is a silicon dioxide isolation layer. Specifically, the first dielectric isolation layer 8 is provided with a silicon dioxide isolation layer, which can effectively block the carriers on the side of the collector layer 601 close to the drift layer 2 from the insulated gate bipolar transistor region 103 to the fast recovery diode region 104, so that the resistance of the collector layer 601 on the side close to the drift layer 2 in the insulated gate bipolar transistor region 103 can be increased to increase the voltage drop on the carrier flow path, thereby enabling the semiconductor device 100 to quickly enter bipolar conduction from unipolar conduction, so as to reduce or even eliminate the voltage foldback phenomenon in the semiconductor device 100.

[0070] Combination Figure 1As shown, one end of the first dielectric isolation layer 8 toward the first main surface 101 does not exceed the second sub-drift layer 2012 in the first region 1031 and the first sub-drift layer 2011 in the second region 1032. Such a configuration can prevent the first dielectric isolation layer 8 from extending too deep into the drift layer 2 in the first direction. On the one hand, it can ensure that the first dielectric isolation layer 8 has a blocking effect on the movement of carriers from the insulated gate bipolar transistor region 103 to the fast recovery diode region 104. Compared with the reverse-conducting insulated gate bipolar transistor, the speed at which the device enters bipolar conduction can be accelerated. On the other hand, if the first dielectric isolation layer 8 extends too deep into the drift layer 2, the carrier concentration of the fast recovery diode region 104 will be too limited, which will interfere with the reverse recovery characteristics of the wind. As a result, not only can the voltage foldback phenomenon when the insulated gate bipolar transistor region 103 is forward-conducted be reduced, but also the reverse recovery of the fast recovery diode region 104 can be ensured to be turned on normally.

[0071] Combination Figure 1 As shown, the semiconductor device 100 also includes a second dielectric isolation layer 9, the collector metal layer 7 includes a first collector metal layer 701 and a second collector metal layer 702, the first collector metal layer 701 is located in the insulated gate bipolar transistor region 103, the second collector metal layer 702 is arranged in the fast recovery diode region 104, and the first collector metal layer 701 and the second collector metal layer 702 are arranged at intervals.

[0072] Specifically, the first collector metal layer 701 is located in the insulated gate bipolar transistor region 103 to form the basic structure of the insulated gate bipolar transistor region 103. The second collector metal layer 702 is located in the fast recovery diode region 104 to form the basic structure of the fast recovery diode region 104. The second dielectric isolation layer 9 is disposed between the first collector metal layer 701 and the second collector metal layer 702, and corresponds to the first dielectric isolation layer 8.

[0073] According to some embodiments of the present invention, the second dielectric isolation layer 9 may be a silicon dioxide isolation layer. In this embodiment, the second dielectric isolation layer 9 and the first dielectric isolation layer 8 may be integrally formed or separately formed during the production process of the semiconductor device 100. It should be noted that, in this embodiment, the first collector metal layer 701 and the second collector metal layer 702 in the semiconductor device 100 have the same potential.

[0074] According to other embodiments of the present invention, the second dielectric isolation layer 9 may be air. In this embodiment, after the first dielectric isolation layer 8 is manufactured, it constitutes at least part of the second main surface 102. Then, a collector metal is deposited on the second main surface 102, wherein the first collector metal layer 701 of the insulated gate bipolar transistor region 103 and the second collector metal layer 702 of the fast recovery diode region 104 are spaced apart in the second direction, and part of the second main surface 102 constituted by the first dielectric isolation layer 8 is exposed to the collector metal layer 7. It should be noted that, in this embodiment, the first collector metal layer 701 and the second collector metal layer 702 in the semiconductor device 100 have the same potential.

[0075] According to some further embodiments of the present invention, the second dielectric isolation layer 9 may be a collector metal. In this embodiment, after the first dielectric isolation layer 8 is manufactured, it constitutes at least a portion of the second main surface 102. Then, a collector metal is deposited on the second main surface 102, wherein the collector metal covers the second main surface 102, and the second dielectric isolation layer 9 connects the first collector metal layer 701 and the second collector metal layer 702 into a whole. It should be noted that, in this embodiment, the first collector metal layer 701 and the second collector metal layer 702 in the semiconductor device 100 have the same potential.

[0076] Combination Figure 1 As shown, the semiconductor device 100 further includes a floating layer 10 of the second conductivity type, the floating layer 10 is disposed in the second drift layer 202, the depth direction of the floating layer 10 extends from the side of the second drift layer 202 adjacent to the second main surface 102 toward the first main surface 101, and the floating layer 10 is in contact with the cathode layer 602. It should be noted that the depth direction of the floating layer 10 in the embodiment of the present invention is Figure 1 The first direction in .

[0077] Specifically, when the semiconductor device 100 is forward-conducted, the floating layer 10 can provide an electron potential barrier to block electrons from flowing from the side of the collector layer 601 close to the drift layer 2 to the side of the cathode layer 602 close to the drift layer 2. This can concentrate the current on the collector layer 601, thereby increasing the resistance on the collector layer 601 and allowing the device to quickly enter bipolar conduction, thereby suppressing the voltage foldback phenomenon.

[0078] Furthermore, when the semiconductor device 100 is reverse recovered, the floating layer 10 can also control the hole injection efficiency of the cathode layer 602 into the second drift layer 202, thereby improving the softness of the reverse conducting insulated gate bipolar transistor during reverse recovery and avoiding voltage overshoot during reverse recovery.

[0079] In an embodiment of the present invention, the doping concentration of the second conductive type floating layer 10 is low-concentration doping. This is because the doping concentration of the first conductive type second drift layer 202 in the fast recovery diode region 104 is also low-concentration doping. If the doping concentration of the floating layer 10 is too high, it will affect the opening of the fast recovery diode region 104.

[0080] Combination Figure 1 As shown, there are multiple floating layers 10, and the multiple floating layers 10 are arranged at intervals through the drift layer 2. In this way, the side of the cathode layer 602 facing the first main surface 101 can at least partially contact the second drift layer 202, so that there is a current gap in the fast recovery diode region 104, so that the cathode layer 602 can normally extract charges from the second drift layer 202 during the device shutdown process.

[0081] Combination Figure 1 As shown, one end of the first dielectric isolation layer 8 adjacent to the first main surface 101 protrudes from one end of the floating layer 10 adjacent to the first main surface 101. While the floating layer 10 is in contact with the cathode layer 602, a silicon dioxide isolation layer is provided between the fast recovery diode region 104 and the insulated gate bipolar transistor region 103, so as to prevent the floating layer 10 from contacting the cathode layer 602 and affecting the withstand voltage of the device.

[0082] Combine the following Figure 2-Figure 13 A method for manufacturing the semiconductor device 100 according to an embodiment of the present invention is described.

[0083] Combination Figure 2-Figure 13 As shown, a substrate of a semiconductor device 100 with a drift layer 2 of a first conductivity type is provided, the substrate having a first main surface 101 and a second main surface 102 opposite to the first main surface 101, the first main surface 101 and the second main surface 102 being spaced apart in a first direction. The semiconductor device 100 is manufactured based on the substrate.

[0084] Furthermore, a groove 5 is etched on the substrate by photolithography and etching, a gate oxide layer 1501 is first deposited in the groove 5 to cover the inner wall of the groove 5, and then a gate 15 metal is deposited in the groove 5. The gate 15 metal includes but is not limited to polysilicon.

[0085] Furthermore, ions of the second conductivity type are implanted into the drift layer 2 near the first main surface 101 to form a base layer 3. A carrier storage layer 14 is formed on one side of the drift layer 2 near the base layer 3.

[0086] Furthermore, ions of the first conductivity type are implanted on the base layer 3 to form an emitter region 12 . The emitter region 12 is located on at least one side of the trench 5 in the second direction and constitutes at least a portion of the first main surface 101 .

[0087] Furthermore, ions of the first conductivity type are implanted on the base layer 3 to form a contact hole region 13 . The contact hole region 13 constitutes at least a portion of the first main surface 101 and is spaced apart from the trench 5 in the second direction.

[0088] Furthermore, a dielectric layer is deposited on the first main surface 101 of the substrate, and the dielectric layer is etched to form contact holes, a gate pad 11 and an emitter metal layer 4 at positions corresponding to the gate 15, the emitter region 12 and the contact hole region 13 on the dielectric layer, wherein the gate pad 11 is electrically connected to the active gate, and the emitter metal layer 4 is electrically connected to the emitter region 12.

[0089] Furthermore, etching is performed on the side of the substrate facing the second main surface 102 to form a groove between the insulated gate bipolar transistor region 103 and the fast recovery diode region 104 , and silicon dioxide is deposited in the groove to form a first dielectric isolation layer 8 .

[0090] Furthermore, ions of the second conductivity type are implanted into the drift layer 2 corresponding to the IGBT region 103 and close to the second main surface 102 to form a buffer layer 16 on one side of the drift layer 2 close to the second main surface 102 in the IGBT region 103 .

[0091] Further, ions of the second conductivity type are implanted in the first region 1031 of the insulated gate bipolar transistor region 103 near the fast recovery diode region 104 to form a second sub-drift layer 2012 in the first region 1031. Ions of the second conductivity type are then implanted in the first drift layer 201 far from the fast recovery diode region 104 to form a second sub-drift layer 2012 in the second region 1032. The second sub-drift layer 2012 in the first region 1031 forms a blocking junction with the first sub-drift layer 2011.

[0092] Furthermore, ions of the second conductivity type are implanted into the drift layer 2 in the fast recovery diode region 104 near the second main surface 102 to form a plurality of floating layers 10 disposed at intervals.

[0093] Further, ions of the second conductivity type are implanted at a position of the second main surface 102 of the substrate corresponding to the insulated gate bipolar transistor region 103 to form a collector layer 601, wherein the ion doping concentration of the collector layer 601 is higher than the ion doping concentration of the second sub-drift layer 2012. Then, ions of the first conductivity type are implanted at a side of the floating layer 10 facing the second main surface 102 to form a cathode layer 602.

[0094] Further, a collector metal is deposited on the side of the second main surface 102 of the substrate away from the collector layer 601 to form a first collector metal layer 701 in the insulated gate bipolar transistor region 103 and a second collector metal layer 702 in the fast recovery diode region 104. Further, silicon dioxide is deposited between the first collector metal layer 701 and the second collector metal layer 702 to form a second dielectric isolation layer 9. At this point, the second dielectric isolation layer 9 and the first dielectric isolation layer 8 are an integrated silicon dioxide isolation layer. At this point, the semiconductor device 100 of the embodiment of the present invention is completed.

[0095] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "circumferential", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0096] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0097] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate (1) having a first main surface (101) and a second main surface (102) opposite to the first main surface (101), wherein the first main surface (101) and the second main surface (102) are arranged at intervals in a first direction; A drift layer (2), the drift layer (2) being arranged on the semiconductor substrate (1) and located between the first main surface (101) and the second main surface (102), the semiconductor substrate (1) comprising an insulated gate bipolar transistor region (103) and a fast recovery diode region (104), the insulated gate bipolar transistor region (103) being arranged circumferentially around the outside of the fast recovery diode region (104); The drift layer (2) comprises a first drift layer (201) and a second drift layer (202), the second drift layer (202) is of a first conductivity type and is located in the fast recovery diode region (104), the first drift layer (201) is located in the insulated gate bipolar transistor region (103) and comprises a first sub-drift layer (2011) of the first conductivity type and a second sub-drift layer (2012) of the second conductivity type, the insulated gate bipolar transistor region (103) comprises a first region (1031) and a second region (1032), the first region (1031) is adjacent to the fast recovery diode region (104), and the second region (1032) is away from the fast recovery diode region (104); The first region (1031) is provided with the first sub-drift layer (2011) and the second sub-drift layer (2012); the first sub-drift layer (2011) is closer to the first main surface (101) in a first direction than the second sub-drift layer (2012); The first sub-drift layer (2011) and the second sub-drift layer (2012) are also arranged in the second region (1032); in the second region (1032), the second sub-drift layer (2012) is closer to the first main surface (101) in the first direction than the first sub-drift layer (2011); A base layer (3) of a second conductivity type, the base layer (3) being arranged on a side of the drift layer (2) facing the first main surface (101), and a surface of the base layer (3) on a side away from the drift layer (2) constituting a part of the first main surface (101); An emitter metal layer (4), the emitter metal layer (4) being arranged on the first main surface (101); A groove (5), wherein the depth direction of the groove (5) penetrates the base layer (3) from the first main surface (101) and reaches the drift layer (2), the groove (5) is multiple, the multiple grooves (5) are arranged at intervals in the second direction, and at least one of the multiple grooves (5) extends into the first sub-drift layer (2011) of the first region (1031); a collector layer (601) of the second conductivity type and a cathode layer (602) of the first conductivity type, wherein the collector layer (601) is arranged on a side of the first drift layer (201) facing the second main surface (102), a side of the collector layer (601) away from the drift layer (2) constitutes at least a portion of the second main surface (102), and the collector layer (601) is located in the insulated gate bipolar transistor region (103); The cathode layer (602) is arranged on a side of the second drift layer (202) facing the second main surface (102), a side of the cathode layer (602) away from the drift layer (2) constitutes at least a portion of the second main surface (102), and the cathode layer (602) is located in the fast recovery diode region (104); A collector metal layer (7), wherein the collector metal layer (7) is arranged on the second main surface (102).

2. The semiconductor device according to claim 1, wherein: The boundary between the first sub-drift layer (2011) and the second sub-drift layer (2012) in the first region (1031) and the boundary between the first sub-drift layer (2011) and the second sub-drift layer (2012) in the second region (1032) are flush with each other.

3. The semiconductor device according to claim 2, wherein: The first sub-drift layer (2011) and the second sub-drift layer (2012) in the first region (1031) have the same depth in the first direction and are both D1, and the first sub-drift layer (2011) and the second sub-drift layer (2012) in the second region (1032) have the same depth in the first direction and are both D2, and D1 and D2 satisfy the relationship: D1=D2.

4. The semiconductor device according to claim 1, wherein: The invention also comprises a first dielectric isolation layer (8), wherein the first dielectric isolation layer (8) is arranged between the insulated gate bipolar transistor region (103) and the fast recovery diode region (104), wherein the first dielectric isolation layer (8) extends in depth from the second main surface (102) toward the first main surface (101), and wherein the first dielectric isolation layer (8) penetrates between the collector layer (601) and the cathode layer (602) and reaches the drift layer (2).

5. The semiconductor device according to claim 4, wherein: The first dielectric isolation layer (8) is a silicon dioxide isolation layer.

6. The semiconductor device according to claim 4, wherein: One end of the first dielectric isolation layer (8) facing the first main surface (101) does not extend beyond the second sub-drift layer (2012) in the first region (1031) and the first sub-drift layer (2011) in the second region (1032).

7. The semiconductor device according to claim 4, wherein: The invention also comprises a second dielectric isolation layer (9), wherein the collector metal layer (7) comprises a first collector metal layer (701) and a second collector metal layer (702), wherein the first collector metal layer (701) is located in the insulated gate bipolar transistor region (103), the second collector metal layer (702) is arranged in the fast recovery diode region (104), the first collector metal layer (701) and the second collector metal layer (702) are arranged at intervals, and the second dielectric isolation layer (9) is arranged between the first collector metal layer (701) and the second collector metal layer (702) and corresponds to the first dielectric isolation layer (8).

8. The semiconductor device according to claim 4, wherein: The invention also comprises a floating layer (10) of the second conductivity type, wherein the floating layer (10) is arranged in the second drift layer (202), and the depth direction of the floating layer (10) extends from a side of the second drift layer (202) adjacent to the second main surface (102) toward the first main surface (101), and the floating layer (10) is in contact with the cathode layer (602).

9. The semiconductor device according to claim 8, wherein: There are a plurality of floating layers (10), and the plurality of floating layers (10) are arranged at intervals through the drift layer (2).

10. The semiconductor device according to claim 8, wherein: One end of the first dielectric isolation layer (8) adjacent to the first main surface (101) protrudes beyond one end of the floating layer (10) adjacent to the first main surface (101).

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