Field effect transistor, manufacturing method thereof and memory
By setting the annular first gate and the annular second gate in the field effect tube, the performance degradation caused by the short channel effect is solved, the switching current ratio and density are improved, and more efficient memory manufacturing is achieved.
Patent Information
- Application Number
- CN202310723741.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-16
- Publication Date
- 2024-12-17
AI Technical Summary
In the prior art, the performance of field effect tubes has significantly reduced due to the short channel effect, making it difficult to manufacture high-density memory cells on a limited substrate.
By providing an annular first gate on the outside of the semiconductor structure and at least part of the annular second gate on the inside, the semiconductor structure is affected by the electric fields of the two gates at the same time, the short channel effect is reduced, the switching current ratio is improved, and Reduce the size of the field effect tube.
It significantly improves the performance and density of field effect tubes, reduces manufacturing difficulty and cost, and enhances the performance of memory.
Smart Images
Figure CN119153512A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and more specifically, to a field effect transistor, a manufacturing method thereof, and a memory. Background Art
[0002] Semiconductor storage can be divided into volatile memory (RAM, including DRAM and SRAM, etc.) and non-volatile memory (ROM and non-ROM) based on application.
[0003] Taking DRAM as an example, the traditional known DRAM has multiple repeated "storage cells", each of which has a capacitor and a transistor. The capacitor can store 1 bit of data, and after charging and discharging, the amount of charge stored in the capacitor can correspond to the binary data "1" and "0" respectively. The transistor is the switch that controls the charging and discharging of the capacitor.
[0004] In order to reduce the cost of products as much as possible, people hope to make as many storage units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention
[0005] In view of the shortcomings of the existing methods, the present application proposes a field effect transistor and a manufacturing method thereof, and a memory, so as to solve the technical problem in the prior art that the performance of the field effect transistor is significantly reduced due to the obvious short channel effect.
[0006] In a first aspect, an embodiment of the present application provides a field effect transistor, including:
[0007] The semiconductor structure is arranged on one side of the substrate, and the semiconductor structure is ring-shaped;
[0008] A first electrode, a first gate electrode, and a second electrode are sequentially stacked on one side of the substrate, the first gate electrode is arranged around the outer side of the semiconductor structure, and the first electrode and the second electrode are both connected to the semiconductor structure;
[0009] The second gate, at least a portion of the second gate is surrounded by the semiconductor structure, and the first gate and the second gate are both insulated from the semiconductor structure.
[0010] In a second aspect, an embodiment of the present application provides a memory, including: the field effect transistor provided in the first aspect.
[0011] In a third aspect, an embodiment of the present application provides a method for manufacturing a field effect transistor, comprising:
[0012] Forming a first electrode, a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer in sequence on one side of the substrate;
[0013] A first hole is formed from top to bottom in the second conductive layer, the second dielectric layer and the first conductive layer based on a patterning process; the sidewall of the first hole is a first conductive structure formed by the first conductive layer, a second dielectric structure formed by the second dielectric layer and a second electrode formed by the second conductive layer;
[0014] Performing back etching on the first conductive structure exposed on the inner side wall of the first hole to form a groove, and the back-etched first conductive structure forms a first gate;
[0015] Etching the first dielectric layer to expose the portion in the first hole, so that at least a portion of the first electrode is exposed, and the etched first dielectric layer forms a first dielectric structure;
[0016] a first gate dielectric layer formed in the groove;
[0017] forming a semiconductor structure covering the inner sidewall of the first hole, wherein the semiconductor structure encloses a second hole;
[0018] A second gate dielectric layer and a second gate are sequentially formed on the inner sidewall of the second hole.
[0019] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:
[0020] In the field effect transistor provided in the embodiment of the present application, by setting the first gate to surround the outer side of the semiconductor structure, and setting at least a portion of the second gate to be surrounded by the semiconductor structure, the semiconductor structure can be affected by the electric field applied by the first gate and the second gate at the same time, which can significantly reduce the influence of the short channel effect, help to improve the switching current ratio of the field effect tube, can ensure the performance of the field effect tube, and at the same time, help to further reduce the size of the field effect tube.
[0021] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
[0023] Figure 1 A schematic diagram of the structure of a field effect transistor provided in an embodiment of the present application;
[0024] Figure 2 Provided in the embodiments of this application Figure 1 A schematic diagram of the structure of the semiconductor structure in the field effect transistor shown;
[0025] Figure 3 A schematic diagram of the structure of another field effect transistor provided in an embodiment of the present application;
[0026] Figure 4 A schematic diagram of a process for manufacturing a field effect transistor provided in an embodiment of the present application;
[0027] Figure 5 A schematic diagram of the structure after forming a first dielectric layer in a method for manufacturing a field effect transistor provided in an embodiment of the present application;
[0028] Figure 6 A schematic diagram of the structure after forming a second conductive layer in a method for manufacturing a field effect transistor provided in an embodiment of the present application;
[0029] Figure 7 A schematic diagram of the structure after a third dielectric layer is formed in a method for manufacturing a field effect transistor provided in an embodiment of the present application;
[0030] Figure 8 A schematic diagram of a structure after a third dielectric junction and a second conductive structure are formed in a method for manufacturing a field effect transistor provided in an embodiment of the present application;
[0031] Fig. 9 A schematic diagram of a structure after the second conductive structure is etched back to form a third conductive structure in a method for manufacturing a field effect transistor provided in an embodiment of the present application;
[0032] Fig.10 A schematic diagram of a structure after a first conductive structure is formed in a method for manufacturing a field effect transistor provided in an embodiment of the present application;
[0033] Fig.11 A schematic diagram of a structure after a first conductive structure is etched back to form a first gate in a method for manufacturing a field effect transistor provided in an embodiment of the present application;
[0034] Fig.12 A schematic diagram of a structure after a first dielectric structure is formed in a method for manufacturing a field effect transistor provided in an embodiment of the present application;
[0035] Fig.13 A schematic diagram of the structure after a fifth dielectric layer is formed in a method for manufacturing a field effect transistor provided in an embodiment of the present application;
[0036] Fig.14 A schematic diagram of the structure after forming a first gate dielectric layer in a method for manufacturing a field effect transistor provided in an embodiment of the present application;
[0037] Fig.15 A schematic diagram of a structure after a semiconductor structure is formed in a method for manufacturing a field effect transistor provided in an embodiment of the present application;
[0038] Fig.16A schematic diagram of the structure after a connection end is formed in a method for manufacturing a field effect transistor provided in an embodiment of the present application.
[0039] Description of reference numerals:
[0040] 11-first electrode; 12-second electrode; 13-first grid; 14-second grid;
[0041] 15-Semiconductor structure;
[0042] 151- annular portion; 152- bottom portion;
[0043] 1511-first annular sub-portion; 1512-second annular sub-portion;
[0044] 16-first dielectric structure; 17-second dielectric structure; 18-first gate dielectric layer; 19-second gate dielectric layer;
[0045] 100 - substrate; 101 - fourth dielectric layer; 102 - first dielectric layer;
[0046] 103- a first conductive layer;
[0047] 1031 - a first conductive structure;
[0048] 104- a second dielectric layer;
[0049] 105- a second conductive layer;
[0050] 1051 - second conductive structure; 1052 - third conductive structure;
[0051] 106- a third dielectric layer;
[0052] 1061-third medium structure; 1062-fourth medium structure;
[0053] 107 - first hole; 108 - third hole; 109 - fifth dielectric layer; 110 - second hole; 111 - sixth dielectric layer; 112 - connection end. DETAILED DESCRIPTION
[0054] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.
[0055] Those skilled in the art will appreciate that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".
[0056] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.
[0057] The short channel effect means that when the channel length is reduced to a certain extent, the threshold voltage and the channel length become strongly correlated. As the channel length decreases, the threshold voltage will also decrease significantly.
[0058] As the integration of memories such as DRAM (Dynamic Random Access Memory) and MRAM (Magnetoresistive Random Access Memory) becomes increasingly higher, the size of field effect transistors used in such memories needs to become smaller and smaller.
[0059] For example, in the related technology, the size of the capacitor of the 1T (Transistor) 1C (Capacitor) storage unit in DRAM has been reduced to the limit. The current main direction of attack is to reduce the size of the transistor. How to overcome the short channel effect and ensure the performance of the transistor is the current key research direction.
[0060] The field effect transistor, its manufacturing method, and memory provided in this application are intended to solve the above technical problems of the prior art.
[0061] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following implementation modes can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementation modes will not be described repeatedly.
[0062] The present application embodiment provides a field effect tube, the structure diagram of which is as follows: Figure 1 The field effect transistor comprises: a first electrode 11, a second electrode 12, a first gate 13, a second gate 14 and a semiconductor structure 15.
[0063] In the embodiment of the present application, the semiconductor structure 15 is disposed on one side of the substrate 100, and the semiconductor structure 15 is annular. The first electrode 11, the first gate 13, and the second electrode 12 are sequentially stacked and disposed on one side of the substrate 100, the first gate 13 is disposed around the outer side of the semiconductor structure 15, and the first electrode 11 and the second electrode 12 are both connected to the semiconductor structure 15; the second gate 14, at least a portion of the second gate 14 is surrounded by the semiconductor structure 15, and the first gate 13 and the second gate 14 are both insulated from the semiconductor structure 15.
[0064] In the field effect transistor provided in the embodiment of the present application, by setting the first gate 13 to surround the outer side of the semiconductor structure 15, and setting at least a portion of the second gate 14 to be surrounded by the semiconductor structure 15, the semiconductor structure 15 can be simultaneously affected by the electric field applied by the first gate 13 and the second gate 14, which can significantly reduce the influence of the short channel effect, help to improve the switching current ratio of the field effect transistor, can ensure the performance of the field effect transistor, and at the same time, help to further reduce the size of the field effect transistor.
[0065] like Figure 1 As shown, the semiconductor structure 15 is disposed on one side of the substrate 100 . In the embodiment of the present application, the semiconductor structure 15 is ring-shaped, that is, the semiconductor structure 15 includes an outer side surface and an inner side surface.
[0066] In the present application embodiment, Figure 1 As shown, in a direction away from the substrate 100, the first electrode 11, the first gate 13 and the second electrode 12 are sequentially stacked on one side of the substrate 100. The first electrode 11 and the second electrode 12 are both connected to the semiconductor structure 15. Optionally, the first electrode 11 is one of the source and the drain, and the second electrode 12 is the other of the source and the drain.
[0067] In the present application embodiment, Figure 1 As shown, along the direction away from the substrate 100 , the first gate 13 is located between the first electrode 11 and the second electrode 12 , and the first gate 13 surrounds the outer side of the semiconductor structure 15 , that is, the first gate 15 is a ring gate.
[0068] In the present application embodiment, Figure 1 As shown, at least a portion of the second gate 14 is located in a space enclosed by the annular semiconductor structure 15 , that is, the second gate 14 is located on the inner side of the annular semiconductor structure 15 .
[0069] In the embodiment of the present application, the first gate 13 and the second gate 14 are both insulated from the semiconductor structure 15. By arranging the second gate 14 on the inner side of the annular semiconductor structure 15 and the first gate 13 surrounding the outer side of the semiconductor structure 15, the semiconductor structure 15 can be simultaneously affected by the electric field applied by the first gate 13 and the second gate 14, which can significantly reduce the impact of the short channel effect, help to improve the switching current ratio of the field effect tube, and ensure the performance of the field effect tube.
[0070] Meanwhile, in the embodiment of the present application, the influence of the short channel effect is reduced by providing the field effect tube with the second gate 14 including the first gate 13, which helps to further reduce the size of the field effect tube.
[0071] Alternatively, if Figure 1 As shown, in one embodiment of the present application, the semiconductor structure 15 is disposed on a side of the first electrode 11 away from the substrate 100 ; and the second electrode 12 is disposed around the outer side of the semiconductor structure 15 .
[0072] In the present application embodiment, Figure 1 As shown, the first electrode 11 is disposed on one side of the substrate 100 , the semiconductor structure 15 is disposed on the side of the first electrode 11 away from the substrate 100 , and the second electrode 12 surrounds the outer side of the semiconductor structure 15 , that is, the second electrode 12 is a ring electrode.
[0073] In the embodiment of the present application, by setting the second electrode 12 as a ring electrode, the contact area between the second electrode 12 and the semiconductor structure 15 can be guaranteed, which is beneficial to the transmission of carriers; at the same time, it is easy to make the second electrode 12, which helps to reduce the difficulty of manufacturing the field effect transistor.
[0074] Alternatively, if Figure 2 As shown, in one embodiment of the present application, the semiconductor structure 15 includes a connected annular portion 151 and a bottom 152, the bottom 152 is arranged on the side of the first electrode 11 away from the substrate 100, and is connected to the first electrode 11; the annular portion 151 is arranged on the side of the bottom 152 away from the substrate 100, the axial direction of the annular portion 151 is perpendicular to the substrate 100, and at least part of the second gate 14 is located in the space enclosed by the annular portion 151 and the bottom 152; the first gate 13 and the second electrode 12 are arranged around the outer side surface of the annular portion 151.
[0075] In the present application embodiment, Figure 2 As shown, the semiconductor structure 15 includes an annular portion 151 and a bottom portion 152 connected to each other, and the annular portion 151 and the bottom portion 152 are integrally formed.
[0076] In the present application embodiment, combined Figure 1 and Figure 2It can be seen that the bottom 152 is disposed on the side of the first electrode 11 away from the substrate 100, the bottom 152 is connected to the first electrode 11, the annular portion 151 is disposed on the side of the bottom 152 away from the first electrode 11, and the axial direction of the annular portion 151 is perpendicular to the substrate 100, so that the annular portion 151 and the bottom 152 are enclosed to form a hole-shaped space. Optionally, as Figure 2 As shown, the bottom 152 is in the shape of a flat plate.
[0077] In the embodiment of the present application, at least part of the second gate 14 is located in the hole-shaped space formed by the annular portion 151 and the bottom portion 152, and the first gate 13 surrounds the outer side of the annular portion 151, so that the annular portion 151 can be affected by the electric field applied by the first gate 13 and the second gate 14 at the same time.
[0078] In the present application embodiment, combined Figure 1 and Figure 2 It can be seen that the second electrode 12 also surrounds the outer side surface of the annular portion 151 .
[0079] Alternatively, if Figure 2 As shown, the annular portion 151 includes a first annular sub-portion 1511 and a second annular sub-portion 1512 connected to each other. The first annular sub-portion 1511 is arranged on a side of the bottom 152 away from the first electrode 11. The first annular sub-portion 1511 is connected to the bottom 152, and the second annular sub-portion 1512 is arranged on a side of the first annular sub-portion 1511 away from the bottom 152.
[0080] Alternatively, if Figure 2 As shown, the maximum diameter of the second annular sub-portion 1512 is greater than the diameter of the first annular sub-portion 1511 .
[0081] It should be noted that, in order to facilitate readers to intuitively understand the specific structure of the semiconductor structure 15 in the field effect transistor provided in the embodiment of the present application, as shown in FIG. Figure 2 As shown, the first annular sub-portion 1511, the second annular sub-portion 1512 and the bottom 152 are divided by dotted lines. In actual products, the semiconductor structure 15 is an integrated structure, and there is no Figure 2 Dotted line shown.
[0082] Alternatively, if Figure 1 As shown, in one embodiment of the present application, along a direction parallel to the substrate 100 , the orthographic projection of the first gate 13 is located within the range of the second gate 14 .
[0083] In the present application embodiment, Figure 1As shown, along the direction parallel to the substrate 100, the positive projection of the first gate 13 is located within the range of the second gate 14, that is, the first gate 13 and the second gate 14 have mutually opposite parts, and when the first gate 13 and the second gate 14 are powered on, the electric field of the first gate 13 and the electric field of the second gate 14 overlap, so that the electric fields applied by the first gate 13 and the second gate 14 can act on the same part of the semiconductor structure 15 at the same time, which helps to improve the switching current ratio of the field effect tube, thereby ensuring the performance of the field effect tube.
[0084] Optionally, in the embodiment of the present application, the first gate 13 surrounds the outer side surface of the semiconductor structure 15, and the second gate 14 is arranged on the inner side surface of the semiconductor structure 15, so that along the circumference of the semiconductor structure 15, the first gate 13 forms a ring-shaped orthographic projection figure surrounding the second gate 14 on the second gate 14, which can increase the part of the semiconductor structure 15 that is simultaneously affected by the electric field applied by the first gate 13 and the second gate 14, thereby helping to further improve the switching current ratio of the field effect tube and further ensure the performance of the field effect tube.
[0085] Alternatively, if Figure 3 As shown, in one embodiment of the present application, the first electrode 11 and the second electrode 12 are both disposed around the outer side of the semiconductor structure 15 .
[0086] In the present application embodiment, Figure 3 As shown, along a direction perpendicular to the substrate 100, the first electrode 11, the first gate 13 and the second electrode 12 are stacked in sequence and spaced apart from each other on one side of the substrate 100, and the semiconductor structure 15 penetrates the second electrode 12, the first gate 13 and the first electrode 11 along a direction perpendicular to the substrate 100, so that the first electrode 11, the first gate 13 and the second electrode 12 are all surrounded by the outer side of the semiconductor structure 15, that is, the first electrode 11, the first gate 13 and the second electrode 12 are all annular electrodes.
[0087] In the embodiment of the present application, by setting the first electrode 11, the first gate 13 and the second electrode 12 to be annular electrodes, during the manufacturing process of the field effect tube, it is beneficial to simultaneously form the annular first electrode 11, the first gate 13 and the second electrode 12 through a patterning process, thereby helping to simplify the manufacturing process of the field effect tube, helping to reduce the manufacturing difficulty of the field effect tube, and further helping to reduce the manufacturing cost of the field effect tube.
[0088] Optionally, in the embodiment of the present application, Figure 3 The structure of the semiconductor structure 15 in the field effect transistor shown can be referred to Figure 2 The description of the semiconductor structure 15 is not repeated here.
[0089] Alternatively, if Figure 1 and Figure 3 As shown, in one embodiment of the present application, the field effect transistor also includes: a first dielectric structure 16, which is arranged on a side of the first electrode 11 away from the substrate 100, and the first gate 13 is arranged on a side of the first dielectric structure 16 away from the substrate 100; a second dielectric structure 17, which is arranged on a side of the first gate 13 away from the substrate 100, and the second electrode 12 is arranged on a side of the second dielectric structure 17 away from the substrate 100; along a direction perpendicular to the substrate 100, the semiconductor structure 15 penetrates the first dielectric structure 16 and the second dielectric structure 17.
[0090] In the present application embodiment, Figure 1 and Figure 3 As shown, along the direction perpendicular to the substrate 100, the first electrode 11, the first dielectric structure 16, the first gate 13, the second dielectric structure 17 and the second electrode 12 are sequentially stacked on one side of the substrate 100. The first dielectric structure 16 is provided to insulate the first electrode 11 and the first gate 13 from each other, and the second dielectric structure 17 is provided to insulate the first gate 13 and the second electrode 12 from each other.
[0091] In the present application embodiment, Figure 1 and Figure 3 As shown, along a direction perpendicular to the substrate 100 , the semiconductor structure 15 penetrates the second electrode 12 , the second dielectric structure 17 , the first gate 13 and the first dielectric structure 16 , that is, the first dielectric structure 16 and the second dielectric structure 17 both surround the outer side of the semiconductor structure 15 .
[0092] Optionally, in the embodiment of the present application, the material of the first dielectric structure 16 includes silicon oxide, and the material of the second dielectric structure 17 includes silicon nitride.
[0093] Alternatively, if Figure 1 and Figure 3 As shown, in one embodiment of the present application, the field effect transistor also includes: a first gate dielectric layer 18, which is arranged in a lateral groove formed by the first dielectric structure 16, the first gate 13 and the second dielectric structure 17; a second gate dielectric layer 19, which is arranged on the inner side of the semiconductor structure 15, and the second gate dielectric layer 19 is arranged around the outer side of the second gate 14.
[0094] In the present application embodiment, Figure 1 and Figure 3 As shown, a first gate dielectric layer 18 is disposed between the first gate 13 and the semiconductor structure 15 along a direction parallel to the substrate 100 .
[0095] Optionally, the first gate dielectric layer 18 is conformal to the first gate 13 , that is, the first gate dielectric layer 18 is a ring structure.
[0096] Optionally, an orthographic projection of the first gate dielectric layer 18 on the outer side of the semiconductor structure 15 overlaps with an orthographic projection of the first gate 13 on the outer side of the semiconductor structure 15 .
[0097] In the present application embodiment, Figure 1 and Figure 3 As shown, in the stacked structure formed by the first dielectric structure 16, the first gate 13 and the second dielectric structure 17, the first gate 13 is retracted relative to the first dielectric structure 16 and the second dielectric structure 17 in a direction away from the semiconductor structure 15 and parallel to the substrate 100, so that the first dielectric structure 16, the first gate 13 and the second dielectric structure 17 enclose a lateral groove opening toward the semiconductor structure 15.
[0098] In the present application embodiment, Figure 1 and Figure 3 As shown, the first gate dielectric layer 18 is arranged in the lateral groove, so that the outer side surface of the first gate dielectric layer 18 facing the semiconductor structure 15, the outer side surface of the first dielectric structure 16 facing the semiconductor structure 15, and the outer side surface of the second dielectric structure 17 facing the semiconductor structure 15 are coplanar, so that in the manufacturing process of the field effect transistor, it is beneficial to form the semiconductor structure 15 on the coplanar surface, which is beneficial to ensure the flatness of the outer side surface of the formed semiconductor structure 15, and can reduce the manufacturing difficulty of the semiconductor structure 15.
[0099] In the present application embodiment, Figure 1 and Figure 3 As shown, the orthographic projection of the first gate dielectric layer 18 on the substrate 100 is located within the orthographic projection of the first dielectric structure 16 on the substrate 100 ; the orthographic projection of the first gate dielectric layer 18 on the substrate 100 is located within the orthographic projection of the second dielectric structure 17 on the substrate 100 .
[0100] In the present application embodiment, Figure 1 and Figure 3 As shown, the second gate dielectric layer 19 is disposed on the inner side of the semiconductor structure 15 , that is, the second gate dielectric layer 19 conforms to the inner side of the semiconductor structure 15 , and the semiconductor structure 15 and the second gate 14 are insulated from each other by disposing the second gate dielectric layer 19 .
[0101] In the present application embodiment, Figure 1 and Figure 3 As shown, the second gate dielectric layer 19 surrounds the outer side of the second gate 14 .
[0102] Optionally, in one embodiment of the present application, the first gate 13 is electrically connected to the second gate 14 .
[0103] In the embodiment of the present application, the first gate 13 is electrically connected to the second gate 14. When the first gate 13 and the second gate 14 are powered on, the first gate 13 and the second gate 14 can be connected to the same electrical signal, so that the first gate 13 and the second gate 14 can generate the same electric field, which can ensure that the outer side and the inner side of the semiconductor structure 15 are subjected to the same electric field, which helps to increase the concentration of carriers in the channel region of the semiconductor structure 15, thereby helping to improve the switching current ratio of the field effect tube and ensure the performance of the field effect tube.
[0104] Optionally, in one embodiment of the present application, the semiconductor structure 15 includes a metal oxide semiconductor material.
[0105] In the embodiment of the present application, the semiconductor structure 15 is manufactured by using a metal oxide semiconductor material. Compared with related non-metallic semiconductor materials, the metal oxide semiconductor material has a higher electron mobility, which helps to further reduce the size of the field effect transistor.
[0106] In some embodiments, the metal oxide semiconductor material or the material of the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific details can be adjusted according to the actual situation.
[0107] These materials have a wider band gap and a lower leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is smaller, thereby improving the operating performance of the dynamic memory.
[0108] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.
[0109] In the present application, the first gate and the second gate are both gates. In an exemplary embodiment, the gate material may be one or more of the following different types of materials.
[0110] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; or it may be a metal alloy containing the aforementioned metals.
[0111] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as tin-doped indium oxide ITO, indium-doped zinc oxide IZO, indium oxide InO, aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), ruthenium oxide (RuOx) and other metal oxide conductive materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other metal nitride materials.
[0112] Based on the same inventive concept, an embodiment of the present application provides a memory, including a field effect transistor provided in any of the above embodiments.
[0113] In the embodiments of the present application, since the memory adopts any one of the field effect transistors provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be described in detail here.
[0114] Optionally, in the embodiment of the present application, the memory includes RAM (Random Access Memory), ROM (Read-Only Memory), etc.
[0115] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which includes: any memory provided in the above embodiments.
[0116] In the embodiments of the present application, since the electronic device adopts any one of the memories provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be described in detail here.
[0117] Optionally, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.
[0118] It should be noted that electronic devices are not limited to the above-mentioned ones. Those skilled in the art can set any one of the memories provided in the above-mentioned embodiments of the present application in different devices according to actual application requirements, so as to obtain the electronic device provided in the embodiments of the present application.
[0119] Those skilled in the art will appreciate that the electronic devices provided in the embodiments of the present application may be specially designed and manufactured for the desired purpose, or may also include known devices in general-purpose computers. These devices have any memory provided in the above embodiments.
[0120] Based on the same inventive concept, the present application embodiment provides a method for manufacturing a field effect transistor, and the flow chart of the manufacturing method is as follows Figure 4 As shown, the method includes steps S401 to S407.
[0121] S401 , forming a first electrode 11 , a first dielectric layer 102 , a first conductive layer 103 , a second dielectric layer 104 and a second conductive layer 105 in sequence on one side of a substrate.
[0122] S402, based on the patterning process, a first hole 107 is formed from top to bottom in the second conductive layer 105, the second dielectric layer 104 and the first conductive layer 103; the sidewalls of the first hole 107 are the first conductive structure 1031 formed by the stacked first conductive layer 103, the second dielectric structure 17 formed by the second dielectric layer 104 and the second electrode 12 formed by the second conductive layer 105.
[0123] S403 , performing an etching back process on the first conductive structure 1031 exposed on the inner sidewall of the first hole 107 to form a groove, and the first conductive structure 1031 after etching back forms a first gate 13 .
[0124] S404 , etching the first dielectric layer 102 to expose a portion in the first hole 107 , so that at least a portion of the first electrode 11 is exposed. The etched first dielectric layer 102 forms a first dielectric structure 16 .
[0125] S405 , forming a first gate dielectric layer 18 in the groove.
[0126] S406 , forming a semiconductor structure 15 covering the inner wall of the first hole 107 , and the semiconductor structure encloses the second hole 110 .
[0127] S407 , forming a second gate dielectric layer 19 and a second gate 14 in sequence on the inner sidewall of the second hole 110 .
[0128] In the method for manufacturing a field effect transistor provided in an embodiment of the present application, a first annular gate 13 is formed on the outer side of a semiconductor structure 15, and a columnar second gate 14 is formed on the inner side of the semiconductor structure 15, so that the semiconductor structure 15 can be simultaneously affected by the electric field applied by the first gate 13 and the second gate 14, which can significantly reduce the influence of the short channel effect, help to improve the switching current ratio of the manufactured field effect transistor, ensure the performance of the field effect transistor, and at the same time, help to further reduce the size of the field effect transistor.
[0129] In order to facilitate readers to intuitively understand the manufacturing method of the field effect transistor provided in the embodiment of the present application and the advantages of the manufacturing method, the following will be combined with Figure 5-Figure 16 A memory manufacturing method is described in detail.
[0130] Optionally, in an embodiment of the present application, before the above step S401 , the method further includes: forming a fourth dielectric layer 101 on one side of the substrate 100 .
[0131] Optionally, a fourth dielectric layer 101 is formed on one side of the substrate 100 based on a deposition process.
[0132] Optionally, the deposition process includes CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition), and the like.
[0133] Optionally, in an embodiment of the present application, the step S401 includes: sequentially forming a first electrode 11, a first dielectric layer 102, a first conductive layer 103, a second dielectric layer 104 and a second conductive layer 105 on one side of the substrate 100 based on a deposition process.
[0134] Optionally, a conductive material is deposited on one side of the substrate 100 to form a conductive film layer, and then the conductive film layer is processed based on a patterning process to form the first electrode 11, such as Figure 5 shown.
[0135] Optionally, in the embodiment of the present application, the conductive material forming the first electrode 11 includes metal materials such as Ti (titanium), Mo (molybdenum) and W (tungsten).
[0136] Optionally, after forming the first electrode 11 on one side of the substrate 100, the method includes: forming a first dielectric layer 102 covering the first electrode 11 based on a deposition process; forming a first conductive layer 103 on a side of the first dielectric layer 102 away from the substrate 100 based on a deposition process and a patterning process; forming a second dielectric layer 104 covering the first conductive layer 103 based on a deposition process; forming a second conductive layer 105 on a side of the second dielectric layer 104 away from the substrate 100 based on a deposition process and a patterning process, such as Figure 6 shown.
[0137] Optionally, forming the first dielectric layer 102 covering the first electrode 11 based on a deposition process includes: planarizing the first dielectric layer 102 based on a CMP (Chemical Mechanical Polishing) process.
[0138] Optionally, forming the second dielectric layer 104 covering the first conductive layer 103 based on a deposition process includes: planarizing the second dielectric layer 104 based on a CMP process.
[0139] Optionally, in the embodiment of the present application, under the same etching conditions, the etching rate of the material made of the first dielectric layer 102 is greater than the etching rate of the material made of the second dielectric layer 104 .
[0140] Optionally, in an embodiment of the present application, after the above step S401 and before the above step S402 , the process further includes: forming a third dielectric layer 106 on a side of the second conductive layer 105 away from the substrate 100 .
[0141] Optionally, in the embodiment of the present application, after forming the second conductive layer 105 on the side of the second dielectric layer 104 away from the substrate 100 based on the deposition process and the patterning process, the method further includes: forming a third dielectric layer 106 covering the second conductive layer 105 based on the deposition process, and planarizing the third dielectric layer 106 based on the CMP process, such as Figure 7 shown.
[0142] Optionally, in the embodiment of the present application, the manufacturing material of the third dielectric layer 106 is the same as the manufacturing material of the first dielectric layer 102 , that is, under the same etching conditions, the etching rate of the first dielectric layer 102 and the third dielectric layer 106 is greater than the etching rate of the second dielectric layer 104 .
[0143] Optionally, in one embodiment of the present application, after forming the third dielectric layer 106, the above step S402 includes: processing the third dielectric layer 106 and the second conductive layer 105 based on a patterning process, the patterned third dielectric layer 106 forms a third dielectric structure 1061, the patterned second conductive layer 105 forms a second conductive structure 1051, and the third dielectric structure 1061 and the second conductive structure 1051 both include interconnected vias, such as Figure 8 shown.
[0144] Optionally, the third dielectric layer 106 is processed based on a patterning process including photoresist coating, exposure and development, and etching to form a third dielectric structure 1061 including a via hole, and then the second conductive layer 105 is etched based on the third dielectric structure 1061 as a mask to form a second conductive structure 1051 including a via hole, such as Figure 8 As shown, the via holes of the third dielectric structure 1061 are connected to the via holes of the second conductive structure 1051 , and the via holes of the third dielectric structure 1061 and the via holes of the second conductive structure 1051 have the same aperture.
[0145] Optionally, in an embodiment of the present application, after forming the third dielectric structure 1061 and the second conductive structure 1051 , the method further includes: performing back etching on the sidewall of the second conductive structure 1051 exposed in the via hole to form the second electrode 12 .
[0146] Optionally, the sidewall of the second conductive structure 1051 exposed at the via hole is etched back to form a third conductive structure 1502, such as Fig. 9 shown.
[0147] Alternatively, if Fig. 9 As shown, the sidewall of the third conductive structure 1502 facing the via hole is laterally retracted relative to the sidewall of the third dielectric structure 1061 facing the via hole, so that the aperture of the via hole of the third conductive structure 1502 is larger than the aperture of the via hole of the third dielectric structure 1061 .
[0148] like Fig. 9 As shown, the distance between the sidewall of the third conductive structure 1502 facing the via hole and the sidewall of the third dielectric structure 1061 facing the via hole is a first distance d1, that is, the sidewall of the third conductive structure 1502 is retracted by d1 relative to the sidewall of the third dielectric structure 1061. Optionally, the first distance d1 is greater than 0 nanometers and not greater than 5 nanometers.
[0149] Optionally, in an embodiment of the present application, the material of the second dielectric layer 104 includes silicon nitride, which has a dense structure, thereby preventing the second dielectric layer 104 from being etched during the etching of the second conductive layer 105 and the etching of the second conductive structure 1051, thereby protecting the first conductive layer 103.
[0150] Optionally, in one embodiment of the present application, after etching back the second conductive structure 1051 to form the third conductive structure 1052, the process further includes: using the third dielectric structure 1061 as a mask, etching the second dielectric layer 104 and the first conductive layer 103 to respectively form the second dielectric structure 17 and the first conductive structure 1031, and the interconnected vias of the second dielectric structure 17, the first conductive structure 1031, the third dielectric structure 1061 and the third conductive structure 1052 form the first hole 107.
[0151] Optionally, in the embodiment of the present application, since the materials of the second dielectric layer 104 and the first conductive layer 103 are different from the material of the third dielectric structure 1061, the morphology of the third dielectric structure 1061 is retained during the etching of the second dielectric layer 104 and the first conductive layer 103, so that the third dielectric structure 1061 can be used as a hard mask, and the setting of a photoresist-based mask can be avoided, thereby simplifying the manufacturing process of the field effect transistor, reducing the difficulty of manufacturing the field effect transistor, and further reducing the manufacturing cost of the field effect transistor.
[0152] Alternatively, if Fig.10 As shown, the second dielectric structure 17 including vias is formed after etching the second dielectric layer 104, the first conductive structure 1031 including vias is formed after etching the first conductive layer 103, the vias of the third dielectric structure 1061, the vias of the third conductive structure 1502, the vias of the second dielectric structure 17 and the vias of the first conductive structure 1031 are connected to form a first hole 107, and the axial direction of the first hole 107 is perpendicular to the substrate 100.
[0153] Optionally, in one embodiment of the present application, the step S403 includes: performing a back etching process on the first conductive structure 1031 exposed on the inner side wall of the first hole 107 to form the first gate 13, so that the side wall of the first gate 13 is laterally retracted relative to the side wall of the second dielectric structure 17, so that the second dielectric structure 17, the first gate 13 and the first dielectric layer 102 are surrounded to form a lateral groove, such as Fig.11 shown.
[0154] Alternatively, if Fig.11 As shown, since the first conductive structure 1031 and the third conductive structure 1502 are both made of metal materials, during the process of etching back the first conductive structure 1031, the third conductive structure 1502 will also be etched back to form the second electrode 12. That is, after etching back the first conductive structure 1031, the sidewall of the first hole 107 includes the first gate 13, the second dielectric structure 17, the second electrode 12 and the third dielectric structure 1061 stacked in sequence.
[0155] Alternatively, if Fig.11 As shown, the distance between the sidewall of the second electrode 12 facing the via hole and the sidewall of the third dielectric structure 1061 facing the via hole is a second distance d2, that is, the sidewall of the second electrode 12 is retracted by d2 relative to the sidewall of the third dielectric structure 1061. Optionally, the second distance d2 is greater than 0 nanometers and not greater than 10 nanometers.
[0156] Alternatively, if Fig.11 As shown, the distance between the sidewall of the first gate 13 facing the via hole and the sidewall of the third dielectric structure 1061 facing the via hole is a third distance d3, that is, the sidewall of the first gate 13 is retracted by d3 relative to the sidewall of the third dielectric structure 1061. Optionally, the third distance d3 is greater than 0 nanometers and not greater than 5 nanometers.
[0157] Optionally, in one embodiment of the present application, the step S404 includes: etching the first dielectric layer 102 to expose the portion in the first hole 107, so that at least a portion of the first electrode 11 is exposed, and the first dielectric layer 102 after etching forms a first dielectric structure 16, such as Fig.12 shown.
[0158] Optionally, in the embodiment of the present application, since the materials of the third dielectric structure 1061 and the first dielectric layer 102 are both silicon oxide, during the etching process of the first dielectric layer 102, part of the third dielectric structure 1061 will also be etched away. Fig.12 As shown, the third dielectric structure 1061 is etched to form a fourth dielectric structure 1062; since the material of the second dielectric structure 17 includes silicon nitride, which has a dense structure, the second dielectric structure 17 is difficult to be etched during the etching of the third dielectric structure 1061 and the first dielectric layer 102. Therefore, during the etching of the first dielectric layer 102, the second dielectric structure 17 acts as a hard mask.
[0159] Optionally, after etching, the first dielectric layer 102 forms a first dielectric structure 16, and the first dielectric structure 16 includes a via hole, such as Fig.12 As shown, the via hole of the first dielectric structure 16 , the via hole of the first gate 13 , the via hole of the second dielectric structure 17 and the via hole of the second electrode 12 are connected to form a third hole 108 , and the axial direction of the third hole 108 is perpendicular to the substrate 100 .
[0160] Alternatively, if Fig.12 As shown, the sidewall of the third hole 108 includes a first dielectric structure 16 , a first gate 13 , a second dielectric structure 17 and a second electrode 12 stacked in sequence.
[0161] Alternatively, if Fig.12 As shown, the second dielectric structure 17 , the first gate 13 and the first dielectric structure 16 formed after etching the first dielectric layer 102 are enclosed to form a lateral groove, and the opening of the lateral groove faces the third hole 108 .
[0162] Optionally, in one embodiment of the present application, the above step S405 includes: forming a first gate dielectric layer 18 in the lateral groove. Specifically, the following steps are included:
[0163] First, a high-K dielectric material is deposited in the third hole 108 by a deposition process to form a fifth dielectric layer 109. Fig.13 As shown, the fifth dielectric layer 109 conforms to the inner sidewall of the third hole 108 , so that the fifth dielectric layer 109 completely covers the inner sidewall of the third hole 108 .
[0164] Next, the fifth dielectric layer 109 is etched away except for the portion located in the lateral groove, so as to form the first gate dielectric layer 18 located in the lateral groove. Fig.14 shown.
[0165] Alternatively, if Fig.14As shown, due to the covering protection of the second dielectric structure 17, in the subsequent process, the portion of the fifth dielectric layer 109 located in the lateral groove is retained, thereby forming a first gate dielectric layer 18, and the side walls of the first gate dielectric layer 18 facing the third hole 108 are coplanar with the side walls of the second dielectric structure 17 and the side walls of the first dielectric structure 16, thereby helping to ensure the formation of the subsequent semiconductor structure 15.
[0166] Optionally, in the embodiment of the present application, after etching the fifth dielectric layer 109 to form the first gate dielectric layer 18 , the process further includes: performing an annealing operation.
[0167] Optionally, the temperature of the annealing operation is not less than 300°C (degrees Celsius) and not more than 400°C, the time of the annealing operation is not less than 30 minutes and not more than 60 minutes, and the annealing operation is carried out in a forming gas atmosphere to repair the etching damage of the first dielectric structure 16 and the second dielectric structure 17, which is beneficial to ensure the performance of the subsequently formed field effect transistor.
[0168] Optionally, in one embodiment of the present application, the step S406 includes: forming a semiconductor structure 15 covering the inner sidewall of the first hole 108, the semiconductor structure 15 enclosing the second hole 110, such as Fig.15 shown.
[0169] Optionally, in the embodiment of the present application, a semiconductor material is deposited based on a deposition process to form a semiconductor structure 15 covering the inner sidewall of the first hole 108, such as Fig.15 As shown, the semiconductor structure 15 is a hole-shaped structure, and the semiconductor structure 15 encloses a second hole 110 .
[0170] In the embodiment of the present application, a hole-shaped semiconductor structure 15 is formed in the first hole 108 , so that the outer sidewall of the semiconductor structure 15 is directly connected to both the first electrode 11 and the second electrode 12 .
[0171] Optionally, in an embodiment of the present application, the step S407 includes: sequentially forming a second gate dielectric layer 19 and a second gate 14 on the inner sidewall of the second hole 110 .
[0172] Optionally, in the embodiment of the present application, a dielectric material with a high K value is deposited on the inner sidewall of the second hole 110 based on a deposition process to form a second gate dielectric layer 19 covering the inner sidewall of the second hole 110 .
[0173] Optionally, in the embodiment of the present application, a metal material is filled in the third hole enclosed by the second gate dielectric layer 19 based on a deposition process to form a second gate 14 partially wrapped by the second gate dielectric layer 19 .
[0174] Optionally, in one embodiment of the present application, after the above step S407, it also includes: forming a sixth dielectric layer 111 covering the second gate 14 based on a deposition process; forming at least four vias in the sixth dielectric layer 111 based on a patterning process, so that the first electrode 11, the second electrode 12, the first gate 13 and the second gate 14 are exposed; and forming a connection terminal 112 in each via hole based on a deposition process.
[0175] Optionally, in the embodiment of the present application, the first electrode 11, the second electrode 12, the first gate 13 and the second gate 14 are each connected to a connection terminal 112, so as to facilitate the electrical connection of the first electrode 11, the second electrode 12, the first gate 13 and the second gate 14 with other terminals, and facilitate the electrical connection of the manufactured field effect transistor with other components.
[0176] Optionally, in the embodiment of the present application, the connection terminal 112 connected to the first gate 13 and the connection terminal 112 connected to the second gate 14 are electrically connected.
[0177] Optionally, in the embodiment of the present application, the connection terminal 112 includes multiple conductive sublayers, thereby helping to reduce the respective resistances. Optionally, the connection terminal 112 includes three conductive sublayers, the material of the outermost conductive sublayer is Ti, the material of the middle conductive sublayer is TiN (titanium nitride), and the material of the innermost conductive sublayer is W.
[0178] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:
[0179] In the field effect transistor provided in the embodiment of the present application, by setting the first gate 13 to surround the outer side of the semiconductor structure 15, and setting at least a portion of the second gate 14 to be surrounded by the semiconductor structure 15, the semiconductor structure 15 can be simultaneously affected by the electric field applied by the first gate 13 and the second gate 14, which can significantly reduce the influence of the short channel effect, help to improve the switching current ratio of the field effect transistor, can ensure the performance of the field effect transistor, and at the same time, help to further reduce the size of the field effect transistor.
[0180] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.
[0181] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the exemplary directions or positional relationships shown in the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.
[0182] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.
[0183] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0184] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.
[0185] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.
Claims
1. A field effect transistor, characterized in that: include: A semiconductor structure is arranged on one side of the substrate, and the semiconductor structure is ring-shaped; A first electrode, a first gate electrode, and a second electrode are sequentially stacked on one side of the substrate, the first gate electrode is arranged around the outer side of the semiconductor structure, and the first electrode and the second electrode are both connected to the semiconductor structure; A second gate, at least a portion of the second gate is surrounded by the semiconductor structure, and the first gate and the second gate are both insulated from the semiconductor structure.
2. The field effect transistor according to claim 1, characterized in that: The semiconductor structure is arranged on a side of the first electrode away from the substrate; The second electrode is disposed around the outer side surface of the semiconductor structure.
3. The field effect transistor according to claim 2, characterized in that: The semiconductor structure includes a connected annular portion and a bottom portion, The bottom is arranged on a side of the first electrode away from the substrate and is connected to the first electrode; the annular portion is arranged on a side of the bottom away from the substrate, the axial direction of the annular portion is perpendicular to the substrate, and at least part of the second gate is located in the space enclosed by the annular portion and the bottom; the first gate and the second electrode are arranged around the outer side surface of the annular portion.
4. The field effect transistor according to claim 1, characterized in that: Along a direction parallel to the substrate, an orthographic projection of the first gate on the second gate is located within a range of the second gate.
5. The field effect transistor according to claim 1, characterized in that: The first electrode and the second electrode are both disposed around the outer side surface of the semiconductor structure.
6. The field effect transistor according to claim 1, characterized in that: Also includes: A first dielectric structure is arranged on a side of the first electrode away from the substrate, and the first gate is arranged on a side of the first dielectric structure away from the substrate; The second dielectric structure is arranged on a side of the first gate away from the substrate, and the second electrode is arranged on a side of the second dielectric structure away from the substrate; along a direction perpendicular to the substrate, the semiconductor structure penetrates the first dielectric structure and the second dielectric structure.
7. The field effect transistor according to claim 6, characterized in that: Also includes: A first gate dielectric layer is disposed in a lateral groove formed by the first dielectric structure, the first gate and the second dielectric structure; The second gate dielectric layer is disposed on the inner side of the semiconductor structure, and the second gate dielectric layer is disposed around the outer side of the second gate.
8. The field effect transistor according to claim 1, characterized in that: The first gate is electrically connected to the second gate.
9. The field effect transistor according to claim 1, characterized in that: The semiconductor structure includes a metal oxide semiconductor material.
10. A memory, characterized in that: include: A field effect transistor as claimed in any one of claims 1 to 9.
11. A method for manufacturing a field effect transistor, characterized in that: include: Forming a first electrode, a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer in sequence on one side of the substrate; forming a first hole from top to bottom in the second conductive layer, the second dielectric layer and the first conductive layer based on a patterning process; The sidewall of the first hole is a first conductive structure formed by the first conductive layer, a second dielectric structure formed by the second dielectric layer, and a second electrode formed by the second conductive layer. Performing back etching on the first conductive structure exposed on the inner side wall of the first hole to form a groove, wherein the first conductive structure after back etching forms a first gate; Etching the portion of the first dielectric layer exposed in the first hole so that at least a portion of the first electrode is exposed, and the first dielectric layer after etching forms a first dielectric structure; a first gate dielectric layer formed in the groove; forming a semiconductor structure covering the inner sidewall of the first hole, wherein the semiconductor structure encloses a second hole; A second gate dielectric layer and a second gate are sequentially formed on the inner sidewall of the second hole.
12. The method for manufacturing a field effect transistor according to claim 11, characterized in that: Before forming a first hole from top to bottom in the second conductive layer, the second dielectric layer and the first conductive layer based on a patterning process, the method further includes: forming a third dielectric layer on a side of the second conductive layer away from the substrate; And, forming a first hole from top to bottom in the second conductive layer, the second dielectric layer and the first conductive layer based on a patterning process, comprising: Patterning the third dielectric layer and the second conductive layer to form a third dielectric structure and a second conductive structure respectively; the third dielectric structure and the second conductive structure both include interconnected vias; Performing back etching on the sidewall of the second conductive structure exposed at the via hole to form the second electrode; Using the third dielectric structure as a mask, the second dielectric layer and the first conductive layer are etched to form the second dielectric structure and the first conductive structure respectively; the second dielectric structure, the first conductive structure, the third dielectric structure and the second conductive structure are interconnected via holes to form the first hole.