SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with SBD integrated on side wall of source trench and preparation method
By integrating Schottky diodes in the source trench sidewall and introducing P shielding layer grounding in SiC MOSFET, the problems of trench corner electric field crowding effect and high power consumption are solved, and the reverse freewheeling capability and reliability of the device are improved. reduces loss.
Patent Information
- Application Number
- CN202411346588.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-26
- Publication Date
- 2024-12-17
AI Technical Summary
The trench SiC MOSFET has a trench corner electric field congestion effect, resulting in early breakdown of gate oxygen, and the Miller capacitance and gate charge are large, which increases power consumption and cost. At the same time, the reliability of SiC body diodes is reduced under bipolar stress. Continued High current loss.
The Schottky diode is integrated on the side wall of the source trench and grounded with the source through the P shielding layer, and a shielded gate structure is introduced to reduce the gate leakage capacitance and improve the reverse freewheeling capability and reliability of the device.
Reduces the reverse freewheeling loss and switching loss of the device, improves the reverse conduction capability and gate oxygen reliability, reduces the on-resistance, and avoids the bipolar degradation effect of the body diode.
Smart Images
Figure CN119153525A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a power semiconductor device, and in particular to a SiC MOSFET with a source trench sidewall integrated with a SBD and a preparation method thereof. Background Art
[0002] Silicon carbide materials have wider bandgap, higher critical electric field, higher carrier saturation drift velocity, higher thermal conductivity and other advantages compared to silicon materials. They are excellent materials for preparing high-voltage power electronic devices and have broad application prospects in the fields of high-power, high-temperature, high-voltage and radiation-resistant power electronics. SiC MOSFET is a unipolar device with good reverse recovery characteristics and low switching losses. It is widely used in new energy equipment and various consumer electronics fields and is a core device of electronic power systems. Compared with planar SiC MOSFET, trench SiC MOSFET devices can achieve smaller cell sizes, making chip costs lower and have better application prospects.
[0003] However, trench SiC MOSFET has certain problems due to its own structural characteristics. On the one hand, the formation of the trench is limited by the process level, the etching method affects the roughness of the side wall surface, and the etching angle determines the channel crystal plane and the gate groove corner, which further affects the channel mobility and gate oxide reliability. In the blocking state, there is an electric field crowding effect at the trench corner, which makes the gate oxide electric field peak far exceed the critical breakdown electric field of the SiO2 material, making it easier to cause the device gate oxide to break down prematurely. In order to alleviate the electric field crowding effect at the trench corner, a P-type shielding layer is introduced at the bottom of the trench after the gate groove is etched. The electric field peak of the device during breakdown is transferred from the gate oxide layer to the PN junction formed by the P-type shielding layer and the N-type drift region, which improves the gate oxide reliability. There are two methods for the P-type shielding layer: floating and grounding. Grounding the P-type shielding layer can more effectively improve the gate oxide reliability, but the process is often difficult to achieve. On the other hand, the Miller capacitance (C gd ) and gate charge (Q gd ) is large, resulting in higher power consumption of the device in high-frequency and high-power applications, which will greatly increase the cost of using the device.
[0004] In addition, SiC MOSFET often needs to use body diodes for freewheeling in applications, but the SiC MOSFET body diode will produce bipolar degradation effect under bipolar stress, which reduces the reliability of the device. At the same time, due to the wide bandgap of SiC materials, the turn-on voltage of the device body diode is high, which makes the device's freewheeling loss high. In practical applications, freewheeling can be achieved by using anti-parallel Schottky diodes, but the cost of external Schottky diodes is high, and the parasitic inductance caused by the bonding wires is large, which limits the high-frequency and high-efficiency applications of the device. Summary of the invention
[0005] The purpose of the present invention is to provide a SiC MOSFET with an integrated SBD on the sidewall of a source trench and a preparation method thereof, wherein a P shielding layer is in contact with the source trench to optimize the disadvantage that a traditional shielding layer is difficult to be grounded, and a Schottky diode SBD is integrated on the sidewall of the source trench to improve the reverse freewheeling capability of the device, and a grounded shielding gate structure is used to shield the capacitive coupling between the gate and the drain, thereby reducing the gate-drain capacitance and reducing the switching loss.
[0006] In order to achieve the above object, the present invention adopts the following technical solution: In a first aspect, the present invention provides a method for preparing a SiC MOSFET with a source trench sidewall integrated SBD, comprising: S1, preparing a SiC substrate, growing an epitaxial layer on the surface of the SiC substrate, and forming an N buried layer and a symmetrical P shielding layer on the surface of the epitaxial layer; S2, continuing to grow an epitaxial layer on the surface of the epitaxial layer processed by S1, and sequentially generating a current spreading layer, a Pwell region and an N+ region on the upper surface of the epitaxial layer; S3, etching the surface of the epitaxial layer processed by S2 to form a source trench and a gate trench, wherein the gate trench is located at the center of the epitaxial layer, and after etching the gate trench, a symmetrical Pwell region and a symmetrical N+ region are formed on the surface of the epitaxial layer, and the source trench is located on both sides of the epitaxial layer, and is symmetrical between the left and right sides; S4, performing oxide deposition and polysilicon deposition on the bottom and sidewalls of the gate trench to form a shielding gate and a gate; S5, depositing metal at the bottom, sidewall and N+ region of the source trench to form a source, and making the source metal form an ohmic contact with the N+ region, the Pwell region and the P shielding region, and at the same time form a Schottky contact with the current spreading layer; S6. Generate a drain.
[0007] Preferably, the specific implementation process of S1 includes: Selecting an N-type doped 4H-SiC substrate, and growing an epitaxial layer on the 4H-SiC substrate by a MOCVD homoepitaxial method; After cleaning, gluing, photolithography and development, high-energy ions are symmetrically implanted on the left and right sides of the epitaxial layer to form a symmetrical P shielding layer; and high-energy ions are implanted at the center of the epitaxial layer surface to form an N buried layer of equal thickness between the symmetrical P shielding layers; The doping element of the 4H-SiC substrate is nitrogen or phosphorus, and the doping concentration is 1×10 18 ~1×10 20 cm -3, thickness is 10-12um, width is 2-6um; The doping element of the epitaxial layer is nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 16 cm -3 , thickness is 6-15um, width is 2-6um; The P shielding layer is P-type doped, the doping element is aluminum or boron, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , thickness is 0.2-0.5um, width is 1-1.4um; The N buried layer is N-type doped, the doping element is nitrogen or phosphorus, and the doping concentration is 1×10 17 ~1×10 20 cm -3 , thickness is 0.2-0.5um, width is 0.1-0.4um.
[0008] Preferably, the specific implementation process of S2 includes: The epitaxial layer is further grown on the surface of the epitaxial layer treated with S1 by depositing SiC. After cleaning, gluing, photolithography and development, a current spreading layer is generated on the upper surface of the P shielding layer by high energy ion implantation; Using high energy ion implantation from the upper surface of the epitaxial layer, a Pwell region of equal width is generated on the upper surface of the current spreading layer; Using high energy ion implantation from the upper surface of the epitaxial layer, an N+ region of equal width is generated on the upper surface of the Pwell region; The doping element of the continuously growing epitaxial layer is nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 16 cm -3 , thickness is 1-3um, width is 2-6um; The CSL layer is N-type doped, the doping element is nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 16 cm -3 , thickness is 0.1-1um, width is 2-6um; The Pwell region is P-type doped, the doping element is aluminum or boron, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , thickness is 0.2-1um, width is 2-6um; The N+ region is N-type doped, the doping element is nitrogen or phosphorus, and the doping concentration is 1×1018 ~1×10 20 cm -3 , thickness is 0.2-0.4um, width is 2-6um.
[0009] Preferably, the specific implementation process of S3 includes: Cleaning, gluing, photolithography and developing the epitaxial layer after S2 treatment, using photoresist to protect the non-etched area, and etching on the surface of the epitaxial layer to form source trenches and gate trenches; The gate trench is etched downward from the center of the epitaxial layer, and the bottom of the gate trench does not contact the N buried layer, the etching width is 0.2-1um, and the thickness is 1-3um; after etching the gate trench, a symmetrical Pwell region and a symmetrical N+ region are formed on the surface of the epitaxial layer; The source trench is etched symmetrically downward from the left and right sides of the epitaxial layer, and it is ensured that the source trench is in direct contact with the P shielding layer. The etching width is 0.3-0.5um and the thickness is 1.2-3.2um.
[0010] Preferably, the specific implementation process of S4 includes: Depositing oxide on the bottom and sidewalls of the gate trench, wherein the thickness of the oxide deposited on the bottom of the trench is 0.05um-0.1um, and the thickness of the oxide deposited on the sidewalls of the trench is 0.05um-0.15um; Then, the first step of polysilicon deposition is performed on the gate trench to form a shield gate, and the deposition thickness is 0.2um-1um; Continue to perform oxide deposition on the gate trench, the oxide layer deposited at the bottom of the trench has a thickness of 0.05um-0.1um, and the oxide layer deposited on the sidewall has a thickness of 0.05um; Then, a second polysilicon deposition is performed on the gate trench to form a gate, and the deposition thickness is 0.6um-1um; Finally, oxide deposition is performed on the gate to make the deposited oxide layer flush with the surface of the epitaxial layer.
[0011] Preferably, in S5, Titanium metal is selected as the metal for source trench deposition.
[0012] In a second aspect, the present invention provides a SiC MOSFET with a source trench sidewall integrated with an SBD, which is manufactured using the above-mentioned method for manufacturing a SiC MOSFET with a source trench sidewall integrated with an SBD.
[0013] The beneficial effects of the present invention are: (1) The present invention provides a SiC MOSFET with an SBD integrated on the sidewall of a source trench and a preparation method thereof. By integrating a Schottky diode (SBD) on the sidewall of the source trench, the Schottky metal is connected to the source. In the reverse freewheeling state, the SBD with a lower turn-on voltage is turned on first, thereby improving the reverse conduction capability of the device, while also reducing the freewheeling loss and reverse recovery loss, thereby effectively avoiding the bipolar degradation effect caused by the turn-on of the body diode.
[0014] (2) The SiC MOSFET prepared by the present invention uses a deep source trench to set a P shielding layer for grounding, thereby alleviating the electric field crowding effect at the trench corner and improving the gate oxide reliability.
[0015] (3) The SiC MOSFET prepared by the present invention introduces a shielded gate structure, which is connected to the source metal to achieve the effect of zeroing the shielded gate potential, while shielding the capacitive coupling between the gate and the drain, thereby reducing the gate-drain capacitance and reducing switching losses.
[0016] (4) The SiC MOSFET prepared by the present invention adds a current expansion layer and an N buried layer to alleviate the JFET effect caused by the P shielding layer, thereby reducing the device on-resistance and increasing the output current. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 It is a flow chart of manufacturing a SiC MOSFET device with a source trench sidewall integrated SBD provided by the present invention; Figure 2 It is a schematic structural diagram of a SiC MOSFET device with a source trench sidewall integrated SBD provided by the present invention after an N buried layer and a P shielding layer are prepared; Figure 3 It is a schematic structural diagram of the SiC MOSFET device with integrated SBD on the sidewall of the source trench provided by the present invention after the CSL layer, the Pwell region and the N+ region are prepared; Figure 4 It is a schematic structural diagram of a SiC MOSFET device with a source trench sidewall integrated SBD provided by the present invention after etching the source trench and the gate trench; Figure 5 It is a schematic structural diagram of the SiC MOSFET device with integrated SBD on the sidewall of the source trench provided by the present invention after preparing the shielding gate and the gate; Figure 6 It is a schematic structural diagram of a SiC MOSFET device with a source trench sidewall integrated SBD provided by the present invention after preparation; Figure 7 It is a schematic diagram of the forward conduction working mechanism of the SiC MOSFET device with integrated SBD on the sidewall of the source trench provided by the present invention; Figure 8 It is a schematic diagram of the reverse freewheeling state of the SiC MOSFET device with the source trench sidewall integrated SBD provided by the present invention. DETAILED DESCRIPTION
[0018] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.
[0019] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0020] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0021] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.
[0022] The specific embodiments of the present invention are described in further detail below in conjunction with the accompanying drawings. The following examples are used to illustrate the present invention but are not intended to limit the scope of the present invention.
[0023] In a first aspect, the present invention provides a method for preparing a SiC MOSFET with a source trench sidewall integrated SBD, such as Figure 1 As shown, the following steps are included: S100, preparing a SiC substrate, and generating an epitaxial layer on the SiC substrate by a MOCVD homoepitaxial method; then, forming an N buried layer and a symmetrical P shielding layer on the epitaxial layer by high energy ion implantation.
[0024] S200, further growing an epitaxial layer by depositing SiC, and sequentially generating a current spreading layer (CSL), a Pwell region, and an N+ region by high-energy ion implantation.
[0025] S300, etching is performed on the surface of the epitaxial layer processed in S200 to form a source trench and a gate trench. The gate trench is located at the center of the epitaxial layer. After etching the gate trench, a symmetrical Pwell region and a symmetrical N+ region are formed on the surface of the epitaxial layer. The source trench is located on both sides of the epitaxial layer, and is symmetrical.
[0026] S400, performing oxide deposition on the bottom and sidewalls of the gate trench, and performing polysilicon deposition in the trench to form a shielding gate.
[0027] S500, continuing to deposit an oxide layer and polysilicon in the gate trench processed in S400 to form a gate, and finally performing oxide deposition to make the deposited oxide layer flush with the upper surface of the epitaxial layer.
[0028] S600, depositing metal on the bottom, sidewall and N+ region of the source trench to form a source, while ensuring that the source metal forms an ohmic contact with the N+ region, Pwell region and P shielding region, and forms a Schottky contact with the current spreading layer. Titanium metal is generally used as the metal of the Schottky diode.
[0029] S700, forming a drain electrode by externally connecting a metal electrode to the substrate.
[0030] In the present invention, the specific implementation process of step S100 is as follows: S110, the substrate is selected as N-type doped 4H-SiC, the doping element is nitrogen or phosphorus, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , thickness is 10-12um, width is 2-6um; Preferably, the doping element is nitrogen, and the doping concentration is 1×10 18 cm -3 , thickness is 10um, width is 3um; N-type doped 4H-SiC was grown on a 4H-SiC substrate by MOCVD homoepitaxial method. The doping element was nitrogen or phosphorus, and the doping concentration was 1×10 15 ~1×10 16 cm -3 , thickness is 6-15um, width is 2-6um; Preferably, the doping element is nitrogen, and the doping concentration is 6.5×10 15 cm -3, thickness is 11um and width is 3um.
[0031] S120, cleaning, gluing, photolithography, and developing the epitaxial wafer, and using high-energy ion implantation to form a P shielding layer and an N buried layer, see Figure 2 , The P shielding layer is P-type doped, and high-energy ions are implanted symmetrically from the upper surface of the epitaxial layer to form a bilaterally symmetrical P shielding layer. The doping element is aluminum or boron, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , thickness is 0.2-0.5um, width is 1-1.4um; Preferably, aluminum is used for doping, and the doping concentration is 2×10 18 cm -3 , thickness is 0.5um and width is 1.35um.
[0032] The N buried layer is N-type doped. High-energy ion implantation is used from the center point of the epitaxial layer to form an N buried layer between the symmetrical P shielding layers. The thickness is the same as that of the P shielding layer. The doping element is nitrogen or phosphorus, and the doping concentration is 1×10 17 ~1×10 20 cm -3 , thickness is 0.2-0.5um, width is 0.1-0.4um; Preferably, nitrogen is used for doping, and the doping concentration is 1×10 17 cm -3 , thickness is 0.5um and width is 0.3um.
[0033] In the present invention, the specific implementation process of step S200 is as follows: S210, depositing another SiC epitaxial layer on the surface of the epitaxial layer treated by S100 by a SiC deposition method, wherein the doping element is nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 16 cm -3 , thickness is 1-3um, width is 2-6um; Preferably, the doping element is nitrogen, and the doping concentration is 6.5×10 15 cm -3 , thickness is 1.8um and width is 3um.
[0034] S220, after the epitaxial wafer is cleaned, coated, photolithographically processed and developed, high-energy ion implantation is used to sequentially form a current expansion layer, a Pwell region and an N+ region. For details, see Figure 3 , The CSL layer is N-type doped, and high-energy ions are implanted from the upper surface of the epitaxial layer to generate a current spreading layer on the upper surface of the P shielding layer. The doping element is nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 16 cm -3 , thickness is 0.1-1um, width is 2-6um; Preferably, nitrogen is used for doping, and the doping concentration is 1×10 16 cm -3 , thickness is 1um and width is 3um.
[0035] The Pwell region is P-type doped. High-energy ion implantation is used from the upper surface of the epitaxial layer to generate a Pwell region of equal width on the upper surface of the current spreading layer. The doping element is aluminum or boron, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , thickness is 0.2-1um, width is 2-6um; Preferably, the doping element is aluminum, and the doping concentration is 1×10 19 cm -3 , thickness is 0.5um and width is 3um.
[0036] The N+ region is N-type doped. High-energy ion implantation is used from the upper surface of the epitaxial layer to generate an N+ region of equal width on the upper surface of the Pwell region. The doping element is nitrogen or phosphorus, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , thickness is 0.2-0.4um, width is 2-6um; Preferably, the doping element is nitrogen, and the doping concentration is 1×10 19 cm -3 , thickness is 0.3um and width is 3um.
[0037] It should be noted that the internal structure and preparation process of epitaxial wafers are common in the industry and there are no special requirements.
[0038] In the present invention, the specific implementation process of step S300 is as follows: The epitaxial wafer treated by S200 is cleaned, coated, photolithographically processed, and developed. The non-etched area is protected by photoresist, and then the groove is etched.
[0039] The gate trench is etched downward from the center of the epitaxial layer, and it is ensured that the bottom of the gate trench does not contact the N buried layer. The etching width is 0.2-1um and the thickness is 1-3um. After etching the gate trench, a symmetrical Pwell region and a symmetrical N+ region are formed on the surface of the epitaxial layer. Figure 4 shown.
[0040] Preferably, the etching thickness is 1.55 um and the width is 1 um.
[0041] The source trench is etched symmetrically downward from the left and right sides of the epitaxial layer, and the source trench is ensured to be in direct contact with the P shielding layer to facilitate the grounding of the P shielding layer. Figure 4 As shown; the etching width is 0.3-0.5um and the thickness is 1.2-3.2um.
[0042] Preferably, the etching thickness is 1.8 um and the width is 0.5 um.
[0043] In the present invention, the specific implementation process of step S400 is as follows: The epitaxial wafers processed by S300 are cleaned, coated, photolithographically processed and developed, and oxide and polysilicon are deposited on the gate trenches. See Figure 5 , oxide deposition is performed on the bottom and sidewalls of the gate trench, the oxide thickness deposited at the bottom of the trench is 0.05um-0.1um, and the oxide thickness deposited on the sidewalls of the trench is 0.05um-0.15um; Preferably, the thickness of the oxide deposited on the bottom of the trench is 0.05 um, and the thickness of the oxide deposited on the sidewall of the trench is 0.15 um; Then the first step of polysilicon (Poly Si) deposition is performed on the gate trench to form a shield gate, such as Figure 5 As shown; the deposition thickness is 0.2um-1um.
[0044] Preferably, the deposited Poly Si has a thickness of 0.3 um and a width of 0.7 um.
[0045] In the present invention, the specific implementation process of step S500 is as follows: Continue to deposit oxide on the gate trench, the oxide layer thickness deposited at the bottom is 0.05um-0.1um, and the oxide thickness deposited on the sidewall is 0.05um; Then, a second Poly Si deposition is performed on the gate trench to form a gate. Figure 5 As shown; the deposition thickness is 0.6um-1um.
[0046] Preferably, the deposition thickness is 0.8 um and the width is 0.9 um.
[0047] Finally, the oxide deposition on the gate is performed to be flush with the epitaxial layer, such as Figure 5 shown.
[0048] In the present invention, the specific implementation process of step S600 is as follows: Metal is deposited on the bottom, sidewalls and top of the source trench to form the source, ensuring that the source metal forms an ohmic contact with the N+ region, Pwell region and P shielding region, and forms a Schottky contact with the current spreading layer. Titanium metal is generally used as the metal of the Schottky diode. For details, see Figure 6 .
[0049] In the present invention, the specific implementation process of step S700 is as follows: A drain electrode is formed at the bottom of the substrate, wherein a drain electrode ohmic contact metal is provided in the drain electrode. Figure 6 .
[0050] From the above, it can be seen that the novel trench SiC MOSFET structure proposed in the present invention adopts a P shielding layer to reduce the high gate oxide electric field strength at the bottom corner of the gate, thereby improving the reliability of the device; adopts a current expansion layer and an N buried layer to reduce the on-resistance of the device and improve the forward conduction characteristics; adopts a shielded gate structure, which is connected to the source potential, forms a source-drain parasitic capacitance with the source, reduces the gate-drain capacitance, and reduces the switching loss; adopts a Schottky diode integrated on the sidewall of the source trench, which is short-circuited with the source, and in the reverse conduction state, reduces the reverse turn-on voltage of the device, suppresses the turn-on of the device body diode, avoids the bipolar degradation effect of the device, and improves the reverse recovery ability of the device.
[0051] Depend on Figure 7 It can be seen that when the gate voltage V G Greater than the turn-on voltage V th , the inversion layer channel is turned on, the device is forward-conducting, and electrons flow from the N+ region through the side channel of the Pwell region to the current expansion layer, N buried layer and N-drift drift region, and are finally collected by the drain. By adding the current expansion layer and N buried layer, the on-resistance is reduced. At this time, the Schottky junction is in a reverse bias state, and no current flows.
[0052] When zero bias is applied to the gate and high voltage is applied to the drain, the device is reversely cut off, and the P shielding layer and N-drift form a PN junction to withstand the withstand voltage. At this time, the electric field lines from the drain end are blocked by the PN formed by the P shielding layer and the N buried layer, which greatly reduces the electric field strength at the gate oxide corner and improves the gate oxide reliability of the device. When the Schottky junction is subjected to a high electric field, the barrier height will decrease, causing the leakage current to increase and the withstand voltage to decrease. In the present invention, the Pwell region, the P shielding layer and the N-type CSL layer on the side of the Schottky junction surface are mutually depleted to form a depletion region, so that the Schottky junction is protected from the influence of the high electric field.
[0053] Depend on Figure 8It can be seen that in the reverse freewheeling state, since the turn-on voltage of the SBD is lower than that of the body diode, the SBD is turned on first, and the current flows from the Schottky metal to the N-drift region and is finally collected at the drain end. The introduction of the SBD reduces the reverse conduction voltage drop of the device, thereby reducing the reverse freewheeling loss. In addition, the introduction of the SBD allows a large number of free carriers stored in the drift region of the device to be quickly extracted, improving the reverse recovery capability.
[0054] In a second aspect, the present invention provides a SiC MOSFET with a source trench sidewall integrated SBD, which is prepared by the above-mentioned preparation method, and has a structure as shown in Figure 6 shown.
[0055] Finally, it should be noted that the drawings of the embodiments disclosed in the present invention only involve the structures involved in the embodiments disclosed in the present invention, and other structures can refer to the general design; in the absence of conflict, the embodiments disclosed in the present invention and the features in the embodiments can be combined with each other to obtain new embodiments.
[0056] The above are only specific implementation methods disclosed in the present invention, but the protection scope disclosed in the present invention is not limited thereto. The protection scope disclosed in the present invention shall be based on the protection scope of the claims.
Claims
1. A method for preparing a SiC MOSFET with a source trench sidewall integrated SBD, characterized in that: include: S1, preparing a SiC substrate, growing an epitaxial layer on the surface of the SiC substrate, and forming an N buried layer and a symmetrical P shielding layer on the surface of the epitaxial layer; S2, continuing to grow an epitaxial layer on the surface of the epitaxial layer processed by S1, and sequentially generating a current spreading layer, a Pwell region and an N+ region on the upper surface of the epitaxial layer; S3, etching the surface of the epitaxial layer processed by S2 to form a source trench and a gate trench, wherein the gate trench is located at the center of the epitaxial layer, and after etching the gate trench, a symmetrical Pwell region and a symmetrical N+ region are formed on the surface of the epitaxial layer, and the source trench is located on both sides of the epitaxial layer, and is symmetrical between the left and right sides; S4, performing oxide deposition and polysilicon deposition on the bottom and sidewalls of the gate trench to form a shielding gate and a gate; S5, depositing metal at the bottom, sidewall and N+ region of the source trench to form a source, and making the source metal form an ohmic contact with the N+ region, the Pwell region and the P shielding region, and at the same time form a Schottky contact with the current spreading layer; S6. Generate a drain.
2. The method for preparing a SiC MOSFET with a source trench sidewall integrated SBD according to claim 1, characterized in that: The specific implementation process of S1 includes: Selecting an N-type doped 4H-SiC substrate, and growing an epitaxial layer on the 4H-SiC substrate by a MOCVD homoepitaxial method; After cleaning, gluing, photolithography and development, high-energy ions are symmetrically implanted on the left and right sides of the epitaxial layer to form a symmetrical P shielding layer; and high-energy ions are implanted at the center of the epitaxial layer surface to form an N buried layer of equal thickness between the symmetrical P shielding layers; The doping element of the 4H-SiC substrate is nitrogen or phosphorus, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , thickness is 10-12um, width is 2-6um; The doping element of the epitaxial layer is nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 16 cm -3 , thickness is 6-15um, width is 2-6um; The P shielding layer is P-type doped, the doping element is aluminum or boron, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , thickness is 0.2-0.5um, width is 1-1.4um; The N buried layer is N-type doped, the doping element is nitrogen or phosphorus, and the doping concentration is 1×10 17 ~1×10 20 cm -3 , thickness is 0.2-0.5um, width is 0.1-0.4um.
3. The method for preparing a SiC MOSFET with a source trench sidewall integrated SBD according to claim 2, characterized in that: The specific implementation process of S2 includes: The epitaxial layer is further grown on the surface of the epitaxial layer treated with S1 by depositing SiC. After cleaning, gluing, photolithography and development, a current spreading layer is generated on the upper surface of the P shielding layer by high energy ion implantation; Using high energy ion implantation from the upper surface of the epitaxial layer, a Pwell region of equal width is generated on the upper surface of the current spreading layer; Using high energy ion implantation from the upper surface of the epitaxial layer, an N+ region of equal width is generated on the upper surface of the Pwell region; The doping element of the continuously growing epitaxial layer is nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 16 cm -3 , thickness is 1-3um, width is 2-6um; The CSL layer is N-type doped, the doping element is nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 16 cm -3 , thickness is 0.1-1um, width is 2-6um; The Pwell region is P-type doped, the doping element is aluminum or boron, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , thickness is 0.2-1um, width is 2-6um; The N+ region is N-type doped, the doping element is nitrogen or phosphorus, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , thickness is 0.2-0.4um, width is 2-6um.
4. The method for preparing a SiC MOSFET with a source trench sidewall integrated SBD according to claim 3, characterized in that: The specific implementation process of S3 includes: Cleaning, gluing, photolithography and developing the epitaxial layer after S2 treatment, using photoresist to protect the non-etched area, and etching on the surface of the epitaxial layer to form source trenches and gate trenches; The gate trench is etched downward from the center of the epitaxial layer, and the bottom of the gate trench does not contact the N buried layer, the etching width is 0.2-1um, and the thickness is 1-3um; after etching the gate trench, a symmetrical Pwell region and a symmetrical N+ region are formed on the surface of the epitaxial layer; The source trench is etched symmetrically downward from the left and right sides of the epitaxial layer, and it is ensured that the source trench is in direct contact with the P shielding layer. The etching width is 0.3-0.5um and the thickness is 1.2-3.2um.
5. The method for preparing a SiC MOSFET with a source trench sidewall integrated SBD according to claim 4, characterized in that: The specific implementation process of S4 includes: Depositing oxide on the bottom and sidewalls of the gate trench, wherein the thickness of the oxide deposited on the bottom of the trench is 0.05um-0.1um, and the thickness of the oxide deposited on the sidewalls of the trench is 0.05um-0.15um; Then, the first step of polysilicon deposition is performed on the gate trench to form a shield gate, and the deposition thickness is 0.2um-1um; Continue to perform oxide deposition on the gate trench, the oxide layer deposited at the bottom of the trench has a thickness of 0.05um-0.1um, and the oxide layer deposited on the sidewall has a thickness of 0.05um; Then, a second polysilicon deposition is performed on the gate trench to form a gate, and the deposition thickness is 0.6um-1um; Finally, oxide deposition is performed on the gate to make the deposited oxide layer flush with the surface of the epitaxial layer.
6. The method for preparing a SiC MOSFET with a source trench sidewall integrated SBD according to claim 5, characterized in that: In S5, Titanium metal is selected as the metal for source trench deposition.
7. A SiC MOSFET with a source trench sidewall integrated SBD, characterized in that: The SiC MOSFET is manufactured by the method for manufacturing a source trench sidewall integrated SBD according to any one of claims 1 to 6.