Quasi-vertical JBS diode and monolithic integrated DRU three-phase rectification unit

Abstract

The invention discloses a quasi-vertical JBS diode and a monolithic integrated DRU three-phase rectification unit. The quasi-vertical JBS diode sequentially comprises a Si substrate, an N + GaN conduction layer and an N-type GaN drift layer from bottom to top. Groove structures distributed in a concentric ring shape are arranged in the top layer area of the N-type GaN drift layer, and P-type BN materials doped with Mg are arranged in the groove structures and on the side face of the N-type GaN drift layer. An anode is arranged on the surface of the N-type GaN drift layer; and cathodes are arranged at intervals around the N-type GaN drift layer on the surface of the N + GaN conduction layer. According to the invention, the withstand voltage value of the diode can be improved. The monolithic integration DRU three-phase rectification unit circuit comprises three alternating current input ends, two rectified direct current output ends and diode groups corresponding to six rectification bridge arms respectively, the diodes are all quasi-vertical JBS diodes, the integration level can be improved, the circuit size can be reduced, the circuit reliability can be improved, and a voltage application window can be widened.

Description

Technical Field

[0001] The invention belongs to the field of semiconductors, and in particular relates to a quasi-vertical JBS diode and a monolithically integrated DRU three-phase rectifier unit. Background Art

[0002] DRU (diode rectifier unit) rectifier units are commonly used for AC / DC conversion in high-power power electronic equipment. In the prior art, most power devices still use high-power silicon single tubes in the form of discrete devices for use in DRU rectifier circuits, but the use of discrete devices to form DRU rectifier circuits results in low integration. With the increasing requirements for the power handling capacity, miniaturization, and reliability of rectifier systems, the existing board-level integrated DRU rectifier system will become increasingly difficult to adapt to the needs of the times.

[0003] Most of the existing diodes, the core components of DRU circuits, are made of Si-based materials. However, with the increasing requirements for efficiency, power density, and device size of power processing equipment, Si-based devices are rapidly approaching the theoretical limits of their intrinsic material properties, resulting in low device power density and difficulty in miniaturization under high-power conditions.

[0004] Moreover, the voltage application range of existing small-size DRU circuits is narrow, and the withstand voltage of the core device diode is low, which restricts the performance and development of the DRU rectifier unit. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a quasi-vertical JBS diode, a method for preparing a quasi-vertical JBS diode, a monolithic integrated DRU three-phase rectifier unit and a method for preparing a monolithic integrated DRU three-phase rectifier unit. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] In a first aspect, an embodiment of the present invention provides a quasi-vertical JBS diode, including:

[0007] A Si substrate, an N+GaN conducting layer, and an N-type GaN drift layer are sequentially arranged from bottom to top; a concentric ring-shaped groove structure is arranged in the top region of the N-type GaN drift layer, and a Mg-doped P-type BN material is arranged inside each groove structure and on the side of the N-type GaN drift layer; an anode is arranged on the surface of the entire N-type GaN drift layer provided with the groove structure; and a cathode is arranged on the surface of the N+GaN conducting layer and is spaced around the N-type GaN drift layer.

[0008] In one embodiment of the present invention, the doping concentration of Si in the N+GaN conducting layer is 1.0×10 18 cm-3 ~1.0×10 19 cm -3 .

[0009] In one embodiment of the present invention, the Si doping concentration of the non-groove structure portion of the N-type GaN drift layer is 1.8×10 15 cm -3 ~1.0×10 17 cm -3 .

[0010] In one embodiment of the present invention, the doping concentration of Mg in the P-type BN material is 1.7×10 15 cm -3 ~5.0×10 16 cm -3 .

[0011] In one embodiment of the present invention, the depth of the groove structure is 0.5 μm to 4 μm, and the spacing between the concentric annular groove structures is 1 μm to 2.5 μm.

[0012] In a second aspect, an embodiment of the present invention provides a method for preparing a quasi-vertical JBS diode, which is used to prepare the quasi-vertical JBS diode described in the first aspect. The method for preparing the quasi-vertical JBS diode includes:

[0013] Acquire an epitaxial layer structure, wherein the epitaxial layer structure includes, from bottom to top, a Si substrate, an N+GaN conducting layer, and an N-type GaN drift layer;

[0014] The outer N-type GaN drift layer is removed by etching, so that the retained N-type GaN drift layer and the exposed N+GaN conductive layer form a step structure;

[0015] The outer N+GaN conductive layer is removed by etching, so that the retained N+GaN conductive layer and the exposed Si substrate form a step structure;

[0016] A groove structure distributed in a concentric ring shape is etched in a top region of the N-type GaN drift layer;

[0017] The P-type BN material doped with Mg is sputtered inside the groove structure and on the side of the N-type GaN drift layer by using a magnetron sputtering process, and then thermally annealed; the excess sputtered material on the upper surface of the device is removed by using an F-based etching process;

[0018] growing a passivation layer on all surfaces and sides exposed above the upper surface of the Si substrate;

[0019] The passivation layer on the entire surface of the N-type GaN drift layer is removed to form an anode contact opening, and the passivation layer at predetermined positions on both sides of the N+GaN conductive layer is removed to form a cathode contact opening;

[0020] An anode is formed by metal evaporation in the anode contact opening, and a cathode surrounding the N-type GaN drift layer and having a certain distance therebetween is formed by metal evaporation in the cathode contact opening.

[0021] In a third aspect, an embodiment of the present invention provides a monolithic integrated DRU three-phase rectifier unit, comprising:

[0022] The first AC input terminal, the second AC input terminal, the third AC input terminal, the first rectified DC output terminal, the second rectified DC output terminal, and the diode groups corresponding to the six rectifier bridge arms, including a first phase forward diode group, a first phase reverse diode group, a second phase forward diode group, a second phase reverse diode group, a third phase forward diode group, and a third phase reverse diode group;

[0023] Wherein, the first AC input terminal is connected to the anode input terminal of the first phase forward diode group and the cathode input terminal of the first phase reverse diode group;

[0024] The second AC input terminal is connected to the anode input terminal of the second phase forward diode group and the cathode input terminal of the second phase reverse diode group;

[0025] The third AC input terminal is connected to the anode input terminal of the third phase forward diode group and the cathode input terminal of the third phase reverse diode group;

[0026] The first rectified DC output terminal is connected to the cathode input terminals of the first phase forward diode group, the second phase forward diode group, and the third phase forward diode group;

[0027] The second rectified DC output terminal is connected to the anode input terminals of the first phase reverse diode group, the second phase reverse diode group, and the third phase reverse diode group;

[0028] The diodes in each diode group are connected in series in the same direction and are the same in number. The quasi-vertical JBS diodes described in the first aspect are used to implement the diodes. The preparation method of each quasi-vertical JBS diode is the preparation method of the quasi-vertical JBS diode described in the second aspect.

[0029] In one embodiment of the present invention, the working process of the monolithic integrated DRU three-phase rectifier unit includes:

[0030] In each cycle, the three-phase electrical waveform input through the first AC input terminal, the second AC input terminal, and the third AC input terminal, according to the on-state of the circuit, in six on-intervals, uses the diode groups that are simultaneously turned on in the corresponding on-intervals to rectify the input side AC voltage into an output side DC voltage, and outputs it through the first rectified DC output terminal and the second rectified DC output terminal; wherein, in each on-interval, there are and only two diode groups that are positive and negative to each other that are turned on.

[0031] In one embodiment of the present invention, within the six turn-on intervals, the diode groups that are turned on simultaneously include:

[0032] In the first start-up interval T1, the first phase forward diode group and the third phase reverse diode group are turned on;

[0033] In the second start-up interval T2, the second phase forward diode group and the third phase reverse diode group are turned on;

[0034] In the third start-up interval T3, the second phase forward diode group and the first phase reverse diode group are turned on;

[0035] In the fourth start-up interval T4, the third phase forward diode group and the first phase reverse diode group are turned on;

[0036] In the fifth start interval T5, the third phase forward diode group and the second phase reverse diode group are turned on;

[0037] In a sixth start-up interval T6 , the first-phase forward diode group and the second-phase reverse diode group are turned on.

[0038] In a fourth aspect, an embodiment of the present invention provides a method for preparing a monolithic integrated DRU three-phase rectifier unit, which is used to prepare the monolithic integrated DRU three-phase rectifier unit described in the third aspect, and the method for preparing the monolithic integrated DRU three-phase rectifier unit includes:

[0039] On the same Si substrate, a plurality of quasi-vertical JBS diodes are obtained; wherein each quasi-vertical JBS diode is prepared by using the preparation method of the quasi-vertical JBS diode described in the second aspect;

[0040] A passivation layer is grown again on all surfaces and sides of the multi-device structure exposed on the Si substrate, holes are opened by etching the passivation layer, and metal is evaporated in the holes to form a first layer of metal interconnection according to the quasi-vertical JBS diode electrode connection requirements of the monolithic integrated DRU three-phase rectifier unit;

[0041] The passivation layer is grown again, holes are opened by etching the passivation layer, and metal is evaporated in the holes to form the second layer of metal interconnection according to the quasi-vertical JBS diode electrode connection requirements of the monolithic integrated DRU three-phase rectifier unit.

[0042] Beneficial effects of the present invention:

[0043] The diode of the embodiment of the present invention uses silicon-based GaN material, which can reduce circuit costs, and uses grooves filled with Mg-doped P-type BN material on a silicon-based gallium nitride substrate to ensure that the diode forms a JBS (junction barrier Schottky) structure. The embodiment of the present invention replaces the traditional Schottky diode with a quasi-vertical diode with Mg-doped P-type BN JBS technology, and utilizes the high breakdown field strength of the BN material, the electric field adjustment capability of the JBS ring structure, and the device sidewall covering P-BN to suppress the sidewall leakage current, which can improve the withstand voltage value of the diode.

[0044] The monolithic integrated DRU three-phase rectifier unit provided on this basis has achieved an improvement in integration, greatly reduced the circuit volume, and can improve circuit reliability. Existing devices mostly use Si devices, while GaN devices can work stably under more complex working conditions compared to Si devices. The excellent electrical properties and stability they possess are considered to be suitable for applications in high frequency, high power, strong radiation and other occasions. The silicon-based gallium nitride quasi-vertical JBS diode based on the P-BN technology of the present invention utilizes the high breakdown field strength of the BN material and the electric field regulation capability of the JBS structure, which greatly improves the withstand voltage level of the Schottky diode, broadens the voltage application window of the miniaturized DRU three-phase rectifier circuit, and can enhance the power handling capacity of the DRU rectifier circuit. However, the existing technology mostly uses traditional Schottky diodes, lacks effective junction terminal technology to increase the operating voltage of the device, and limits the working range of the existing devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic diagram of the structure of a quasi-vertical JBS diode provided by an embodiment of the present invention;

[0046] Figure 2 A cross-sectional schematic diagram of a quasi-vertical JBS diode provided by an embodiment of the present invention;

[0047] Figure 3 A schematic longitudinal cross-sectional view of a quasi-vertical JBS diode provided by an embodiment of the present invention;

[0048] Figure 4 A schematic flow chart of a method for preparing a quasi-vertical JBS diode provided in an embodiment of the present invention;

[0049] Figure 5a to Figure 5j A schematic diagram of a process for preparing a quasi-vertical JBS diode provided by an embodiment of the present invention;

[0050] Figure 6 A circuit schematic diagram of a monolithic integrated DRU three-phase rectifier unit provided in an embodiment of the present invention;

[0051] Figure 7 The overall 3D diagram of the circuit used by the monolithic integrated DRU three-phase rectifier unit provided in the embodiment of the present invention;

[0052] Figure 8 A 3D diagram showing a top view of a circuit used in a monolithic integrated DRU three-phase rectifier unit provided in an embodiment of the present invention;

[0053] Fig. 9 The conduction state of the monolithic integrated DRU three-phase rectifier unit circuit in different time periods provided by the embodiment of the present invention;

[0054] Fig.10 A schematic diagram of the diode conduction state of the monolithic integrated DRU three-phase rectifier unit circuit in the first turn-on interval T1 provided in an embodiment of the present invention;

[0055] Fig.11 The overall output diagram of the monolithic integrated DRU three-phase rectifier unit circuit provided by the embodiment of the present invention;

[0056] Fig.12 A schematic flow chart of a method for preparing a monolithic integrated DRU three-phase rectifier unit provided in an embodiment of the present invention;

[0057] Figure 13a to Figure 13g A schematic diagram of the process of preparing a monolithic integrated DRU three-phase rectifier unit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0058] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0059] At present, third-generation semiconductor materials such as GaN have excellent electrical properties such as large bandgap, high critical breakdown electric field, high saturation velocity, good thermal conductivity, high temperature resistance and corrosion resistance compared to Si-based materials, and are considered to be suitable for applications in high frequency, high power, strong radiation and other occasions. In recent years, thanks to excellent characteristics such as low saturation velocity, low breakdown voltage, low inversion layer mobility and high device resistance, GaN-based power devices have developed rapidly and have been widely used in power systems. However, with the increasing requirements for the power handling capacity and miniaturization of rectifier systems, and the diversification of usage scenarios, higher requirements for the reliability of circuit systems, the industry has increasingly called for integrated GaN power modules. Compared with traditional GaN integrated circuits, silicon-based GaN monolithic integrated circuits have smaller size, smaller parasitics, higher power density, lower cost and higher reliability, enabling them to be used in high-power power conversion systems with complex working conditions and limited volume, such as inverters, AC / DC bridges, DC / DC bridges, traction modules and other occasions.

[0060] Therefore, the present invention considers designing a DRU rectifier unit using silicon-based GaN to solve the aforementioned defects of the existing DRU rectifier unit.

[0061] In order to achieve the above objectives, embodiments of the present invention provide a quasi-vertical JBS diode, a method for preparing a quasi-vertical JBS diode, a monolithically integrated DRU three-phase rectifier unit, and a method for preparing a monolithically integrated DRU three-phase rectifier unit.

[0062] In a first aspect, an embodiment of the present invention provides a quasi-vertical JBS diode, see Figure 1 The front view of the quasi-vertical JBS diode is shown. Figure 2 The cross-sectional diagram of the quasi-vertical JBS diode shown in FIG. Figure 3 The quasi-vertical JBS diode shown is a schematic longitudinal cross-sectional view, wherein the quasi-vertical JBS diode comprises:

[0063] A Si substrate, an N+GaN conductive layer, and an N-type GaN drift layer are sequentially arranged from bottom to top; a concentric ring-shaped groove structure is arranged in the top region of the N-type GaN drift layer, and a Mg-doped P-type BN (boron nitride) material is arranged inside each groove structure and on the side of the N-type GaN drift layer; an anode is arranged on the surface of the entire N-type GaN drift layer provided with the groove structure; and a cathode is arranged on the surface of the N+GaN conductive layer around the N-type GaN drift layer.

[0064] in, Figure 1 to Figure 3In the figure, Si Substarte represents Si substrate; N+GaN and GaN N+ conduction layer both represent N+GaN conduction layer; N GaN and GaN N drift layer both represent N-type GaN drift layer; P-BN represents P-type BN material doped with Mg; Anode represents anode; Cathode represents cathode.

[0065] Specifically, the Si substrate may adopt a 111 crystal plane.

[0066] The N+GaN conductive layer is located on the upper surface of the Si substrate and is a cylindrical structure. Its thickness can be set as needed, for example, it can be around 0.6um to 1um. In an optional embodiment, the doping concentration of Si in the N+GaN conductive layer can be 1.0×10 18 cm -3 ~1.0×10 19 cm -3 It is understandable that, generally speaking, the higher the doping concentration, the lower the cathode electrode contact resistance, and the smaller the overall on-resistance will be after the device is turned on. However, too high a concentration may reduce the device withstand voltage to a certain extent, so it needs to be reasonably selected according to needs.

[0067] The N-type GaN drift layer is located in the central area of ​​the upper surface of the N+GaN conductive layer and has a cylindrical structure. The thickness of the N-type GaN drift layer can be set as required, for example, about 3um to 5um.

[0068] The top region of the N-type GaN drift layer is provided with a concentric ring-shaped groove structure, see Figure 2 It is understood that each groove structure is an annular groove structure, and each groove structure is nested in size and distributed concentrically. The number of annular groove structures can be determined according to the flow requirements, and single ring or multiple rings are both possible.

[0069] Figure 2 The depth of the black block indicates the depth of the annular groove structure, and the width of the black block indicates the width of the annular groove structure. The depth of the groove structure is less than the thickness of the N-type GaN drift layer. In an optional embodiment, the depth of the groove structure can be 0.5μm to 4μm; generally speaking, reducing the spacing between the groove structures can enhance the reverse withstand voltage of the device, but will correspondingly sacrifice the forward conduction area of ​​the device, causing the conduction ability of the device to decrease, so it needs to be reasonably set. In an optional embodiment, the spacing between each concentric annular groove structure can be 1μm to 2.5μm.

[0070] In an optional embodiment, the Si doping concentration of the non-groove structure portion in the N-type GaN drift layer may be 1.8×10 15 cm -3 ~1.0×10 17cm -3 This doping concentration will also affect the device's withstand voltage. Theoretically, the lower the doping concentration, the higher the device's withstand voltage will be. It will also affect the device's forward conduction characteristics. The lower the doping concentration, the greater the forward conduction resistance. Therefore, this value needs to be considered together with the Si doping concentration in the N+GaN conduction layer and the Mg doping concentration in the P-BN.

[0071] The inside of each groove structure and the side of the N-type GaN drift layer are provided with a P-type BN material doped with Mg; Figure 3 As shown, the Mg-doped P-type BN material not only fills the interior of the groove structure, but is also arranged on the side of the N-type GaN drift layer and extends to the surface of the N+GaN conductive layer at the junction of the N+GaN conductive layer and the N-type GaN drift layer. The Mg doping concentration in the P-type BN material will affect the depletion capability of the P-BN ring in the reverse direction. In an optional embodiment, the Mg doping concentration in the P-type BN material can be 1.7×10 15 cm -3 ~5.0×10 16 cm -3 .

[0072] An anode is arranged on the surface of the entire N-type GaN drift layer having the groove structure;

[0073] A cathode is disposed on the surface of the N+GaN conductive layer and surrounds the N-type GaN drift layer. Figure 1 and Figure 2 It can be seen that the cathode is also in the shape of a ring.

[0074] It should be noted that, as a stand-alone quasi-vertical JBS diode, Figure 3 The passivation layer shown in FIG. 1 need not be retained.

[0075] The diodes in the embodiments of the present invention all adopt a quasi-vertical diode structure. Unlike conventional vertical devices, where current is only transported vertically and the anode and cathode are located on the front and back of the wafer respectively, the anode and cathode of the quasi-vertical device are located on the same surface (e.g. Figure 1 and 2 Such a quasi-vertical structure facilitates subsequent connection of devices using on-chip wiring to complete circuit construction.

[0076] The diode of the embodiment of the present invention uses silicon-based GaN material, which can reduce the circuit cost. The groove filling Mg-doped P-type BN material on the silicon-based gallium nitride substrate can ensure that the diode forms a JBS (junction barrier Schottky) structure. The embodiment of the present invention replaces the traditional Schottky diode with a quasi-vertical diode with Mg-doped P-type BN JBS technology. The high breakdown field strength of the BN material, the electric field regulation ability of the JBS ring structure, and the device sidewall covering P-BN can be used to suppress the sidewall leakage current. The withstand voltage value of the diode can be improved. If the proposed quasi-vertical JBS diode is used to construct a monolithic integrated DRU three-phase rectifier unit, the power processing capacity of the DRU rectifier circuit can be enhanced.

[0077] In a second aspect, an embodiment of the present invention provides a method for preparing a quasi-vertical JBS diode, which is used to prepare the quasi-vertical JBS diode described in the first aspect, see Figure 4 The method for preparing the quasi-vertical JBS diode may include the following steps:

[0078] S1, obtaining an epitaxial layer structure, wherein the epitaxial layer structure includes, from bottom to top, a Si substrate, an N+GaN conducting layer, and an N-type GaN drift layer;

[0079] For epitaxial layer structure, see Figure 5a It is understood that Si Substarte means Si substrate; N+GaN means N+GaN conductive layer; N GaN means N-type GaN drift layer.

[0080] The Si substrate may adopt a 111 crystal plane. The doping concentration of Si in the N+GaN conducting layer may be 1.0×10 18 cm -3 ~1.0×10 19 cm -3 The Si doping concentration in the N-type GaN drift layer can be 1.8×10 15 cm -3 ~1.0×10 17 cm -3 .

[0081] S2, etching and removing the outer N-type GaN drift layer, so that the retained N-type GaN drift layer and the exposed N+GaN conductive layer form a step structure;

[0082] This step is to achieve mesa etching, and etch the N-type GaN drift layer on the outside downward to expose the N+GaN conduction layer. It can be understood that the retained N-type GaN drift layer is still a cylindrical structure. The etching depth is above 4um. Specifically, Cl-based ICP (inductively coupled) etching can be used. The etching gases are mainly Cl2 and BCl3, among which BCl3 is a sidewall protection gas, which can effectively improve the selectivity and improve the etching morphology. The etching power adopts fast etching conditions, with an upper power between 120W and 160W, a lower power between 45W and 60W, and a cavity pressure controlled between 4 and 7mt. For the device structure formed in this step, please see Figure 5b shown.

[0083] S3, etching and removing the outer N+GaN conductive layer, so that the retained N+GaN conductive layer and the exposed Si substrate form a step structure;

[0084] This step is to achieve isolation etching of the active area, specifically etching the outer side of the N+GaN conductive layer downward until the Si substrate is exposed. It can be understood that the retained N+GaN conductive layer is still a cylindrical structure. The etching conditions of this step are consistent with S2, and the etching depth is about 1um. The device structure formed in this step is shown in Figure 5c shown.

[0085] S4, etching a groove structure distributed in a concentric ring shape in the top region of the N-type GaN drift layer;

[0086] This step is to etch the P-type groove in the anode area, and Cl-based ICP etching is also used. However, since the requirements for etching damage in the conduction area are higher than those in the MESA (table), only a smaller etching power can be used. The upper electrode power is between 35W and 50W, and the lower electrode power is below 20W, but not less than 13W. The cavity pressure is controlled between 4 and 6mt. The etched groove structure is distributed in concentric rings, and the depth of the groove structure is less than the thickness of the N-type GaN drift layer; the depth of the groove structure is 0.5μm to 4μm, and the spacing between the groove structures is 1μm to 2.5μm.

[0087] The device structure formed in this step is shown in Figure 5d shown.

[0088] S5, sputtering Mg-doped P-type BN material inside the groove structure and on the side of the N-type GaN drift layer by using a magnetron sputtering process, and performing a thermal annealing treatment; removing excess sputtered material on the upper surface of the device by using an F-based etching process;

[0089] P-type BN material (P-BN for short) is sputtered inside the groove structure and on the side of the N-type GaN drift layer, and thermal annealing is performed to activate impurities. Specifically, dual-target RF magnetron sputtering is used to grow the P-BN layer. The chamber pressure is between 4mt and 5mt, the sputtering gas is Ar, and the sputtering power is between 150W and 160W. The sputtering depth needs to be adjusted according to the depth of the groove structure and needs to be slightly greater than the etching depth of the groove structure. After sputtering, annealing is performed at 1100-1200°C for 10 minutes to activate Mg impurities, thereby forming Mg-doped P-type BN material inside the groove structure and on the side of the N-type GaN drift layer, such as Figure 5e shown.

[0090] Then, the excess Mg-doped P-type BN material beyond the surface of the groove structure is etched away. Figure 5f As shown. Specifically, F-based ICP etching is mainly used, and the main etching gases are SF6, CF4, CHF3, etc. Since BN etching is more difficult, the power used for etching is relatively large, wherein the upper power is between 180W and 200W, and the lower power is controlled between 65W and 77W. Due to the high selectivity of F-based etching for GaN materials, the etching can be set to an over-etching amount greater than 30% of the target depth, ensuring that the BN area to be etched can be etched cleanly, while also minimizing the etching of the GaN material as much as possible.

[0091] The results are as follows Figure 5f As shown, the Mg-doped P-type BN material is distributed inside the trench structure, on the side of the N-type GaN drift layer, and extends to a portion of the surface of the N+GaN conductive layer.

[0092] S6, growing a passivation layer on all surfaces and sides exposed above the upper surface of the Si substrate;

[0093] See also Figure 5g , a SiN passivation layer is grown on the entire device upper surface and side surfaces excluding the Si substrate side using a PECVD (plasma enhanced chemical vapor deposition) device (see Figure 5g Medium SiN x ), the target thickness is about 120nm, the reaction gas is SiH4 and NH3, the carrier gas is He, and it grows at 600mt pressure and 250°C. In order to distinguish it from the monolithic integrated DRU three-phase rectifier unit in the following text, the passivation layer here can be called the first passivation layer.

[0094] S7, removing the passivation layer on the entire surface of the N-type GaN drift layer to form an anode contact opening, and removing the passivation layer at predetermined positions on both sides of the N+GaN conductive layer to form a cathode contact opening;

[0095] For this step, see Figure 5hIt is understood that the anode contact opening is the entire surface of the N-type GaN drift layer, and the cathode contact opening is on both sides of the N+GaN conductive layer, and has a spacing with the N-type GaN drift layer.

[0096] Among them, the formation of through holes requires F-based ICP etching to remove the SiN layer in the opening area. In order to ensure that the metal contact area is etched cleanly, at least 40% to 50% overetching is required.

[0097] S8, forming an anode by performing metal evaporation in the anode contact opening, and forming a cathode surrounding the N-type GaN drift layer and having a certain distance therebetween by performing metal evaporation in the cathode contact opening.

[0098] For details, see Figure 5i For the anode Schottky contact, Ni / Au is evaporated and then annealed to form the anode, wherein the metal layer is formed by evaporation, the thickness adopts the thick gate condition Ni / Au=45 / 400 (nm), and the metal pattern is formed by metal stripping. The annealing condition after stripping is N2 environment, annealing at 860℃ for 60S.

[0099] For details, see Figure 5j For the cathode ohmic contact, Ti / Al / Ni / Au is evaporated to form the cathode. The metal layer is also formed by evaporation. The thickness of each layer is

[0100] In this way, a quasi-vertical JBS diode is finally formed. If the quasi-vertical JBS diode is used alone, the passivation layer can be removed. If other devices still need to be interconnected later, the passivation layer is retained.

[0101] As mentioned above, the diode of the embodiment of the present invention adopts groove-grown Mg-doped P-type BN material on a silicon-based gallium nitride substrate, which can reduce circuit costs while ensuring that the diode forms a quasi-vertical JBS structure, thereby improving the withstand voltage value of the diode.

[0102] In the third aspect, based on the proposed quasi-vertical JBS diode, an embodiment of the present invention provides a monolithic integrated DRU three-phase rectifier unit, see Figure 6 , the monolithic integrated DRU three-phase rectifier unit includes:

[0103] A first AC input terminal Port1, a second AC input terminal Port2, a third AC input terminal Port3, a first rectified DC output terminal Port4, a second rectified DC output terminal Port5, and diode groups corresponding to the six rectifier bridge arms, including a first phase forward diode group DG1, a first phase reverse diode group DG2, a second phase forward diode group DG3, a second phase reverse diode group DG4, a third phase forward diode group DG5, and a third phase reverse diode group DG6;

[0104] The first AC input terminal Port1 is connected to the anode input terminal of the first phase forward diode group DG1 and the cathode input terminal of the first phase reverse diode group DG2;

[0105] The second AC input terminal Port2 is connected to the anode input terminal of the second phase forward diode group DG3 and the cathode input terminal of the second phase reverse diode group DG4;

[0106] The third AC input terminal Port3 is connected to the anode input terminal of the third phase forward diode group DG5 and the cathode input terminal of the third phase reverse diode group DG6;

[0107] The first rectified DC output terminal Port4 is connected to the cathode input terminals of the first phase forward diode group DG1, the second phase forward diode group DG3, and the third phase forward diode group DG5;

[0108] The second rectified DC output terminal Port5 is connected to the anode input terminals of the first phase reverse diode group DG2, the second phase reverse diode group DG4, and the third phase reverse diode group DG6;

[0109] The diodes in each diode group are connected in series in the same direction and are the same in number. Each diode is implemented using the quasi-vertical JBS diode described in the first aspect, and the preparation method is the preparation method of the quasi-vertical JBS diode described in the second aspect.

[0110] Specifically, each diode group corresponds to a rectifier bridge arm. The number of diodes in each diode group can be adjusted according to the system capacity requirements, with a minimum of one, but the number of diodes in each diode group is the same. The diodes in each diode group satisfy the same-direction series connection relationship, that is, the cathode of the previous diode is connected to the anode of the next diode.

[0111] Figure 7 This is the overall 3D diagram of the circuit used by the monolithic integrated DRU three-phase rectifier unit. Figure 8This is a 3D diagram of the circuit used by the monolithic integrated DRU three-phase rectifier unit. Ports 1 to 3 are Port1 to Port3, Ports 4 to 5 are Port4 to Port5, and D1 to D6 are DG1 to DG6. The light-colored connecting lines correspond to the first layer, and the light-colored connecting lines correspond to the second layer. For the connection relationship of each diode group on the first or second layer, please refer to Figure 7 and Figure 8 Please understand the comparison, and I will not explain them one by one here.

[0112] The basic structural unit of the DRU three-phase rectifier unit proposed in the embodiment of the present invention is 6 rectifier bridge arms, each of which is mainly composed of high-power diodes connected in series (all of which are quasi-vertical JBS diodes provided in the first aspect). DRU is essentially a grid-commutated converter, which requires the connected AC system to provide a stable commutation voltage, and then the 6 bridge arms are turned on in sequence to rectify the input side AC voltage into the output side DC voltage. The topological structure and operating principle of DRU are very similar to the LCC used in the converter station of the traditional high-voltage direct current transmission system. The main difference is that the thyristor used in LCC is a semi-controlled device and needs to be configured with a corresponding phase-controlled trigger unit, while the high-power diode used in DRU is an uncontrollable device. DRU can only realize rectification operation, but does not need to receive a trigger control signal during operation, and does not need to configure additional control equipment.

[0113] The working process of the monolithic integrated DRU three-phase rectifier unit includes:

[0114] In each cycle, the three-phase electrical waveform input through the first AC input terminal Port1, the second AC input terminal Port2, and the third AC input terminal Port3, according to the on-state of the circuit, in six on-intervals, uses the diode groups that are simultaneously turned on in the corresponding on-intervals to rectify the input side AC voltage into an output side DC voltage, and outputs it through the first rectified DC output terminal Port4 and the second rectified DC output terminal Port5; wherein, in each on-interval, there are and only two diode groups that are positive and negative to each other and are turned on.

[0115] Specifically, a three-phase electrical waveform of one cycle can be roughly divided into six opening intervals T1-T6 according to the opening state of the circuit. In each interval, there are only two circuits that are positive and negative to each other and are turned on at the same time.

[0116] See also Fig. 9 The shaded area in the middle shows that the diode groups that are turned on at the same time in the six turn-on intervals include:

[0117] In the first start-up interval T1, the first phase forward diode group DG1 and the third phase reverse diode group DG6 are turned on;

[0118] In the second start-up interval T2, the second phase forward diode group DG3 and the third phase reverse diode group DG6 are turned on;

[0119] In the third start-up interval T3, the second phase forward diode group DG3 and the first phase reverse diode group DG2 are turned on;

[0120] In the fourth start-up interval T4, the third phase forward diode group DG5 and the first phase reverse diode group DG2 are turned on;

[0121] In the fifth start interval T5, the third phase forward diode group DG5 and the second phase reverse diode group DG4 are turned on;

[0122] In the sixth start-up interval T6 , the first phase forward diode group DG1 and the second phase reverse diode group DG4 are turned on.

[0123] The opening intervals represented by T1 to T6 are different time segments.

[0124] Specifically,

[0125] ① In the first opening interval T1, since the first phase electricity has the highest voltage, the forward diode group of the first phase electricity, namely the first phase forward diode group DG1, is turned on, and the forward diode groups of the other two phases, namely the second phase forward diode group DG3 and the third phase forward diode group DG5, are in the reverse cut-off state and are not turned on because the second and third phase voltages corresponding to each of them are less than the first phase input voltage. Since the third phase electricity has the highest reverse voltage at this time, the reverse diode group of the third phase electricity, namely the third phase reverse diode group DG6, is turned on, and the reverse diode groups of the other two phases, namely the first phase reverse diode group DG2 and the second phase reverse diode group DG4, are turned off. At this time, for the output end, the DC positive polarity output voltage is the first phase voltage, the DC negative polarity output voltage is the third phase voltage, and the overall output voltage is the absolute value of the voltage difference between the two phases.

[0126] by Figure 8 Based on, the diode conduction state in the first opening interval T1 can be found in Fig.10 shown.

[0127] ② In the second opening interval T2, since the second phase electricity has the highest voltage, the forward diode group of the second phase electricity, i.e., the second phase forward diode group DG3, is turned on, and the forward diode groups of the other two phases, i.e., the first phase forward diode group DG1 and the third phase forward diode group DG5, are not turned on because the anode voltage is less than the second phase input voltage. The third phase electricity has the highest reverse voltage, and at this time, the reverse diode group of the third phase electricity, i.e., the third phase reverse diode group DG6, is turned on, and the reverse diode groups of the other two phases, i.e., the first phase reverse diode group DG2 and the second phase reverse diode group DG4, are turned off. At this time, for the output end, the DC positive polarity output voltage is the second phase electricity voltage, and the DC negative polarity output voltage is the third phase electricity voltage.

[0128] ③ In the third opening interval T3, since the second phase electricity has the highest voltage, the forward diode group of the second phase electricity, namely the second phase forward diode group DG3, is turned on, and the forward diode groups of the other two phases, namely the first phase forward diode group DG1 and the third phase forward diode group DG5, are not turned on because the anode voltage is less than the second phase input voltage. The first phase electricity has the highest reverse voltage, and at this time the first phase reverse diode group DG2 is turned on, and the reverse diode groups of the other two phases, namely the second phase reverse diode group DG4 and the third phase reverse diode group DG6 are turned off. At this time, for the output end, the DC positive polarity output voltage is the second phase electricity voltage, and the DC negative polarity output voltage is the first phase electricity voltage.

[0129] ④ In the fourth opening interval T4, since the third phase electricity has the highest voltage, the forward diode group of the third phase electricity, namely the third phase forward diode group DG5, is turned on, and the forward diode groups of the other two phases, namely the first phase forward diode group DG1 and the second phase forward diode group DG3, are not turned on because the anode voltage is less than the first phase input voltage. The first phase electricity has the highest reverse voltage, and at this time, the first phase reverse diode group DG2 is turned on, and the reverse diode groups of the other two phases, namely the second phase reverse diode group DG4 and the third phase reverse diode group DG6 are turned off. At this time, for the output end, the DC positive polarity output voltage is the third phase voltage, and the DC negative polarity output voltage is the first phase voltage.

[0130] ⑤ In the fifth opening interval T5, since the third phase electricity has the highest voltage, the forward diode group of the third phase electricity, namely the third phase forward diode group DG5, is turned on, and the forward diode groups of the other two phases, namely the first phase forward diode group DG1 and the second phase forward diode group DG3, are not turned on because the anode voltage is less than the third phase input voltage. The second phase electricity has the highest reverse voltage, and at this time the second phase reverse diode group DG4 is turned on, and the reverse diode groups of the other two phases, namely the first phase reverse diode group DG2 and the third phase reverse diode group DG6, are turned off. At this time, for the output end, the DC positive polarity output voltage is the third phase voltage, and the DC negative polarity output voltage is the second phase voltage.

[0131] ⑥ In the sixth opening interval T6, since the first phase has the highest voltage, the forward diode group of the first phase, i.e., the first phase forward diode group DG1, is turned on, and the forward diode groups of the other two phases, i.e., the second phase forward diode group DG3 and the third phase forward diode group DG5, are not turned on because the anode voltage is less than the first phase input voltage. The second phase has the highest reverse voltage, and at this time, the second phase reverse diode group DG4 is turned on, and the reverse diode groups of the other two phases, i.e., the first phase reverse diode group DG2 and the third phase reverse diode group DG6 are turned off. At this time, for the output end, the DC positive polarity output voltage is the first phase voltage, and the DC negative polarity output voltage is the second phase voltage.

[0132] The final DC output waveform is the difference between the maximum and minimum values ​​of the positive and negative voltages at each moment, that is, the voltage envelope, see Fig.11 The above six conduction processes, specific waveforms and the open state of each time interval are as follows: Fig. 9 shown.

[0133] The monolithic integrated DRU three-phase rectifier unit provided in the embodiment of the present invention is implemented based on the quasi-vertical JBS diode provided, which improves the integration level, greatly reduces the circuit volume, and can improve the circuit reliability. Most existing devices use Si devices, while GaN devices can work stably under more complex working conditions compared to Si devices. The excellent electrical properties and stability they possess are considered to be suitable for applications in high frequency, high power, strong radiation and other occasions. The silicon-based gallium nitride quasi-vertical JBS diode based on the P-BN technology of the present invention utilizes the high breakdown field strength of the BN material and the electric field regulation ability of the JBS structure to greatly improve the withstand voltage level of the Schottky diode and broaden the voltage application window of the miniaturized DRU three-phase rectifier circuit. However, the existing technology mostly uses traditional Schottky diodes, lacks effective junction terminal technology to increase the operating voltage of the device, and limits the working range of the existing devices.

[0134] In a fourth aspect, an embodiment of the present invention provides a method for preparing a monolithic integrated DRU three-phase rectifier unit, which is used to prepare the monolithic integrated DRU three-phase rectifier unit described in the third aspect, see Fig.12 The method for preparing the monolithic integrated DRU three-phase rectifier unit may include the following steps:

[0135] S100, obtaining a plurality of quasi-vertical JBS diodes prepared on the same Si substrate; wherein each quasi-vertical JBS diode is prepared by using the preparation method of the quasi-vertical JBS diode described in the second aspect;

[0136] For details, please refer to the relevant content of the second aspect. The obtained single quasi-vertical JBS diode is as follows: Figure 5j As shown in the figure. Since S100 is made on the same Si substrate, multiple quasi-vertical JBS diodes are prepared. The results are shown in Fig.13a As shown, SiN x Represents the passivation layer, that is, the first passivation layer mentioned above. Layer1 represents the first layer.

[0137] S200, growing a passivation layer again on all surfaces and sides of the exposed multi-device structure on the Si substrate, opening holes by etching the passivation layer, and performing metal evaporation in the holes to form a first layer of metal interconnection according to the quasi-vertical JBS diode electrode connection requirements of the monolithic integrated DRU three-phase rectifier unit;

[0138] like Fig.13b As shown, a second passivation layer is grown to cover all surfaces of the current structure.

[0139] Then as Fig.13c As shown, holes are opened in the anode region and the cathode region respectively by etching the second passivation layer. Metal Via means metal via.

[0140] Thereafter, anode metal is evaporated in the anode contact opening, and cathode metal is evaporated in the cathode contact opening.

[0141] Among them, the process parameters of S200 are consistent with the corresponding steps in the second aspect.

[0142] Finally, according to the quasi-vertical JBS diode electrode connection requirements of the monolithic integrated DRU three-phase rectifier unit, the first layer of metal interconnection is formed, that is, a metal through hole (metal via) is formed to connect with the first layer, such as Fig.13d As shown. Among them, which diode electrodes are specifically connected to the first layer of metal interconnection can be seen in Figure 6 to Figure 8 I understand. I won't explain them one by one here.

[0143] S300, growing a passivation layer again, opening a hole by etching the passivation layer, and performing metal evaporation in the hole, and forming a second layer of metal interconnection according to the quasi-vertical JBS diode electrode connection requirements of the monolithic integrated DRU three-phase rectifier unit.

[0144] like Fig.13e As shown, a third passivation layer is grown to cover all surfaces of the current structure.

[0145] Then as Fig.13f As shown, holes are opened in the anode region and the cathode region respectively by etching the third passivation layer.

[0146] Afterwards, anode metal evaporation is performed in the anode contact opening, and cathode metal evaporation is performed in the cathode contact opening. The process parameters of S300 may be consistent with those of S200.

[0147] Finally, according to the quasi-vertical JBS diode electrode connection requirements of the monolithic integrated DRU three-phase rectifier unit, the second layer of metal interconnection is formed, that is, a metal through hole (metal via) is formed to connect with the second layer, such as Figure 13g As shown. Among them, which diode electrodes are specifically connected to the second layer of metal interconnection can be seen in Figure 6 to Figure 8 I understand. I won't explain them one by one here.

[0148] The method for preparing a monolithic integrated DRU three-phase rectifier unit provided in an embodiment of the present invention is based on the method for preparing a quasi-vertical JBS diode provided, and multiple quasi-vertical JBS diodes are prepared on the same Si substrate. Then, a passivation layer is grown again on all surfaces and sides exposed by the multi-device structure on the Si substrate, holes are opened by etching the passivation layer, and metal is evaporated in the holes to form a first layer of metal interconnection according to the electrode connection requirements of the quasi-vertical JBS diode of the monolithic integrated DRU three-phase rectifier unit; finally, a passivation layer is grown again, holes are opened by etching the passivation layer, and metal is evaporated in the holes to form a second layer of metal interconnection according to the electrode connection requirements of the quasi-vertical JBS diode of the monolithic integrated DRU three-phase rectifier unit, thereby preparing a monolithic integrated DRU three-phase rectifier unit. The monolithic integrated DRU three-phase rectifier unit is implemented based on the provided quasi-vertical JBS diode, which improves the integration, greatly reduces the circuit volume, and can improve the circuit reliability. Most existing devices use Si devices, while GaN devices can work stably under more complex working conditions than Si devices. Their excellent electrical properties and stability are considered suitable for applications in high frequency, high power, strong radiation and other occasions. The silicon-based gallium nitride quasi-vertical JBS diode of the present invention based on P-BN technology utilizes the high breakdown field strength of BN materials and the electric field regulation capability of the JBS structure, greatly improving the withstand voltage level of the Schottky diode and broadening the voltage application window of the miniaturized DRU three-phase rectifier circuit. However, the existing technology mostly uses traditional Schottky diodes, lacking effective junction terminal technology to increase the operating voltage of the device, which limits the working range of the existing devices.

[0149] It should be noted that, in the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0150] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0151] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0152] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A quasi-vertical JBS diode, It is characterized in that include: Si substrate, N+GaN conducting layer, and N-type GaN drift layer are arranged in sequence from bottom to top; A concentrically annular groove structure is arranged in the top region of the N-type GaN drift layer, and a Mg-doped P-type BN material is arranged inside each groove structure and on the side of the N-type GaN drift layer; an anode is arranged on the surface of the entire N-type GaN drift layer provided with the groove structure; and a cathode is arranged on the surface of the N+GaN conductive layer, surrounding the N-type GaN drift layer.

2. The quasi-vertical JBS diode according to claim 1, It is characterized in that The doping concentration of Si in the N+GaN conducting layer is 1.0×10 18 cm -3 ~1.0×10 19 cm -3 .

3. The quasi-vertical JBS diode according to claim 1, It is characterized in that The Si doping concentration of the non-groove structure portion of the N-type GaN drift layer is 1.8×10 15 cm -3 ~1.0×10 17 cm -3 .

4. The quasi-vertical JBS diode according to claim 1, It is characterized in that The doping concentration of Mg in the P-type BN material is 1.7×10 15 cm -3 ~5.0×10 16 cm -3 .

5. The quasi-vertical JBS diode according to claim 1, It is characterized in that The depth of the groove structure is 0.5 μm to 4 μm, and the spacing between the concentric annular groove structures is 1 μm to 2.5 μm.

6. A method for preparing a quasi-vertical JBS diode, It is characterized in that Used to prepare the quasi-vertical JBS diode according to any one of claims 1 to 5, the preparation method of the quasi-vertical JBS diode comprising: Acquire an epitaxial layer structure, wherein the epitaxial layer structure includes, from bottom to top, a Si substrate, an N+GaN conducting layer, and an N-type GaN drift layer; The outer N-type GaN drift layer is removed by etching, so that the retained N-type GaN drift layer and the exposed N+GaN conductive layer form a step structure; The outer N+GaN conductive layer is removed by etching, so that the retained N+GaN conductive layer and the exposed Si substrate form a step structure; A groove structure distributed in a concentric ring shape is etched in a top region of the N-type GaN drift layer; The P-type BN material doped with Mg is sputtered inside the groove structure and on the side of the N-type GaN drift layer by using a magnetron sputtering process, and then thermally annealed; the excess sputtered material on the upper surface of the device is removed by using an F-based etching process; growing a passivation layer on all surfaces and sides exposed above the upper surface of the Si substrate; The passivation layer on the entire surface of the N-type GaN drift layer is removed to form an anode contact opening, and the passivation layer at predetermined positions on both sides of the N+GaN conductive layer is removed to form a cathode contact opening; An anode is formed by metal evaporation in the anode contact opening, and a cathode surrounding the N-type GaN drift layer and having a certain distance therebetween is formed by metal evaporation in the cathode contact opening.

7. A monolithic integrated DRU three-phase rectifier unit, It is characterized in that include: A first AC input terminal (Port1), a second AC input terminal (Port2), a third AC input terminal (Port3), a first rectified DC output terminal (Port4), a second rectified DC output terminal (Port5), and diode groups corresponding to the six rectifier bridge arms, including a first phase forward diode group (DG1), a first phase reverse diode group (DG2), a second phase forward diode group (DG3), a second phase reverse diode group (DG4), a third phase forward diode group (DG5) and a third phase reverse diode group (DG6); Wherein, the first AC input terminal (Port1) is connected to the anode input terminal of the first phase forward diode group (DG1) and the cathode input terminal of the first phase reverse diode group (DG2); The second AC input terminal (Port2) is connected to the anode input terminal of the second phase forward diode group (DG3) and the cathode input terminal of the second phase reverse diode group (DG4); The third AC input terminal (Port3) is connected to the anode input terminal of the third phase forward diode group (DG5) and the cathode input terminal of the third phase reverse diode group (DG6); The first rectified DC output terminal (Port4) is connected to the cathode input terminals of the first phase forward diode group (DG1), the second phase forward diode group (DG3), and the third phase forward diode group (DG5); The second rectified DC output terminal (Port5) is connected to the anode input terminals of the first phase reverse diode group (DG2), the second phase reverse diode group (DG4), and the third phase reverse diode group (DG6); The diodes in each diode group are connected in series in the same direction and are the same in number. The diodes are implemented by the quasi-vertical JBS diode described in any one of claims 1 to 5. The preparation method of each quasi-vertical JBS diode is the preparation method of the quasi-vertical JBS diode described in claim 6.

8. The monolithic integrated DRU three-phase rectifier unit according to claim 7, It is characterized in that The working process of the monolithic integrated DRU three-phase rectifier unit includes: In each cycle, the three-phase electrical waveform input through the first AC input terminal (Port1), the second AC input terminal (Port2), and the third AC input terminal (Port3) is rectified into an output DC voltage through the diode groups that are simultaneously turned on in the corresponding turn-on intervals in six turn-on intervals according to the turn-on state of the circuit, and output through the first rectified DC output terminal (Port4) and the second rectified DC output terminal (Port5); wherein, in each turn-on interval, there are and only two diode groups that are positive and negative to each other that are turned on.

9. The monolithic integrated DRU three-phase rectifier unit according to claim 8, It is characterized in that In the six turn-on intervals, the diode groups that are turned on at the same time include: In the first start-up interval T1, the first phase forward diode group (DG1) and the third phase reverse diode group (DG6) are turned on; In the second start-up interval T2, the second phase forward diode group (DG3) and the third phase reverse diode group (DG6) are turned on; In the third start-up interval T3, the second phase forward diode group (DG3) and the first phase reverse diode group (DG2) are turned on; In the fourth opening interval T4, the third phase forward diode group (DG5) and the first phase reverse diode group (DG2) are turned on; In the fifth opening interval T5, the third phase forward diode group (DG5) and the second phase reverse diode group (DG4) are turned on; In the sixth start-up interval T6, the first phase forward diode group (DG1) and the second phase reverse diode group (DG4) are turned on.

10. A method for preparing a monolithic integrated DRU three-phase rectifier unit, It is characterized in that For preparing the monolithic integrated DRU three-phase rectifier unit according to any one of claims 7 to 9, the preparation method of the monolithic integrated DRU three-phase rectifier unit comprises: On the same Si substrate, a plurality of quasi-vertical JBS diodes are obtained; wherein each quasi-vertical JBS diode is prepared by using the method for preparing a quasi-vertical JBS diode according to claim 6; A passivation layer is grown again on all surfaces and sides of the multi-device structure exposed on the Si substrate, holes are opened by etching the passivation layer, and metal is evaporated in the holes to form a first layer of metal interconnection according to the quasi-vertical JBS diode electrode connection requirements of the monolithic integrated DRU three-phase rectifier unit; The passivation layer is grown again, holes are opened by etching the passivation layer, and metal is evaporated in the holes to form the second layer of metal interconnection according to the quasi-vertical JBS diode electrode connection requirements of the monolithic integrated DRU three-phase rectifier unit.

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