Preparation method of solar cell and solar cell

Abstract

The invention relates to a preparation method of a solar cell and the solar cell. The preparation method of the solar cell comprises the following steps that a substrate is provided, and the substrate is provided with a front face and a back face which are oppositely arranged; forming a groove on the back surface of the substrate; preparing a tunneling oxide layer and an intrinsic silicon material layer which are stacked in sequence on the back surface, provided with the groove, of the substrate; the intrinsic silicon material layer is provided with a first region and a second region which are respectively positioned on two opposite sides of the groove, doping the intrinsic silicon material layer in the first region to obtain a first doped silicon material layer, and doping the intrinsic silicon material layer in the second region to obtain a second doped silicon material layer, and the doping types of the first doped silicon material layer and the second doped silicon material layer are opposite. According to the preparation method of the solar cell, a relatively good preparation effect of the back contact solar cell can be realized through relatively few process steps.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a method for preparing a solar cell and a solar cell. Background Art

[0002] The back-contact cell is a solar cell structure used to improve cell efficiency. Its core design is to place all the metal electrodes of the solar cell on the back of the cell, thereby ensuring that the front of the cell is not blocked by the metal grid. This can increase the area of ​​the cell that absorbs sunlight, reduce optical losses, and improve photoelectric conversion efficiency.

[0003] In back-contact solar cells, the emitters are all placed on the back of the cell and are composed of two different types of doping regions alternating, which makes the preparation process of back-contact solar cells more complicated. Summary of the invention

[0004] Based on this, it is necessary to provide a method for preparing a solar cell and a solar cell. The method for preparing a solar cell of the present application can achieve a better preparation effect of a back-contact solar cell through fewer process steps.

[0005] In a first aspect, the present application provides a method for preparing a solar cell, comprising the following steps:

[0006] Providing a substrate having a front side and a back side disposed opposite to each other;

[0007] forming a groove on the back side of the substrate;

[0008] Preparing a tunneling oxide layer and an intrinsic silicon material layer stacked in sequence on the back side of the substrate;

[0009] The intrinsic silicon material layer has a first region and a second region respectively located on opposite sides of the groove. The intrinsic silicon material layer in the first region is doped to obtain a first doped silicon material layer, and the intrinsic silicon material layer in the second region is doped to obtain a second doped silicon material layer. The doping types of the first doped silicon material layer and the second doped silicon material layer are opposite.

[0010] In some embodiments, doping the intrinsic silicon material layer in the first region to obtain a first doped silicon material layer, and doping the intrinsic silicon material layer in the second region to obtain a second doped silicon material layer comprises the following steps:

[0011] Disposing a first slurry on the surface of the intrinsic silicon material layer in the first region, wherein the first slurry includes a first doping element;

[0012] Disposing a second slurry on the surface of the intrinsic silicon material layer in the second region, wherein the second slurry includes a second doping element, and the first doping element and the second doping element have opposite doping types;

[0013] The first slurry and the second slurry are used to dope the intrinsic silicon material layer through laser processing.

[0014] In some embodiments, the laser power of the laser treatment is 30W~80W.

[0015] In some embodiments, the maximum width of the laser-processed spot is 100 μm to 300 μm.

[0016] In some embodiments, the spot overlap rate of the laser processing is less than 80%.

[0017] In some embodiments, after doping the intrinsic silicon material layer in the first region to obtain a first doped silicon material layer and doping the intrinsic silicon material layer in the second region to obtain a second doped silicon material layer, the following steps are further included:

[0018] The first doped silicon material layer and the second doped silicon material layer are subjected to hydrogen plasma treatment.

[0019] In some embodiments, the pressure of the hydrogen plasma treatment is 1 Torr~2 Torr.

[0020] In some embodiments, the temperature of the hydrogen plasma treatment is 150°C to 250°C.

[0021] In some embodiments, the hydrogen plasma treatment time is 30s to 200s.

[0022] In some embodiments, forming a groove on the back side of the substrate comprises the following steps:

[0023] preparing a mask layer on the back side of the substrate;

[0024] An opening is formed on the mask layer by laser, and the groove is formed in the opening by laser.

[0025] In some embodiments, after forming the groove in the opening, the following steps are further included:

[0026] The sample after the groove is formed is subjected to a texturing treatment using an alkaline solution to form a suede structure on the groove bottom of the groove and the front side of the substrate.

[0027] In some embodiments, after doping the intrinsic silicon material layer in the first region to obtain a first doped silicon material layer and doping the intrinsic silicon material layer in the second region to obtain a second doped silicon material layer, the following steps are further included:

[0028] A first passivation anti-reflection layer and a second passivation anti-reflection layer are respectively prepared on the front side and the back side of the substrate.

[0029] In a second aspect, the present application provides a solar cell prepared by any of the above-mentioned methods for preparing a solar cell.

[0030] In some embodiments, the solar cell includes a substrate having a front side and a back side disposed opposite to each other, wherein the front side of the substrate has a suede structure and is provided with a first passivation anti-reflection layer;

[0031] A groove is formed on the back side of the substrate, and a tunneling oxide layer, an intrinsic silicon material layer and a second passivation anti-reflection layer are sequentially stacked in the groove;

[0032] The solar cell comprises a first region and a second region respectively located on opposite sides of the groove, the tunneling oxide layer, the first doped silicon material layer and the second passivation anti-reflection layer are sequentially stacked on the back side of the substrate located in the first region, the tunneling oxide layer, the second doped silicon material layer and the second passivation anti-reflection layer are sequentially stacked on the back side of the substrate located in the second region, and the first doped silicon material layer and the second doped silicon material layer have opposite doping types;

[0033] The solar cell further includes a first electrode and a second electrode disposed on the second passivation anti-reflection layer, the first electrode being in electrical contact with the first doped silicon material layer, and the second electrode being in electrical contact with the second doped silicon material layer.

[0034] In the above-mentioned method for preparing solar cells, a groove is first formed on the back side of the substrate, and then a first doped silicon material layer and a second doped silicon material layer of opposite doping types are prepared in the first region and the second region located on opposite sides of the groove, respectively, so that the isolation of different types of emitters can be achieved through fewer process steps. The method for preparing solar cells of the present application can achieve a better preparation effect of back-contact solar cells through fewer process steps.

[0035] Furthermore, the above-mentioned method for preparing solar cells can prepare solar cells with lower leakage current and higher fill factor, thereby achieving higher photoelectric conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG1 is a schematic structural diagram of forming a mask layer on the back side of a substrate;

[0037] FIG2 is a schematic diagram of a structure in which an opening is formed on the basis of the structure shown in FIG1 ;

[0038] FIG3 is a schematic diagram of a structure after grooves are formed and textured on the basis of the structure shown in FIG2 ;

[0039] FIG4 is a schematic diagram of a structure for preparing a tunnel oxide layer and an intrinsic silicon material layer based on the structure shown in FIG3 ;

[0040] FIG5 is a schematic diagram of a structure in which a first slurry and a second slurry are formed on the basis of the structure shown in FIG4 ;

[0041] FIG6 is a schematic diagram of the structure of a first doped silicon material layer and a second doped silicon material layer prepared on the basis of the structure shown in FIG5 ;

[0042] FIG7 is a schematic diagram of a structure in which a first passivation anti-reflection layer and a second passivation anti-reflection layer are formed on the basis of the structure shown in FIG6 ;

[0043] FIG. 8 is a schematic diagram showing a structure in which a first electrode and a second electrode are formed on the basis of the structure shown in FIG. 7 .

[0044] Description of Reference Numerals

[0045] 10. substrate; 20. mask layer; 30. groove; 40. tunneling oxide layer; 50. intrinsic silicon material layer; 61. first slurry; 62. second slurry; 71. first doped silicon material layer; 72. second doped silicon material layer; 81. first passivation anti-reflection layer; 82. second passivation anti-reflection layer; 91. first electrode; 92. second electrode. DETAILED DESCRIPTION

[0046] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0048] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0049] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0050] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0051] 1 to 8 , an embodiment of the present application provides a method for preparing a solar cell, comprising the following steps:

[0052] Providing a substrate 10, the substrate 10 having a front side and a back side arranged opposite to each other;

[0053] forming a groove 30 on the back side of the substrate 10;

[0054] A tunneling oxide layer 40 and an intrinsic silicon material layer 50 are sequentially stacked on the back side of the substrate 10;

[0055] The intrinsic silicon material layer 50 has a first region and a second region respectively located on opposite sides of the groove 30. The intrinsic silicon material layer 50 in the first region is doped to obtain a first doped silicon material layer 71, and the intrinsic silicon material layer 50 in the second region is doped to obtain a second doped silicon material layer 72. The doping types of the first doped silicon material layer 71 and the second doped silicon material layer 72 are opposite.

[0056] In the above-mentioned method for preparing the solar cell, a groove 30 is first formed on the back side of the substrate 10, and then a first doped silicon material layer 71 and a second doped silicon material layer 72 of opposite doping types are prepared in the first region and the second region located on opposite sides of the groove 30, respectively, so that the isolation of different types of emitters can be achieved through fewer process steps. The method for preparing the solar cell of the present application can achieve a better preparation effect of the back contact solar cell through fewer process steps. Furthermore, the above-mentioned method for preparing the solar cell can prepare a solar cell with lower leakage current and higher fill factor, thereby achieving higher photoelectric conversion efficiency.

[0057] In some embodiments, the method for preparing a solar cell comprises the following steps:

[0058] S10 : providing a substrate 10 , wherein the substrate 10 has a front side and a back side that are opposite to each other; and forming a groove 30 on the back side of the substrate 10 .

[0059] In some embodiments, forming the groove 30 on the back side of the substrate 10 includes the following steps:

[0060] Preparing a mask layer 20 on the back side of the substrate 10;

[0061] An opening is formed on the mask layer 20 by laser, and a groove 30 is formed in the opening by laser.

[0062] 1 and 2 , FIG1 is a schematic diagram of a structure in which a mask layer 20 is formed on the back surface of a substrate 10. FIG2 is a schematic diagram of a structure in which an opening is formed based on the structure shown in FIG1 .

[0063] In some of the embodiments, the mask preparation method includes at least one of low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, catalytic chemical vapor deposition and atomic layer deposition.

[0064] In some embodiments, the material of the mask layer 20 includes SiO x and Si x N y At least one of .

[0065] In some embodiments, the groove 30 is prepared by laser ablation.

[0066] In some of the embodiments, the groove 30 is prepared by laser grooving and ablation, the laser wavelength is 355nm, the laser power is 30W~80W, the laser spot size is a square spot of 100μm~300μm, and the spot overlap rate in the horizontal direction is controlled below 80%.

[0067] In some embodiments, after forming the groove 30 in the opening, the following steps are further included:

[0068] The sample after the groove 30 is formed is subjected to a texturing treatment using an alkaline solution, so as to form a suede structure on the groove bottom of the groove 30 and the front surface of the substrate 10 .

[0069] It is understandable that during the texturing process, the back of the substrate 10 on both sides of the groove 30 is protected by the mask layer 20, so the velvet structure is only formed on the bottom of the groove 30 and the front of the substrate 10. Referring to Figure 3, Figure 3 is a schematic diagram of the structure after the groove 30 is formed and the texturing is performed on the basis of the structure shown in Figure 2. In the preparation method of the solar cell of the present application, the process steps of preparing the traditional back contact solar cell can be reduced by first preparing the groove 30 and then performing the texturing process.

[0070] In some of the embodiments, the texturing process lasts for 300s to 420s.

[0071] Optionally, the time of the texturing treatment is 300s, 320s, 340s, 360s, 380s, 400s or 420s, or, the time of the texturing treatment may also be within the range between any two of the above times.

[0072] In some embodiments, the temperature of the texturing treatment is 70°C to 85°C.

[0073] Optionally, the temperature of the texturing treatment is 70°C, 72°C, 74°C, 76°C, 78°C, 80°C, 82°C or 85°C, or, the temperature of the texturing treatment may also be within the range between any two of the above temperatures.

[0074] In some embodiments, the width of the groove 30 is 100 μm-300 μm.

[0075] Optionally, the width of the groove 30 is 100 μm, 120 μm, 140 μm, 160 μm, 180 μm, 200 μm, 220 μm, 240 μm, 260 μm, 280 μm or 300 μm, or the width of the groove 30 may be within the range between any two of the above widths.

[0076] In some embodiments, after the sample with the groove 30 formed therein is subjected to texturing treatment using an alkali solution, the following steps are further included:

[0077] The remaining mask layer 20 is removed using an acid solution.

[0078] In some embodiments, before preparing the mask layer 20 on the back side of the substrate 10, the following steps are also included:

[0079] The substrate 10 is polished using an alkali solution.

[0080] In some embodiments, the alkaline solution includes an alkaline solution and water in a volume ratio of 1:5.

[0081] In some embodiments, the alkaline solution includes at least one of NH4OH, KOH and NaOH.

[0082] In some embodiments, the concentration of the alkaline solution is 40 wt % to 50 wt %.

[0083] Optionally, the concentration of the alkaline solution is 40wt%, 42wt%, 44wt%, 46wt%, 48wt% or 50wt%, or, the concentration of the alkaline solution may also be within the range between any two of the above concentrations.

[0084] In some embodiments, the polishing temperature is 60°C to 80°C.

[0085] Optionally, the polishing temperature is 60°C, 62°C, 64°C, 66°C, 68°C, 70°C, 72°C, 74°C, 76°C, 78°C or 80°C, or, the polishing temperature may be within the range between any two of the above temperatures.

[0086] In some embodiments, the polishing time is 200s to 400s.

[0087] Optionally, the polishing time is 200s, 220s, 240s, 260s, 280s, 300s, 320s, 340s, 360s, 380s or 400s, or, the polishing time may also be within the range between any two of the above times.

[0088] In some embodiments, after polishing the substrate 10 with an alkaline solution, the following steps are further included:

[0089] The polished substrate 10 is cleaned with acid solution and deionized water in sequence.

[0090] In some embodiments, the acid solution includes hydrofluoric acid solution and water in a volume ratio of 1:20.

[0091] In some embodiments, the concentration of the hydrofluoric acid solution is 45 wt % to 50 wt %.

[0092] Optionally, the concentration of the hydrofluoric acid solution is 45wt%, 46wt%, 47wt%, 48wt%, 49wt% or 50wt%, or, the concentration of the hydrofluoric acid solution may also be within the range between any two of the above concentrations.

[0093] In some embodiments, the acid cleaning time is 30s to 200s.

[0094] Optionally, the time for acid cleaning is 30s, 50s, 80s, 100s, 120s, 140s, 160s, 180s or 200s, or, the time for acid cleaning may also be within the range between any two of the above times.

[0095] In some of the embodiments, the tower base morphology size on the surface of the cleaned substrate 10 is 8 μm to 40 μm, and the reflectivity is 40% to 50%.

[0096] S20 : ​​preparing a tunneling oxide layer 40 and an intrinsic silicon material layer 50 stacked in sequence on the back side of the substrate 10 where the groove 30 is formed.

[0097] 4 is a schematic diagram showing a structure in which a tunnel oxide layer 40 and an intrinsic silicon material layer 50 are prepared based on the structure shown in FIG3. It can be understood that the tunnel oxide layer 40 covers both the bottom and the wall of the groove 30 and the back side of the substrate 10.

[0098] In some embodiments, the material of the tunnel oxide layer 40 includes silicon oxide.

[0099] In some embodiments, the thickness of the tunnel oxide layer 40 is 1 nm to 3 nm.

[0100] Optionally, the thickness of the tunnel oxide layer 40 is 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2 nm, 2.2 nm, 2.4 nm, 2.6 nm, 2.8 nm or 3 nm, or the thickness of the tunnel oxide layer 40 may be within a range between any two of the above thicknesses.

[0101] In some embodiments, the tunnel oxide layer 40 is formed by low pressure chemical vapor deposition.

[0102] In some embodiments, the tunnel oxide layer 40 is deposited at a temperature of 500° C. to 800° C.

[0103] Optionally, the deposition temperature of the tunnel oxide layer 40 is 500° C., 550° C., 600° C., 650° C., 700° C., 750° C. or 800° C., or the deposition temperature of the tunnel oxide layer 40 may also be within a range between any two of the above deposition temperatures.

[0104] In some embodiments, the intrinsic silicon material layer 50 has a thickness of 80 nm to 300 nm.

[0105] Optionally, the thickness of the intrinsic silicon material layer 50 is 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, 220 nm, 250 nm, 280 nm or 300 nm, or the thickness of the intrinsic silicon material layer 50 may also be within the range between any two of the above thicknesses.

[0106] In some embodiments, the intrinsic silicon material layer 50 is an intrinsic polysilicon layer.

[0107] In some embodiments, the intrinsic silicon material layer 50 is prepared by low pressure chemical vapor deposition.

[0108] In some embodiments, during the preparation of the intrinsic silicon material layer 50 , the silane flow rate is 200 sccm-1000 sccm.

[0109] Optionally, in the preparation of the intrinsic silicon material layer 50, the silane flow rate is 200 sccm, 300 sccm, 400 sccm, 500 sccm, 600 sccm, 700 sccm, 800 sccm, 900 sccm or 1000 sccm, or the silane flow rate may be within the range between any two of the above flow rates.

[0110] In some embodiments, the deposition temperature of the intrinsic silicon material layer 50 is 500° C. to 900° C.

[0111] Optionally, the deposition temperature of the intrinsic silicon material layer 50 is 500°C, 550°C, 600°C, 650°C, 700°C, 750°C, 800°C, 850°C or 900°C, or, the deposition temperature of the intrinsic silicon material layer 50 may also be within the range between any two of the above temperatures.

[0112] S30: The intrinsic silicon material layer 50 has a first region and a second region respectively located on opposite sides of the groove 30. The intrinsic silicon material layer 50 in the first region is doped to obtain a first doped silicon material layer 71, and the intrinsic silicon material layer 50 in the second region is doped to obtain a second doped silicon material layer 72. The doping types of the first doped silicon material layer 71 and the second doped silicon material layer 72 are opposite.

[0113] In some embodiments, doping the intrinsic silicon material layer 50 in the first region to obtain the first doped silicon material layer 71, and doping the intrinsic silicon material layer 50 in the second region to obtain the second doped silicon material layer 72 comprises the following steps:

[0114] Disposing a first slurry 61 on the surface of the intrinsic silicon material layer 50 in the first region, wherein the first slurry 61 includes a first doping element;

[0115] Disposing a second slurry 62 on the surface of the intrinsic silicon material layer 50 in the second region, the second slurry 62 comprising a second doping element, wherein the first doping element and the second doping element have opposite doping types;

[0116] The first slurry 61 and the second slurry 62 dope the intrinsic silicon material layer 50 through laser processing.

[0117] Referring to Figures 5 and 6, Figure 5 is a schematic diagram of the structure of forming the first slurry 61 and the second slurry 62 on the basis of the structure shown in Figure 4; Figure 6 is a schematic diagram of the structure of preparing the first doped silicon material layer 71 and the second doped silicon material layer 72 on the basis of the structure shown in Figure 5. It can be understood that by arranging the first slurry 61 and the second slurry 62 on the intrinsic silicon material of the first region and the second region and performing doping by laser treatment, the film layer in the middle groove 30 can be kept unchanged, so that the groove 30 separates the first doped silicon material layer 71 and the second doped silicon material layer 72, and at the same time, by performing doping by laser treatment, a doping effect with high precision can be achieved.

[0118] In some embodiments, before the first slurry 61 and the second slurry 62 are doped with the intrinsic silicon material layer 50 by laser processing, the following steps are also included:

[0119] The first slurry 61 and the second slurry 62 are dried and solidified.

[0120] In some embodiments, the first slurry 61 and the second slurry 62 are boron slurry and phosphorus slurry, respectively.

[0121] In some of the embodiments, the printing width of the phosphor paste is 30 μm to 200 μm.

[0122] Optionally, the printing width of the phosphor paste is 30 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm or 200 μm, or, the printing width of the phosphor paste may also be within the range between any two of the above widths.

[0123] In some of the embodiments, the solid content of the phosphorus slurry is 15% to 35%.

[0124] Optionally, the solid content of the phosphorus slurry is 15%, 20%, 25%, 30% or 35%, or, the solid content of the phosphorus slurry may also be within a range between any two of the above solid contents.

[0125] In some embodiments, the viscosity of the phosphorus slurry is 20 Pa·s to 50 Pa·s.

[0126] Optionally, the viscosity of the phosphorus slurry is 20 Pa·s, 25 Pa·s, 30 Pa·s, 35 Pa·s, 40 Pa·s, 45 Pa·s or 50 Pa·s, or, the viscosity of the phosphorus slurry may also be within the range between any two of the above viscosities.

[0127] In some embodiments, the printing width of the boron paste is 50 μm to 200 μm.

[0128] Optionally, the printing width of the boron paste is 50 μm, 80 μm, 100 μm, 120 μm, 140 μm, 160 μm, 180 μm or 200 μm, or, the printing width of the boron paste may also be within the range between any two of the above widths.

[0129] In some embodiments, the solid content of the boron slurry is 20% to 55%.

[0130] Optionally, the solid content of the boron slurry is 20%, 25%, 30%, 35%, 40%, 45%, 50% or 55%, or, the solid content of the boron slurry may also be within the range between any two of the above solid contents.

[0131] In some embodiments, the viscosity of the boron slurry is 20 Pa·s to 50 Pa·s.

[0132] Optionally, the viscosity of the boron slurry is 20 Pa·s, 25 Pa·s, 30 Pa·s, 35 Pa·s, 40 Pa·s, 45 Pa·s or 50 Pa·s, or, the viscosity of the boron slurry may also be within the range between any two of the above viscosities.

[0133] Within the above parameter ranges of the phosphorus paste and the boron paste, a better printing effect of the paste on the intrinsic silicon material layer 50 can be achieved, thereby achieving a more uniform doping effect through laser processing.

[0134] In some embodiments, the laser power of the laser treatment is 30W~80W.

[0135] Optionally, the laser power of the laser processing is 30 W, 40 W, 50 W, 60 W, 70 W or 80 W, or, the laser power of the laser processing may also be within a range between any two of the above powers.

[0136] In some of the embodiments, the maximum width of the laser processed spot is 100 μm to 300 μm.

[0137] Optionally, the maximum width of the laser-processed light spot is 100 μm, 150 μm, 200 μm, 250 μm or 300 μm, or the maximum width of the laser-processed light spot may also be within a range between any two of the above widths.

[0138] In some embodiments, the laser processed spot is a square spot.

[0139] In some of the embodiments, the spot overlap rate of the laser processing is less than 80%.

[0140] In some embodiments, the scanning width of the laser treatment on the area where the boron paste is printed is 500 μm to 700 μm.

[0141] Optionally, the scanning width of the region where the boron paste is printed by laser treatment is 500 μm, 550 μm, 600 μm, 650 μm or 700 μm, or the scanning width of the region where the boron paste is printed by laser treatment may also be within the range between any two of the above widths.

[0142] In some embodiments, the scanning width of the laser processing on the area where the phosphor paste is printed is 300 μm to 500 μm.

[0143] Optionally, the scanning width of the area where the phosphor paste is printed by laser processing is 300 μm, 350 μm, 400 μm, 450 μm or 500 μm, or the scanning width of the area where the phosphor paste is printed by laser processing can also be within the range between any two of the above widths.

[0144] It is understood that the width of the groove 30 remains unchanged after the laser treatment.

[0145] Within the range of the above parameters of the laser processing, a better doping effect on the intrinsic silicon material layer 50 can be achieved by the slurry.

[0146] In some embodiments, after doping the intrinsic silicon material layer 50 in the first region to obtain the first doped silicon material layer 71 and doping the intrinsic silicon material layer 50 in the second region to obtain the second doped silicon material layer 72, the following steps are further included:

[0147] The first doped silicon material layer 71 and the second doped silicon material layer 72 are subjected to hydrogen plasma treatment.

[0148] After the intrinsic silicon material layer 50 is doped with the first slurry 61 and the second slurry 62 to prepare the first doped silicon material layer 71 and the second doped silicon material layer 72 , the first doped silicon material layer 71 and the second doped silicon material layer 72 are subjected to hydrogen plasma treatment, which can effectively improve the quality of interface passivation.

[0149] In some embodiments, the pressure of the hydrogen plasma treatment is 1 Torr to 2 Torr.

[0150] Optionally, the pressure of the hydrogen plasma treatment is 1 Torr, 1.2 Torr, 1.4 Torr, 1.6 Torr, 1.8 Torr or 2 Torr, or, the pressure of the hydrogen plasma treatment may also be within a range between any two of the above pressures.

[0151] In some embodiments, the temperature of the hydrogen plasma treatment is 150°C to 250°C.

[0152] Optionally, the temperature of the hydrogen plasma treatment is 150°C, 160°C, 170°C, 180°C, 190°C, 200°C, 210°C, 220°C, 230°C, 240°C or 250°C, or the temperature of the hydrogen plasma treatment may be within the range between any two of the above temperatures.

[0153] In some embodiments, the hydrogen plasma treatment time is 30s to 200s.

[0154] Optionally, the time of the hydrogen plasma treatment is 30s, 50s, 80s, 100s, 120s, 150s, 180s or 200s, or, the time of the hydrogen plasma treatment may also be within the range between any two of the above times.

[0155] Within the parameter ranges of the above hydrogen plasma treatments, a better treatment effect can be achieved on the first doped silicon material layer 71 and the second doped silicon material layer 72 , and a better effect on improving the interface passivation quality.

[0156] S40: preparing a first passivation anti-reflection layer 81 and a second passivation anti-reflection layer 82 on the front and back sides of the substrate 10 respectively.

[0157] 7 is a schematic diagram of a structure in which a first passivation anti-reflection layer 81 and a second passivation anti-reflection layer 82 are formed on the basis of the structure shown in FIG6. It can be understood that the first passivation anti-reflection layer 81 covers the front surface of the substrate 10, and the second passivation anti-reflection layer 82 covers the back surface of the substrate 10, as well as the bottom and wall of the groove 30.

[0158] In some embodiments, the first passivation anti-reflection layer 81 includes a first passivation film and a first anti-reflection film that are stacked, and the first anti-reflection film is disposed on a surface of the first passivation film away from the substrate 10 .

[0159] In some embodiments, the material of the first passivation film includes aluminum oxide.

[0160] In some embodiments, the thickness of the first passivation film is 3 nm to 10 nm.

[0161] Optionally, the thickness of the first passivation film is 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm, or the thickness of the first passivation film may also be within a range between any two of the above thicknesses.

[0162] In some embodiments, the first passivation film is prepared by atomic layer deposition.

[0163] In some embodiments, a material of the first anti-reflection film includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0164] In some embodiments, the thickness of the first anti-reflection film is 70 nm to 110 nm.

[0165] Optionally, the thickness of the first anti-reflection film is 70 nm, 80 nm, 90 nm, 100 nm or 110 nm, or the thickness of the first anti-reflection film may also be within a range between any two of the above thicknesses.

[0166] In some embodiments, the refractive index of the first anti-reflection film is 2-2.4.

[0167] Optionally, the refractive index of the first anti-reflection film is 2, 2.1, 2.2, 2.3 or 2.4, or the refractive index of the first anti-reflection film may also be within a range between any two of the above reflectivities.

[0168] In some embodiments, the first anti-reflection film is prepared by plasma enhanced chemical vapor deposition.

[0169] In some embodiments, the second passivation anti-reflection layer 82 includes a second passivation film and a second anti-reflection film which are stacked, and the second anti-reflection film is disposed on a surface of the second passivation film away from the substrate 10 .

[0170] In some embodiments, the material of the second passivation film includes aluminum oxide.

[0171] In some embodiments, the second passivation film has a thickness of 3 nm to 10 nm.

[0172] Optionally, the thickness of the second passivation film is 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm, or the thickness of the second passivation film may also be within a range between any two of the above thicknesses.

[0173] In some embodiments, the second passivation film is prepared by atomic layer deposition.

[0174] In some embodiments, a material of the second anti-reflection film includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0175] In some embodiments, the second anti-reflection film has a thickness of 70 nm to 110 nm.

[0176] Optionally, the thickness of the second anti-reflection film is 70 nm, 80 nm, 90 nm, 100 nm or 110 nm, or the thickness of the second anti-reflection film may also be within a range between any two of the above thicknesses.

[0177] In some embodiments, the refractive index of the second anti-reflection film is 2-2.4.

[0178] Optionally, the refractive index of the second anti-reflection film is 2, 2.1, 2.2, 2.3 or 2.4, or the refractive index of the second anti-reflection film may also be within a range between any two of the above reflectivities.

[0179] In some embodiments, the first anti-reflection film is prepared by plasma enhanced chemical vapor deposition.

[0180] S50 : preparing a first electrode 91 and a second electrode 92 on the surface of the second passivation anti-reflection layer 82 , wherein the first electrode 91 is in electrical contact with the first doped silicon material layer 71 , and the second electrode 92 is in electrical contact with the second doped silicon material layer 72 .

[0181] Referring to FIG. 8 , FIG. 8 is a schematic diagram showing a structure in which a first electrode 91 and a second electrode 92 are formed on the basis of the structure shown in FIG. 7 .

[0182] In some embodiments, the first electrode 91 and the second electrode 92 are prepared by sintering silver paste.

[0183] In some embodiments, the sintering temperature is 700°C to 900°C.

[0184] Optionally, the sintering temperature is 700° C., 750° C., 800° C., 850° C. or 900° C., or the sintering temperature may also be within a range between any two of the above temperatures.

[0185] Yet another embodiment of the present application provides a solar cell, which is prepared by any of the above-mentioned methods for preparing a solar cell.

[0186] Referring again to FIG. 8 , in some embodiments, the solar cell includes a substrate 10 having a front side and a back side disposed opposite to each other, and the front side of the substrate 10 has a suede structure and is provided with a first passivation anti-reflection layer 81 ;

[0187] A groove 30 is formed on the back side of the substrate 10, and a tunneling oxide layer 40, an intrinsic silicon material layer 50 and a second passivation anti-reflection layer 82 are sequentially stacked in the groove 30;

[0188] The solar cell comprises a first region and a second region respectively located on opposite sides of the groove 30, a tunneling oxide layer 40, a first doped silicon material layer 71 and a second passivation anti-reflection layer 82 are sequentially stacked on the back surface of the substrate 10 located in the first region, and a tunneling oxide layer 40, a second doped silicon material layer 72 and a second passivation anti-reflection layer 82 are sequentially stacked on the back surface of the substrate 10 located in the second region, and the first doped silicon material layer 71 and the second doped silicon material layer 72 have opposite doping types;

[0189] The solar cell further includes a first electrode 91 and a second electrode 92 disposed on the second passivation anti-reflection layer 82 . The first electrode 91 is in electrical contact with the first doped silicon material layer 71 , and the second electrode 92 is in electrical contact with the second doped silicon material layer 72 .

[0190] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0191] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims, and the description and drawings may be used to interpret the contents of the claims.

Claims

1. A method for preparing a solar cell, characterized in that: The steps include: Providing a substrate having a front side and a back side disposed opposite to each other; forming a groove on the back side of the substrate; Preparing a tunneling oxide layer and an intrinsic silicon material layer stacked in sequence on the back side of the substrate; The intrinsic silicon material layer has a first region and a second region respectively located on opposite sides of the groove. The intrinsic silicon material layer in the first region is doped to obtain a first doped silicon material layer, and the intrinsic silicon material layer in the second region is doped to obtain a second doped silicon material layer. The doping types of the first doped silicon material layer and the second doped silicon material layer are opposite.

2. The method for preparing a solar cell according to claim 1, characterized in that: Doping the intrinsic silicon material layer in the first region to obtain a first doped silicon material layer, and doping the intrinsic silicon material layer in the second region to obtain a second doped silicon material layer comprises the following steps: Disposing a first slurry on the surface of the intrinsic silicon material layer in the first region, wherein the first slurry includes a first doping element; Disposing a second slurry on the surface of the intrinsic silicon material layer in the second region, wherein the second slurry includes a second doping element, and the first doping element and the second doping element have opposite doping types; The first slurry and the second slurry are used to dope the intrinsic silicon material layer through laser processing.

3. The method for preparing a solar cell according to claim 2, characterized in that: The laser processing satisfies at least one of the following characteristics: (1) The laser power of the laser treatment is 30W~80W; (2) The maximum width of the laser-processed spot is 100 μm to 300 μm; (3) The spot overlap rate of the laser treatment is less than 80%.

4. The method for preparing a solar cell according to claim 1, characterized in that: After doping the intrinsic silicon material layer in the first region to obtain a first doped silicon material layer and doping the intrinsic silicon material layer in the second region to obtain a second doped silicon material layer, the following steps are further included: The first doped silicon material layer and the second doped silicon material layer are subjected to hydrogen plasma treatment.

5. The method for preparing a solar cell according to claim 4, characterized in that: The hydrogen plasma treatment satisfies at least one of the following characteristics: (1) The pressure of the hydrogen plasma treatment is 1 Torr~2 Torr; (2) The temperature of the hydrogen plasma treatment is 150°C to 250°C; (3) The hydrogen plasma treatment time is 30s~200s.

6. The method for preparing a solar cell according to any one of claims 1 to 5, characterized in that: Forming a groove on the back side of the substrate comprises the following steps: preparing a mask layer on the back side of the substrate; An opening is formed on the mask layer by laser, and the groove is formed in the opening by laser.

7. The method for preparing a solar cell according to claim 6, characterized in that: After forming the groove in the opening, the method further includes the following steps: The sample after the groove is formed is subjected to a texturing treatment using an alkaline solution, so as to form a velvet structure on the front side of the substrate at the bottom of the groove.

8. The method for preparing a solar cell according to any one of claims 1 to 5, characterized in that: After doping the intrinsic silicon material layer in the first region to obtain a first doped silicon material layer and doping the intrinsic silicon material layer in the second region to obtain a second doped silicon material layer, the following steps are further included: A first passivation anti-reflection layer and a second passivation anti-reflection layer are respectively prepared on the front side and the back side of the substrate.

9. A solar cell, characterized in that: The solar cell is prepared by the method for preparing the solar cell according to any one of claims 1 to 8.

10. The solar cell according to claim 9, characterized in that: The invention comprises a substrate having a front side and a back side arranged opposite to each other, wherein the front side of the substrate has a suede structure and is provided with a first passivation anti-reflection layer; A groove is formed on the back side of the substrate, and a tunneling oxide layer, an intrinsic silicon material layer and a second passivation anti-reflection layer are sequentially stacked in the groove; The solar cell comprises a first region and a second region respectively located on opposite sides of the groove, the tunneling oxide layer, the first doped silicon material layer and the second passivation anti-reflection layer are sequentially stacked on the back side of the substrate located in the first region, the tunneling oxide layer, the second doped silicon material layer and the second passivation anti-reflection layer are sequentially stacked on the back side of the substrate located in the second region, and the first doped silicon material layer and the second doped silicon material layer have opposite doping types; The solar cell further includes a first electrode and a second electrode disposed on the second passivation anti-reflection layer, the first electrode being in electrical contact with the first doped silicon material layer, and the second electrode being in electrical contact with the second doped silicon material layer.

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