Preparation method of TOPCon solar cell

Abstract

The invention discloses a preparation method of a TOPCon solar cell. The preparation method comprises the following steps: S1, polishing the back surface of a silicon wafer; s2, depositing a tunneling oxide layer, a phosphorus-doped amorphous silicon layer and a mask layer on the back surface; s3, performing alkali texturing on the front surface; s4, depositing a tunneling oxide layer and an intrinsic amorphous silicon layer on the front side; s5, performing boron diffusion on the front surface, and synchronously crystallizing the phosphorus-doped amorphous silicon layer on the back surface to form a phosphorus-containing polycrystalline silicon layer; s6, carrying out laser crystallization; s7, removing the surface layer parts of the side surface BSG layer and the back surface mask layer; s8, removing the side boron diffusion layer, the front BSG layer and the residual mask layer; s9, double-sided film coating; and S10, carrying out silk-screen printing, sintering and light injection. According to the method, single-side texturing of the silicon wafer can be realized, and excessive internal expansion of phosphorus atoms caused by too high crystallization temperature can be avoided by matching low-temperature boron diffusion with laser crystallization. According to the method, the thickness of the silicon wafer is reduced slightly, the fragmentation rate of the silicon wafer in the preparation process is reduced, and the optical performance of the cell can be further improved.

Description

Technical Field

[0001] The invention relates to the field of solar cells, and in particular to a method for preparing a TOPCon solar cell. Background Art

[0002] Tunnel Oxide Passivating Contacts (TOPCon) solar cells are further upgraded from PERC (Passivated emitter and rear cell) solar cells. Their structure consists of an ultra-thin tunnel oxide layer and a doped polysilicon (poly-Si) layer. The silicon oxide between the interface of poly-Si and the substrate silicon can significantly reduce the interface state density between the substrate silicon and poly-Si through chemical passivation, reduce the recombination of the gold / semi-contact area, and effectively improve the photoelectric conversion efficiency of the cell. It is the representative of the mainstream N-type cell after the PERC cell.

[0003] However, there are many problems with existing TOPCon solar cells. First, due to the trend of thinning silicon wafers, the size of N-type silicon wafers has been reduced to ~130 μm. After multiple wet processes, the thickness of the silicon wafers will be further reduced, which will lead to further loss of the optical performance of the cell. Secondly, the preparation process of TOPCon solar cells is also relatively complicated, which increases the technical difficulty of cell production and performance improvement.

[0004] In summary, it is particularly critical to further reduce the thickness of silicon wafers during the preparation of TOPCon solar cells and simplify the preparation process of TOPCon solar cells to improve cell performance and reduce production costs. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a method for preparing TOPCon solar cells. The method of the present invention can realize single-sided texturing of silicon wafers, and the phosphorus-doped amorphous silicon layer on the back side can be synchronously crystallized and transformed into a phosphorus-containing polycrystalline silicon layer during the subsequent low-temperature boron diffusion process on the front side. In addition, the thickness of the silicon wafer is less thinned during the preparation process of the present invention, which is not only conducive to reducing the silicon wafer fragmentation rate during the preparation process, but also can further improve the optical performance of the battery.

[0006] The specific technical solution of the present invention is: a method for preparing a TOPCon solar cell, comprising the following steps: S1. The back of the N-type single crystal silicon wafer is polished on one side using a chain acid polishing machine. During the polishing process, only the back of the silicon wafer contacts the corrosive liquid, and the front side is not in contact with the corrosive liquid, so it is not affected by the corrosive liquid. The advantage of single-side polishing is that it can effectively reduce the loss of silicon wafer thickness during the preparation process.

[0007] S2. Depositing a tunnel oxide layer, a phosphorus-doped amorphous silicon layer, and a mask layer in sequence on the back side of the silicon wafer by PVD; wherein the phosphorus-doped amorphous silicon layer is deposited by using a phosphorus-containing silicon target.

[0008] The unique plate-type deposition method of PVD is adopted, and there is no problem of wrap-around plating of phosphorus-doped amorphous silicon layer on the front and sides in the process. Therefore, there is no need to remove the wrap-around layers on the front and sides in the subsequent process, which can reduce the preparation steps (in the conventional tubular LPCVD and PECVD deposition process, it is inevitable to generate wrap-around layers on the side and front of the silicon wafer at the same time, so an additional step is required to remove the wrap-around layers on the front and sides).

[0009] In addition, the mask layer needs to be thicker during the deposition process, mainly because: on the one hand, during the low-temperature boron diffusion process on the front side, it is necessary to prevent boron atoms from diffusing into the phosphorus-doped amorphous silicon layer on the back side; on the other hand, during the subsequent wet chain acid etcher to remove the side BSG layer, the back mask layer can only be partially removed simultaneously, and part of the mask layer must still be retained, otherwise the phosphorus-containing polysilicon layer on the back side will also be damaged during the subsequent alkaline cleaning process.

[0010] S3, alkali texturing on the front side of the silicon wafer. During the texturing process, the front side of the silicon wafer is etched with alkali to form a pyramid texture surface; while the back side of the silicon wafer is protected by a mask layer, which can block the etching of alkali, thus achieving the effect of single-sided texturing.

[0011] S4. Depositing a tunneling oxide layer and an intrinsic amorphous silicon layer in sequence on the front side of the silicon wafer.

[0012] S5. Place the silicon wafers back to back in a boron diffusion furnace and perform low-temperature boron diffusion on the front side at a temperature of <900°C, so that the inner layer and the surface layer of the intrinsic amorphous silicon layer are converted into a low crystallization rate boron diffusion layer and a BSG layer respectively. Due to the presence of the mask layer on the back side of the silicon wafer, the boron atoms can be effectively prevented from diffusing into the phosphorus-doped amorphous silicon layer on the back side during the boron diffusion process, and the layer is prevented from being inverted into a boron diffusion layer. At the same time, in the temperature environment of boron diffusion, the phosphorus-doped amorphous silicon layer on the back side of the silicon wafer can be crystallized and phosphorus atoms activated simultaneously, thereby being converted into a phosphorus-containing polysilicon layer.

[0013] It should be emphasized that the conventional boron diffusion process temperature is often high, usually >900°C. The present invention finds that the ideal temperature for synchronously transforming the back phosphorus-doped amorphous silicon into polysilicon needs to be <900°C; if the temperature is too high, on the one hand, it will cause the phosphorus atoms of the back phosphorus-doped amorphous silicon layer to excessively diffuse into the silicon substrate during the crystallization process, affecting the subsequent battery performance. On the other hand, too high a boron diffusion process temperature will also increase the risk of boron atoms penetrating the back mask layer into the phosphorus-doped amorphous silicon layer during the front boron diffusion process. The present invention uses a low-temperature boron diffusion process (<900°C) to effectively avoid this problem.

[0014] S6. Transform the low crystallization rate boron diffusion layer into a high crystallization rate boron diffusion layer by laser crystallization.

[0015] Since the present invention adopts a low-temperature boron diffusion process, only a low-crystallization-rate boron diffusion layer can be obtained. To this end, the present invention further improves the crystallization rate of the boron diffusion layer by laser crystallization. The advantages of laser crystallization are: (1) laser crystallization on the front side can prevent the phosphorus-doped polysilicon layer on the back side from being affected by secondary high temperature; (2) the low-temperature boron diffusion process on the front side can first transform the initial intrinsic amorphous silicon layer into a low-crystallization-rate polysilicon layer, and then only a lower laser power is needed to effectively transform this part into a high-crystallization-rate boron-diffused polysilicon layer, avoiding the problem of damage caused by high laser power.

[0016] S7, pickling to remove the surface of the BSG layer on the side of the silicon wafer and the mask layer on the back. Since the initial back mask layer is relatively thick, a portion of the back mask layer still exists when the BSG layer on the side of the silicon wafer is removed, so as to ensure that the phosphorus-containing polysilicon layer on the back of the silicon wafer is not damaged during the subsequent alkali etching of the side boron diffusion layer.

[0017] S8, alkaline washing to remove the boron diffusion layer on the side of the silicon wafer, and then acid washing to remove the BSG layer on the front of the silicon wafer and the residual mask layer on the back. After the boron diffusion, a boron diffusion layer will inevitably be formed on the side of the silicon wafer. Removing the side boron diffusion layer can reduce the impact of subsequent battery side leakage. Since there is a BSG layer on the front of the silicon wafer and a residual mask layer on the back, the front and back of the silicon wafer can be protected from damage during the alkaline polishing process. Then, the BSG layer on the front and the residual mask layer on the back are removed by acid washing.

[0018] S9, double-sided coating.

[0019] S10, screen printing, sintering, light injection, and obtaining TOPCon solar cells.

[0020] Preferably, in S1, the back side polishing specifically comprises: performing single-side back polishing on the silicon wafer in a chain acid polishing machine to reduce the weight by 0.1-0.2 g.

[0021] Preferably, the HF solution (concentration 45-55 wt%) and HNO in the acid tank of the chain acid polishing machine 3 The volume ratio of the solution (concentration 65~75 wt%) is 1:2~1:8; the temperature is room temperature, and the belt speed is 1~10 m / min.

[0022] Preferably, in S2, the deposition conditions of the tunnel oxide layer are: the RF power of the magnetron sputtering equipment is 100-200W, the reaction gas is O 2 , O 2The flow rate is 300~500 sccm, the reaction chamber temperature is 300~400℃, the tunneling oxide layer is formed by oxygen ionization, the reaction time is 20~100 s, and the growth thickness is 1~5 nm.

[0023] Preferably, in S2, the deposition conditions of the phosphorus-doped amorphous silicon layer are: using a phosphorus-containing silicon target, a power of 30000-40000 W, and a reaction gas of Ar, PH 3 , Ar:PH 3 Flow rate = 1:1~5:1 sccm, chamber temperature 200~300℃, reaction time 1000~8000 s, growth thickness 100~500 nm.

[0024] Preferably, in S2, the deposition conditions of the mask layer are: using pure silicon target material, and the reaction gas is Ar, O 2 , Ar:O 2 Flow rate = 2:1~6:1 sccm, chamber temperature 200~300℃, reaction time 800~3000 s, growth thickness 100~300nm.

[0025] Since the mask layer plays an important blocking role in the subsequent process, the thickness of this layer is relatively large.

[0026] Preferably, S3 specifically includes: immersing the silicon wafer in an alkaline solution for texturing for 6 to 9 minutes at a temperature of 75 to 85°C; after the alkaline texturing, a positive pyramid texturing surface (1 to 2 μm) is formed on the front side of the silicon wafer, with a reflectivity of 9 to 10% and a weight loss of 0.15 to 0.25 g.

[0027] Preferably, S4 specifically includes: depositing a tunnel oxide layer on the front side of the silicon wafer after texturing by using LPCVD method, 2 Flow rate 10000~80000 sccm, temperature 400~800℃, time 200~1000 s, tunnel oxide layer thickness 2~10 nm; deposit intrinsic amorphous silicon layer on the tunnel oxide layer: SiH 4 Flow rate 300~2000 sccm, temperature 500~700℃, time 2~4 h, working gas pressure 100~500 mTorr, intrinsic amorphous silicon layer thickness 100~300 nm.

[0028] Preferably, in S5, the conditions for the low-temperature boron diffusion are: temperature 800-860°C, time 20-80 min, BCl 3 Gas flow rate 100~1000 sccm, O 2 Gas flow rate 1000~3000 sccm; oxidation advancement temperature 860~895℃, O 2Gas flow rate is 5000~80000 sccm, advancement time is 50~100 min, and BSG thickness is 20~50 nm.

[0029] During the above low-temperature boron diffusion process, the back phosphorus-doped amorphous silicon layer is synchronously crystallized into a phosphorus-containing polycrystalline silicon layer. Since the temperature during conventional front boron diffusion is often high (>900°C), and the temperature required for the back phosphorus-doped amorphous silicon layer to be transformed into phosphorus-doped polycrystalline silicon is relatively low (<900°C), if the conventional boron diffusion process is used directly, on the one hand, it will cause the phosphorus atoms of the back phosphorus-doped amorphous silicon layer to excessively diffuse into the silicon substrate during the crystallization process, affecting the subsequent battery performance. On the other hand, too high a boron diffusion process temperature will also increase the risk of boron atoms penetrating the back mask layer and entering the phosphorus-doped amorphous silicon layer during the front boron diffusion process. The present invention uses a low-temperature boron diffusion process (<900°C) to effectively avoid this problem.

[0030] Preferably, in S5, the crystallization rate of the low crystallization rate boron diffusion layer is 20-70%.

[0031] Preferably, in S6, the conditions for laser crystallization are: laser wavelength 400-600 nm, pulse time 10-20 ns, frequency 10-20 KHz, power 1-10 W, time 1-20 s; and the crystallization rate of the high crystallization rate boron diffusion layer is 70-90%.

[0032] Preferably, S7 specifically includes: using a chain acid etcher to remove the BSG layer formed on the side of the silicon wafer during the boron diffusion process and the surface portion of the back mask layer with the front side of the silicon wafer facing upward, the concentration of the HF solution in the chain acid etcher is 20-80wt%, and the belt speed is 0.5-5 m / min.

[0033] Preferably, S8 specifically includes: placing the silicon wafer in an alkaline solution to remove the side boron diffusion layer at a temperature of 75-85° C. for 3-7 min; then acid-washing the silicon wafer to remove the front BSG layer and the residual mask layer on the back.

[0034] Compared with the prior art, the beneficial effects of the present invention are: (1) Compared with the conventional TOPCon solar cell preparation process, the method of the present invention can realize single-sided texturing of silicon wafers, and the phosphorus-doped amorphous silicon layer on the back side can be synchronously crystallized and transformed into a phosphorus-containing polycrystalline silicon layer during the subsequent low-temperature boron diffusion process on the front side.

[0035] (2) The method of the present invention reduces the thickness of the silicon wafer less during the preparation process, which is not only beneficial to reducing the silicon wafer fragmentation rate during the preparation process, but also can further improve the optical performance of the battery.

[0036] (3) The present invention adopts a method of low-temperature boron diffusion combined with laser crystallization, which can not only construct a high crystallization rate boron diffusion layer, but also prevent the excessive diffusion of phosphorus atoms into the silicon substrate due to the high crystallization temperature of the back phosphorus-doped amorphous silicon layer, thereby affecting the subsequent battery performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Schematic diagram of the structure after single-sided back polishing of the silicon wafer.

[0038] Figure 2 Schematic diagram of the structure after the tunneling oxide layer / phosphorus-doped amorphous silicon layer / mask layer are deposited on the back of the silicon wafer.

[0039] Figure 3 This is a schematic diagram of the structure of the silicon wafer after texturing.

[0040] Figure 4 This is a schematic diagram of the structure after low-temperature boron diffusion on the front side of the silicon wafer and crystallization of the phosphorus-doped amorphous silicon layer on the back side.

[0041] Figure 5 Schematic diagram of the structure of silicon wafer after laser crystallization.

[0042] Figure 6 Schematic diagram of the structure after the side boron diffusion layer is removed by alkali polishing of the silicon wafer.

[0043] Figure 7 Schematic diagram of the structure of TOPCon solar cell.

[0044] The reference numerals in the drawings are: N-type single crystal silicon wafer 1, tunneling oxide layer 2, phosphorus-doped amorphous silicon layer 3, mask layer 4, pyramid velvet 5, low crystallization rate boron diffusion layer 6, BSG layer 7, phosphorus-containing polysilicon layer 8, high crystallization rate boron diffusion layer 9, passivation anti-reflection layer 10, and electrode layer 11. DETAILED DESCRIPTION

[0045] The present invention will be further described below in conjunction with the embodiments.

[0046] A method for preparing a TOPCon solar cell comprises the following steps: S1. The back side of the N-type monocrystalline silicon wafer is polished on one side using a chain acid polishing machine. During the polishing process, only the back side of the silicon wafer contacts the corrosive liquid, and the front side faces upward and does not contact the corrosive liquid, so it is not affected by the corrosive liquid.

[0047] In some preferred implementation cases, in S1, the back side polishing specifically includes: performing single-side back polishing on the silicon wafer in a chain acid polishing machine to reduce the weight by 0.1-0.2 g.

[0048] In some more preferred implementation cases, the HF solution (concentration 45-55wt%) and HNO in the acid tank of the chain acid polishing machine 3The volume ratio of the solution (concentration 65~75 wt%) is 1:2~1:8; the temperature is room temperature, and the belt speed is 1~10 m / min.

[0049] S2. Depositing a tunnel oxide layer, a phosphorus-doped amorphous silicon layer, and a mask layer in sequence on the back side of the silicon wafer by PVD; wherein the phosphorus-doped amorphous silicon layer is deposited by using a phosphorus-containing silicon target.

[0050] The unique plate-type deposition method of PVD is adopted, and there is no problem of wrapping around the phosphorus-doped amorphous silicon layer on the front and side. Therefore, there is no need to remove the wrapping around the front and side in the subsequent process, which can reduce the preparation steps. (In the conventional tubular LPCVD and PECVD deposition process, wrapping around the silicon wafer will inevitably generate wrapping around the side and front of the silicon wafer, so an additional step is required to remove the wrapping around the front and side).

[0051] In addition, the mask layer needs to be thicker during the deposition process, mainly because: on the one hand, during the boron diffusion process on the front side, it is necessary to prevent boron atoms from diffusing into the phosphorus-doped amorphous silicon layer on the back side; on the other hand, during the subsequent wet chain acid etcher to remove the side BSG layer, the back mask layer can only be partially removed simultaneously, and part of the mask layer must still be retained, otherwise the phosphorus-containing polysilicon layer on the back side will also be damaged during the subsequent alkaline cleaning process.

[0052] In some preferred implementation cases, in S2, the deposition conditions of the tunnel oxide layer are: the RF power of the magnetron sputtering equipment is 100-200 W, the reaction gas is O 2 , O 2 The flow rate is 300~500 sccm, the reaction chamber temperature is 300~400℃, the tunneling oxide layer is formed by oxygen ionization, the reaction time is 20~100 s, and the growth thickness is 1~5 nm.

[0053] In some preferred implementation cases, in S2, the deposition conditions of the phosphorus-doped amorphous silicon layer are: using a phosphorus-containing silicon target, a power of 30000-40000 W, and a reaction gas of Ar, PH 3 , Ar:PH 3 Flow rate = 1:1~5:1 sccm, chamber temperature 200~300℃, reaction time 1000~8000 s, growth thickness 100~500 nm.

[0054] In some preferred implementation cases, in S2, the deposition conditions of the mask layer are: using a pure silicon target material, and the reaction gases are Ar, O 2 , Ar:O 2 Flow rate = 2:1~6:1 sccm, chamber temperature 200~300℃, reaction time 800~3000 s, growth thickness 100~300 nm.

[0055] S3, alkali texturing on the front side of the silicon wafer. During the texturing process, the front side of the silicon wafer is etched with alkali to form a pyramid texture surface; while the back side of the silicon wafer is protected by a mask layer, which can block the etching of alkali, thus achieving the effect of single-sided texturing.

[0056] In some preferred implementation cases, S3 specifically includes: immersing the silicon wafer in an alkaline solution for texturing for 6 to 9 minutes at a temperature of 75 to 85°C; after the alkaline texturing, a positive pyramid texturing surface (1 to 2 μm) is formed on the front side of the silicon wafer, with a reflectivity of 9 to 10% and a weight loss of 0.15 to 0.25 g.

[0057] S4. Depositing a tunneling oxide layer and an intrinsic amorphous silicon layer in sequence on the front side of the silicon wafer.

[0058] In some preferred implementation cases, S4 specifically includes: depositing a tunnel oxide layer on the front side of the textured silicon wafer by LPCVD, 2 Flow rate 10000~80000 sccm, temperature 400~800℃, time 200~1000 s, tunnel oxide layer thickness 2~10 nm; deposit intrinsic amorphous silicon layer on the tunnel oxide layer: SiH 4 Flow rate 300~2000 sccm, temperature 500~700℃, time 2~4 h, working gas pressure 100~500 mTorr, intrinsic amorphous silicon layer thickness 100~300 nm.

[0059] S5. Place the silicon wafers back to back in a boron diffusion furnace for front boron diffusion, so that the inner layer and the surface layer of the intrinsic amorphous silicon layer are converted into a low crystallization rate boron diffusion layer and a BSG layer respectively; and due to the presence of the mask layer on the back of the silicon wafer, during the boron diffusion process, the boron atoms can be effectively prevented from diffusing into the phosphorus-doped amorphous silicon layer on the back, preventing the layer from being inverted into a boron diffusion layer. At the same time, in the temperature environment of boron diffusion, the phosphorus-doped amorphous silicon layer on the back of the silicon wafer can be crystallized and phosphorus atoms activated simultaneously, thereby being converted into a phosphorus-containing polysilicon layer.

[0060] In some preferred implementation cases, in S5, the conditions for the low temperature boron diffusion are: temperature 800-860°C, time 20-80 min, BCl 3 Gas flow rate 100~1000 sccm, O 2 Gas flow rate 1000~3000 sccm; oxidation advancement temperature 860~895℃, O 2 Gas flow rate is 5000~80000 sccm, advancement time is 50~100 min, and BSG thickness is 20~50 nm.

[0061] In some preferred implementation cases, in S5, the crystallization rate of the low crystallization rate boron diffusion layer is 20-70%.

[0062] S6. Transform the low crystallization rate boron diffusion layer into a high crystallization rate boron diffusion layer by laser crystallization.

[0063] Since the present invention adopts a low-temperature boron diffusion process, only a low-crystallization-rate boron diffusion layer can be obtained. To this end, the present invention further improves the crystallization rate of the boron diffusion layer by laser crystallization. The advantages of laser crystallization are: (1) laser crystallization on the front side can prevent the phosphorus-doped polysilicon layer on the back side from being affected by secondary high temperature; (2) the low-temperature boron diffusion process on the front side can first transform the initial intrinsic amorphous silicon layer into a low-crystallization-rate polysilicon layer, and then only a lower laser power is needed to effectively transform this part into a high-crystallization-rate boron-diffused polysilicon layer, avoiding the problem of damage caused by high laser power.

[0064] In some preferred implementation cases, in S6, the conditions of the laser crystallization are: laser wavelength 400~600 nm, pulse time 10~20 ns, frequency 10~20 KHz, power 1~10 W, time 1~20 s; the crystallization rate of the high crystallization rate boron diffusion layer is 70~90%.

[0065] S7, remove the surface layer of the BSG layer on the side of the silicon wafer and the surface layer of the back mask layer. Since the initial back mask layer is relatively thick, a portion of the back mask layer still exists when the BSG layer on the side of the silicon wafer is removed, so as to ensure that the phosphorus-containing polysilicon layer on the back of the silicon wafer is not damaged during the subsequent alkali etching of the side boron diffusion layer.

[0066] In some preferred implementation cases, S7 specifically includes: removing the BSG layer formed on the side of the silicon wafer and the surface portion of the back mask layer by a chain acid etcher with the front side of the silicon wafer facing upward; wherein the concentration of the HF solution in the chain acid etcher is 20-80 wt%, and the belt speed is 0.5-5 m / min.

[0067] S8, alkaline washing to remove the boron diffusion layer on the side of the silicon wafer, and then acid washing to remove the BSG layer on the front of the silicon wafer and the residual mask layer on the back. After the boron diffusion, a boron diffusion layer will inevitably be formed on the side of the silicon wafer. Removing the side boron diffusion layer can reduce the impact of subsequent battery side leakage. Since there is a BSG layer on the front of the silicon wafer and a residual mask layer on the back, the front and back of the silicon wafer can be protected from damage during the alkaline polishing process. Then, the BSG layer on the front and the residual mask layer on the back are removed by acid washing.

[0068] In some preferred implementation cases, S8 specifically includes: placing the silicon wafer in an alkaline solution to remove the side boron diffusion layer, the temperature is 75-85° C., and the time is 3-7 min; then the silicon wafer is pickled to remove the front BSG layer and the residual mask layer on the back.

[0069] S9, double-sided coating: ALD deposition is used to deposit AlO on both sides of the processed silicon wafer x The film is composed of Al(CH3 ) 3 It reacts with water vapor to form a thickness of 8-10 nm, and the process temperature is controlled at 220-280°C. Then, SiN is deposited on both sides of the silicon wafer using a tubular PECVD device. x The film has a thickness of 80-120 nm and a refractive index of 1.9-2.1. The reaction gas in the tubular cavity is SiH 4 NH 3 , working pressure is 1500~1700 mTorr, power is 10000~15000 W, temperature is 400~600℃, SiH 4 The gas flow rate is 900~2000 sccm, NH 3 The gas flow rate is 7000~12000 sccm and the deposition time is 5~20 min.

[0070] S10, screen-print the coated silicon wafer on the back to form metal contact, then sinter at 700~800℃ to form Ag-Si ohmic contact, and finally perform light injection repair to obtain the final TOPCon finished solar cell.

[0071] Specific examples and comparative examples.

[0072] Example 1 A method for preparing a TOPCon solar cell comprises the following steps: S1, single-sided polishing of the back side of the N-type single crystal silicon wafer 1, such as Figure 1 As shown. Specifically, the N-type single crystal silicon wafer is polished on the back of a single side in a chain acid polishing machine, and the weight loss is 0.15 g. In the above process, only the back side of the silicon wafer contacts the etching liquid during polishing, and the front side is not in contact with the etching liquid, so it is not affected by the etching liquid. Among them, the HF solution (concentration 49 wt%) and HNO in the acid tank of the chain acid polishing machine 3 The volume ratio of the solution (concentration 69 wt%) was 1:4; the temperature was room temperature, and the belt speed was 1.3 m / min.

[0073] S2, depositing a tunnel oxide layer 2, a phosphorus-doped amorphous silicon layer 3, and a mask layer 4 on the back of the silicon wafer in sequence by PVD, such as Figure 2 Specifically, the deposition conditions of the tunnel oxide layer are as follows: the RF power of the magnetron sputtering equipment is 170 W, the reaction gas is O 2 , O 2 The flow rate was 360 sccm, the reaction chamber temperature was 360°C, the tunnel oxide layer was formed by oxygen ionization, the reaction time was 60 s, and the growth thickness was about 3 nm. The deposition conditions of the phosphorus-doped amorphous silicon layer were: using a phosphorus-containing silicon target, a power of 37000 W, and the reaction gases were Ar, PH 3 , Ar:PH3 Flow rate = 3:1 sccm, chamber temperature 230°C, reaction time 4500 s, growth thickness about 280 nm. The deposition conditions of the mask layer are: pure silicon target material, reaction gas is Ar, O 2 , Ar:O 2 Flow rate = 4:1 sccm, chamber temperature 280 °C, reaction time 2300 s, growth thickness about 220 nm.

[0074] S3, immerse the silicon wafer in an alkaline solution for texturing for 7 min at a temperature of 82°C. After the alkaline texturing, a positive pyramid texture surface 5 (1.2 μm) is formed on the front of the silicon wafer, with a reflectivity of 9.3% and a weight loss of 0.17 g. Figure 3 shown.

[0075] S4, sequentially depositing a tunneling oxide layer and an intrinsic amorphous silicon layer on the front side of the silicon wafer, specifically comprising: depositing a tunneling oxide layer on the front side of the silicon wafer after texturing by using an LPCVD method, 2 Flow rate 40000 sccm, temperature 600℃, time 600 s, tunnel oxide layer thickness is about 3 nm; deposit intrinsic amorphous silicon layer on the tunnel oxide layer: SiH 4 The flow rate is 920 sccm, the temperature is 550℃, the time is 3.3 h, the working pressure is 300 mTorr, and the thickness of the intrinsic amorphous silicon layer is about 290 nm.

[0076] S5. Place the silicon wafers back to back in a boron diffusion furnace for low-temperature boron diffusion on the front side, so that the inner layer and the surface layer of the intrinsic amorphous silicon layer are converted into a low-crystallization-rate boron diffusion layer 6 and a BSG layer 7, respectively. Due to the presence of the mask layer 4 on the back side of the silicon wafer, the boron atoms can be effectively prevented from diffusing into the phosphorus-doped amorphous silicon layer on the back side during the boron diffusion process, thereby preventing the layer from being inverted into a boron diffusion layer. At the same time, in the temperature environment of boron diffusion, the phosphorus-doped amorphous silicon layer on the back side of the silicon wafer can be crystallized and phosphorus atoms activated simultaneously, thereby being converted into a phosphorus-containing polycrystalline silicon layer 8 (such as Figure 4 The conditions for boron diffusion are as follows: temperature 820°C, time 50 min, BCl 3 Gas flow rate: 300 sccm, O 2 Gas flow rate 2000 sccm; oxidation push temperature 890℃, O 2 The gas flow rate was 9500 sccm, the push time was 60 min, and the BSG thickness was 47 nm. The crystallization rate of the obtained low crystallization rate boron diffusion layer was about 63%.

[0077] S6, transforming the low crystallization rate boron diffusion layer into a high crystallization rate boron diffusion layer 9 by laser crystallization, such as Figure 5The conditions of laser crystallization are: laser wavelength 532 nm, pulse time 12 ns, frequency 15 KHz, power 8 W, time 5 s; the crystallization rate of the high crystallization rate boron diffusion layer is about 89%.

[0078] S7. With the front side of the silicon wafer facing upward, a chain acid etcher is used to remove the BSG layer formed on the side of the silicon wafer during the boron diffusion process and the surface portion of the mask layer on the back side; wherein the concentration of the HF solution in the chain acid etcher is 40 wt% and the belt speed is 3 m / min.

[0079] S8, alkaline washing to remove the boron diffusion layer on the side of the silicon wafer, and then acid washing to remove the BSG layer 7 on the front side of the silicon wafer and the residual mask layer on the back side, such as Figure 6 Specifically, the process includes: placing the silicon wafer in an alkaline solution at a temperature of 75°C for 5 minutes to remove the side boron diffusion layer; then the silicon wafer is pickled to remove the front BSG layer and the residual mask layer on the back.

[0080] S9, double-sided coating to form a passivation anti-reflection layer 10: Atomic layer deposition ALD is used to deposit AlO on both sides of the processed silicon wafer x The film is composed of Al(CH 3 ) 3 It reacts with water vapor to form a layer with a thickness of about 8 nm. The process temperature is controlled at 250°C. Then, SiN is deposited on both sides of the silicon wafer using a tubular PECVD device. x Thin film, SiN x The film thickness is about 90 nm and the refractive index is 2.0. x The reaction gas in the tube chamber is SiH 4 NH 3 , operating pressure 1600 mTorr, power 12000 W, temperature 440°C, SiH 4 The gas flow rate is 980 sccm, NH 3 The gas flow rate was 8000 sccm and the deposition time was 10 min.

[0081] S10, screen-print the coated silicon wafer on the back to form a metal contact (electrode layer 11), then sinter at 780°C to form an Ag-Si ohmic contact, and finally perform light injection repair to obtain the final TOPCon finished solar cell, the structure of which is as follows Figure 7 shown.

[0082] Example 2 The difference between Example 2 and Example 1 is that in S2 (the rest of the steps are the same), a tunneling oxide layer, a phosphorus-doped amorphous silicon layer, and a mask layer are sequentially deposited on the back of the silicon wafer by plate-type PECVD. The specific conditions are: the deposition conditions of the tunneling oxide layer are: the power is 9500 W, the reaction gas is N2 O, with a flow rate of 20000 sccm, a temperature of 450°C, a time of 300 s, and a working pressure of 1800 mTorr. The thickness of the generated tunnel oxide layer is about 3 nm. The deposition conditions of the phosphorus-doped amorphous silicon layer are: PH 3 Flow rate 1700 sccm, SiH 4 Flow rate 2300 sccm, H 2 The flow rate is 7000 sccm, the temperature is 460℃, the time is 18 min, and the working pressure is 2200 mTorr. The thickness of the generated boron-doped amorphous silicon layer is about 280 nm. The deposition conditions of the mask layer are: SiH 4 Flow rate 2500 sccm, N 2 The O flow rate was 9300 sccm, the temperature was 460°C, the time was 15 min, the working pressure was 2700 mTorr, and the mask layer thickness was about 220 nm.

[0083] Example 3 The difference between Example 3 and Example 1 is that in S7 and S8 (the rest of the steps are the same), the boron diffusion layer on the side of the silicon wafer is removed by laser de-plating. The specific conditions are: S7, stack multiple silicon wafers obtained in S6 in layers. After the stacking, the front of the lower silicon wafer is attached to the back of the upper silicon wafer, and the four sides of all silicon wafers are flush after the stacking. Then, the BSG layer on the four sides of all silicon wafers after the stacking is processed in sequence by laser. After the laser processing of one side, the stacked silicon wafer can be rotated 90° clockwise and the BSG layer of the next side is processed immediately, and a total of 4 sides are processed in sequence; the laser conditions are: using picosecond laser, laser wavelength 532 nm, frequency 600 KHz, marking speed 45000 mm / s, power 50 W, processing time 3 s.

[0084] S8. The laser-treated silicon wafer is placed in an alkaline solution for cleaning at a temperature of 75°C to remove the side boron diffusion layer. Since there is a BSG layer on the front side of the silicon wafer and a mask layer on the back side, the front side and back side of the silicon wafer can be protected from damage during the alkaline polishing process. The front side BSG layer and the back side mask layer are then removed by acid washing.

[0085] Comparative Example 1 Comparative Example 1 adopts a standard TOPCon battery process, which specifically includes the following steps: S1. Perform double-sided alkali texturing on the cut N-type single crystal silicon wafer, wherein the alkali concentration is 1.7 wt%, the temperature is 80°C, the time is 7 min, and the weight loss is 0.36 g, thereby forming a pyramid texture surface on both the front and back sides of the silicon wafer.

[0086] S2, sequentially depositing a tunneling oxide layer and an intrinsic amorphous silicon layer on the front side of the silicon wafer, specifically comprising: depositing a tunneling oxide layer on the front side of the silicon wafer after texturing by using an LPCVD method, 2 Flow rate 40000 sccm, temperature 600℃, time 600 s, tunnel oxide layer thickness is about 3 nm; deposit intrinsic amorphous silicon layer on the tunnel oxide layer: SiH 4 The flow rate is 920 sccm, the temperature is 550℃, the time is 3.3 h, the working pressure is 300 mTorr, and the thickness of the intrinsic amorphous silicon layer is about 290 nm.

[0087] S3, generate a boron diffusion layer and a BSG layer on the front side of the silicon wafer. The conditions for boron diffusion are: boron diffusion temperature 930℃, diffusion time 25 min, BCl 3 Gas flow rate: 200 sccm, O 2 Gas flow rate 1200 sccm, oxidation push temperature 1050℃, O 2 The gas flow rate was 20000 sccm, the advancement time was 60 min, and the thickness of the obtained BSG layer was about 48 nm.

[0088] S4. With the front side of the silicon wafer facing upward, a chain acid etcher is used to remove the BSG layer formed on the side and back of the silicon wafer during the boron diffusion process; wherein the concentration of the HF solution in the chain acid etcher is 40 wt% and the belt speed is 3 m / min.

[0089] S5. Alkaline polishing is then used to remove the boron diffusion layer on the side and back of the silicon wafer, and at the same time, a relatively flat polishing surface is formed on the back of the silicon wafer to pave the way for the subsequent deposition of the phosphorus-doped amorphous silicon layer; the alkaline polishing conditions are: 2.0wt%, temperature 75℃, time 5 min, and weight loss of 0.27 g; during the process, due to the presence of a BSG layer on the front of the silicon wafer, the boron diffusion layer at the bottom of the BSG layer can be effectively protected from being destroyed by the alkaline solution.

[0090] S6. Using PECVD to deposit a tunnel oxide layer, a phosphorus-doped amorphous silicon layer, and a mask layer on the back of the polished silicon wafer in sequence; the deposition conditions of the tunnel oxide layer are: power 9500 W, reaction gas N 2 O, with a flow rate of 20000sccm, a temperature of 450℃, a time of 300 s, and a working pressure of 1800 mTorr. The thickness of the generated tunnel oxide layer is about 3nm. The deposition conditions of the phosphorus-doped amorphous silicon layer are: PH 3 Flow rate 1700 sccm, SiH 4 Flow rate 2300 sccm, H 2The flow rate is 7000sccm, the temperature is 460℃, the time is 18 min, the working pressure is 2200 mTorr, and the thickness of the boron-doped amorphous silicon layer is about 280nm. During the process, due to the presence of the BSG layer on the front side of the silicon wafer, phosphorus atoms can be effectively blocked from diffusing into the boron diffusion layer, preventing the layer from being inverted. The deposition conditions of the mask layer are: SiH 4 Flow rate 2500 sccm, N 2 The O flow rate was 9300 sccm, the temperature was 460°C, the time was 15 min, the working pressure was 2700 mTorr, and the mask layer thickness was about 220 nm.

[0091] S7, then high temperature crystallization of the silicon wafer is performed to transform the phosphorus-doped amorphous silicon into a phosphorus-containing polycrystalline silicon layer, wherein the high temperature crystallization conditions are: N 2 The flow rate is 5000 sccm, the temperature is 890°C, and the time is 55 min.

[0092] S8. With the back side of the silicon wafer facing upward, a chain acid etcher is used to remove the mask layer formed on the front and side surfaces of the silicon wafer during the deposition of phosphorus-doped amorphous silicon, wherein the concentration of the HF solution in the chain acid etcher is 30 wt% and the belt speed is 5 m / min.

[0093] S9, then put the silicon wafer with the front and side mask layers removed into the alkaline polishing solution again for de-wrapping treatment, where the alkaline concentration is 2.2 wt%, the temperature is 72°C, the time is 4 min, and the weight loss is 0.017 g; during the process, due to the presence of a BSG layer on the front of the silicon wafer and a mask layer on the back, the boron diffusion layer and the phosphorus-containing polysilicon layer can be effectively protected from being damaged by the alkaline solution. Then, the front BSG layer and the back mask layer are removed by pickling.

[0094] S10, using atomic layer deposition ALD method to deposit AlO on both sides of the processed silicon wafer x The film is composed of Al(CH 3 ) 3 It reacts with water vapor to form a layer with a thickness of about 8 nm. The process temperature is controlled at 250°C. Then, SiN is deposited on both sides of the silicon wafer using a tubular PECVD device. x Thin film, SiN x The film thickness is about 90 nm and the refractive index is 2.0. x The reaction gas in the tube chamber is SiH 4 NH 3 , operating pressure 1600 mTorr, power 12000 W, temperature 440°C, SiH 4 The gas flow rate is 980 sccm, NH 3 The gas flow rate was 8000 sccm and the deposition time was 10 min.

[0095] S11. The coated silicon wafer is screen-printed on the back to form a metal contact, and then sintered at 780°C to form an Ag-Si ohmic contact. Finally, it is repaired by light injection to obtain the final TOPCon finished solar cell.

[0096] Comparative Example 2 The only difference between Comparative Example 2 and Example 1 is that during the S5 low-temperature boron diffusion process, the temperature is too low, resulting in a low crystallization rate of the phosphorus-doped amorphous silicon layer to transform into a phosphorus-containing polycrystalline silicon layer, thereby causing a decrease in battery performance.

[0097] The specific conditions are: S5, low temperature boron diffusion conditions are: temperature 780℃, time 25 min, BCl 3 Gas flow rate: 300 sccm, O 2 Gas flow rate: 1500 sccm; oxidation push temperature: 850℃, O 2 The gas flow rate was 10000 sccm, the push time was 70 min, and the BSG thickness was about 39 nm.

[0098] Comparative Example 3 The only difference between Comparative Example 3 and Example 1 is that the S6 laser crystallization step is not included, and S5 adopts a high-temperature boron diffusion process. During the high-temperature boron diffusion process, the temperature is too high, resulting in a large number of phosphorus atoms diffusing into the silicon substrate during the transformation of the phosphorus-doped amorphous silicon layer into the phosphorus-containing polycrystalline silicon layer, thereby causing the battery performance to deteriorate.

[0099] The specific conditions are: S5, high temperature boron diffusion conditions are: temperature 910℃, time 25 min, BCl 3 Gas flow rate: 300 sccm, O 2 Gas flow rate: 1500 sccm; oxidation push temperature: 1070℃, O 2 The gas flow rate was 10000 sccm, the push time was 70 min, and the BSG thickness was about 60 nm.

[0100] Performance comparison The TOPCon solar cells prepared in the above-mentioned embodiments and comparative examples were subjected to various performance tests, and the results are shown in the following table:

[0101] From the comparison of the data in the above table, we can see that: Firstly, for Example 1, since a single-sided texturing method is adopted, the thinning amount of the silicon wafer is small, and the optical performance of the battery is further improved.

[0102] Secondly, low-temperature boron diffusion combined with laser crystallization is used to process the boron-doped amorphous silicon layer on the front side. On the one hand, during the low-temperature boron diffusion process on the front side, since the process temperature perfectly matches the temperature required for the transformation of the phosphorus-doped amorphous silicon layer on the back side into the phosphorus-doped polycrystalline silicon layer, the phosphorus-doped amorphous silicon layer on the back side can be crystallized simultaneously. On the other hand, laser crystallization can repair the problem of low crystallization rate of the boron diffusion layer on the front side caused by the initial low temperature, while avoiding the influence of secondary high temperature on the back side, so the overall battery performance is optimal.

[0103] For Example 2 and Example 3, another method for depositing phosphorus-doped amorphous silicon using plate-type PECVD single-sided non-wrap-around plating and a method for removing the side boron diffusion layer by laser are provided respectively. Both methods can also prepare TOPCon cells with better performance, but the performance is slightly lower than that of Example 1.

[0104] For Comparative Example 1, since the conventional tubular PECVD method is used to deposit phosphorus-doped amorphous silicon, the process requires multiple wet steps such as double-sided texturing, back polishing, front and side plating, and an additional back high-temperature crystallization process. The overall process is more complicated, and the amount of silicon wafer thinning is also large, which affects the performance of the battery, which is lower than that of Examples 1-3.

[0105] For Comparative Example 2, due to the low temperature of the boron diffusion process, the phosphorus-doped amorphous silicon layer on the back of the silicon wafer cannot be fully transformed into a phosphorus-containing polycrystalline silicon layer, resulting in a large parasitic absorption of light by this layer, which also affects the subsequent gold / semiconductor contact performance, resulting in lower overall performance.

[0106] For Comparative Example 3, due to the high temperature of the boron diffusion process, the phosphorus atoms severely diffused into the silicon substrate during the process of converting the phosphorus-doped amorphous silicon on the back side of the silicon wafer into the phosphorus-containing polycrystalline silicon layer. This not only aggravated the carrier recombination rate on the back side of the silicon wafer, but also the back mask layer could not effectively block the boron atoms from entering the phosphorus-containing polycrystalline silicon layer on the back side during the boron diffusion process, resulting in the lowest battery performance.

[0107] The raw materials and equipment used in the present invention, unless otherwise specified, are all commonly used raw materials and equipment in the art; the methods used in the present invention, unless otherwise specified, are all conventional methods in the art.

[0108] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any simple modification, change and equivalent transformation made to the above embodiment based on the technical essence of the present invention still falls within the protection scope of the technical solution of the present invention.

Claims

1. A method for preparing a TOPCon solar cell, characterized in that include: S1, silicon wafer backside polishing; S2, depositing a tunnel oxide layer, a phosphorus-doped amorphous silicon layer, and a mask layer on the back of the silicon wafer by PVD; S3, front alkali velveting; S4, depositing a tunnel oxide layer and an intrinsic amorphous silicon layer on the front side; S5, low-temperature boron diffusion on the front side at <900°C to form a low-crystallization-rate boron diffusion layer and a BSG layer, and the phosphorus-doped amorphous silicon layer on the back side is synchronously crystallized into a phosphorus-containing polysilicon layer; S6, laser crystallizing the low crystallization rate boron diffusion layer to convert it into a high crystallization rate boron diffusion layer; S7, pickling to remove the surface portion of the BSG layer on the side of the silicon wafer and the mask layer on the back; S8, alkaline washing to remove the boron diffusion layer on the side of the silicon wafer, and then acid washing to remove the BSG layer on the front side of the silicon wafer and the residual mask layer on the back side; S9, double-sided coating; S10, screen printing, sintering, light injection.

2. The preparation method according to claim 1, characterized in that: In S1, the back side polishing specifically includes: performing single-side back polishing on the silicon wafer in a chain acid polishing machine to reduce the weight by 0.1-0.2 g.

3. The preparation method according to claim 1, characterized in that: In S2, The deposition conditions of the tunnel oxide layer are: RF power 100-200 W, O2 flow rate 300-500 sccm, temperature 300-400°C, reaction time 20-100 s, thickness 1-5 nm; The deposition conditions of the phosphorus-doped amorphous silicon layer are: using a phosphorus-containing silicon target, power 30000-40000 W, Ar:PH3 flow rate = 1:1-5:1 sccm, temperature 200-300° C., reaction time 1000-8000 s, thickness 100-500 nm; The deposition conditions of the mask layer are: using pure silicon target material, Ar:O2 flow rate = 2:1~6:1 sccm, chamber temperature 200~300°C, reaction time 800~3000 s, thickness 100~300 nm.

4. The preparation method according to claim 1, characterized in that: S3 specifically includes: immersing the silicon wafer in an alkaline solution for texturing for 6 to 9 minutes at a temperature of 75 to 85°C; after the alkaline texturing, a positive pyramid texturing surface is formed on the front side of the silicon wafer.

5. The preparation method according to claim 1, characterized in that: S4 specifically includes: The tunnel oxide layer is deposited on the front side of the silicon wafer after texturing by LPCVD, with an O2 flow rate of 10000~80000 sccm, a temperature of 400~800℃, a time of 200~1000 s, and a tunnel oxide layer thickness of 2~10 nm. An intrinsic amorphous silicon layer is deposited on the tunnel oxide layer: SiH4 flow rate is 300~2000 sccm, temperature is 500~700℃, time is 2~4h, working pressure is 100~500 mTorr, and thickness of the intrinsic amorphous silicon layer is 100~300 nm.

6. The preparation method according to claim 1, characterized in that: In S5, the conditions for low-temperature boron diffusion are: temperature 800~860°C, time 20~80 min, BCl3 flow rate 100~1000 sccm, O2 flow rate 1000~3000 sccm; oxidation advancement temperature 860~895°C, O2 flow rate 5000~80000 sccm, advancement time 50~100 min, BSG thickness 20~50 nm.

7. The preparation method according to claim 1 or 6, characterized in that: In S5, the crystallization rate of the low crystallization rate boron diffusion layer is 20-70%.

8. The preparation method according to claim 1, characterized in that: In S6, The conditions of the laser crystallization are: laser wavelength 400-600 nm, pulse time 10-20 ns, frequency 10-20 KHz, power 1-10 W, time 1-20 s; The high crystallization rate boron diffusion layer has a crystallization rate of 70-90%.

9. The preparation method according to claim 1, characterized in that: S7 specifically includes: using a chain acid etcher with the front side of the silicon wafer facing upward to remove the BSG layer formed on the side of the silicon wafer during the boron diffusion process and the surface portion of the back mask layer, the concentration of the HF solution in the chain acid etcher is 20-80 wt%, and the belt speed is 0.5-5 m / min.

10. The preparation method according to claim 1, characterized in that: S8 specifically includes: placing the silicon wafer in an alkaline solution to remove the side boron diffusion layer, the temperature is 75-85°C, and the time is 3-7 minutes; then the silicon wafer is pickled to remove the front BSG layer and the residual mask layer on the back.

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