Composite error amplifier circuit for boost / reverse DC / DC converter

Abstract

The invention provides a composite error amplifier circuit for a boost / reverse DC / DC converter. The composite error amplifier circuit comprises triodes Q1 to Q11, resistors R1 to R11 and a bias current source IB1, the base electrodes of the triodes Q5-Q9 are connected together to form a current mirror structure; the positive electrode of the current source IB1, the collector electrode of the triode Q5 and the base electrode of the triode Q5 are connected; the triodes Q1 and Q2 form a differential pair, and the triodes Q3 and Q4 form a differential pair; a multi-reference voltage comparison function is integrated in a single circuit structure, so that the number of necessary circuit elements and the overall design complexity are remarkably reduced; through the design of the two differential pairs and the current mirrors Q5-Q11, the stability and the response speed of the circuit are improved; the two differential pair structures can effectively suppress external noise and internal interference, and improve the accuracy of signals.

Description

Technical Field

[0001] The invention belongs to the field of switch power supply chips in analog integrated circuits, and in particular relates to a composite error amplifier circuit for a boost / inversion DC / DC converter. Background Art

[0002] In a current mode switching power supply, the error amplifier is used to amplify the difference between the reference voltage and the feedback voltage. Its output is modulated and input into the pulse width modulator to control the peak current of the inductor. For a traditional boost / reverse DC / DC converter chip, its feedback voltage is a positive voltage when used for boost applications and a negative voltage when used for reverse applications. The traditional error amplifier implementation is as follows: Figure 1 As shown, two groups of error amplifiers and control logic circuits are needed to implement the design, which increases the complexity of the design and has a low response speed. Summary of the invention

[0003] In order to solve the problems existing in the background technology, the present invention provides a composite error amplifier circuit for a boost / inverting DC / DC converter, comprising: transistors Q1~Q11, resistors R1~R11 and a bias current source IB1; the bases of the transistors Q5~Q9 are connected together; the positive electrode of the current source IB1, the collector of the transistor Q5 and the base of the transistor Q5 are connected; the emitter of the transistor Q8 is connected to one end of the resistor R9; the collector of the transistor Q8, the collector of the transistor Q10, the base of the transistor Q10, one end of the resistor R11 and the base of the transistor Q11 are connected; the emitter of the transistor Q9 is connected to one end of the resistor R10; the collector of the transistor Q9, the other end of the resistor R11, the collector of the transistor Q11 and the output end EAOUT of the composite error amplifier are connected; the emitter of the transistor Q11 and the resistor R10 are connected. The transistor Q10 emitter is connected to one end of the resistor R5; the collector of the transistor Q6, the emitter of the transistor Q1 and the emitter of the transistor Q3 are connected; the collector of the transistor Q1, the collector of the transistor Q2, the other end of the resistor R7 and one end of the resistor R8 are connected; the collector of the transistor Q7, the emitter of the transistor Q2 and the emitter of the transistor Q4 are connected; the base of the transistor Q2 and one end of the resistor R4 are connected; the collector of the transistor Q3, the collector of the transistor Q4, the other end of the resistor R5 and one end of the resistor R6 are connected; the base of the transistor Q3, one end of the resistor R1 and the reference voltage input terminal VREF are connected; the other end of the resistor R1, one end of the resistor R3 and one end of the resistor R2 are connected; the other end of the resistor R3, the base of the transistor Q1, the base of the transistor Q4 and the feedback voltage input terminal FB are connected.

[0004] Preferably, the emitter of the transistor Q5 , the emitter of the transistor Q6 , the emitter of the transistor Q7 , the other end of the resistor R9 , and the other end of the resistor R10 are connected to VDD.

[0005] Preferably, the other end of the resistor R6, the other end of the resistor R8, the other end of the resistor R4, the other end of the resistor R2 and the negative electrode of the current source are connected to GND.

[0006] Preferably, the resistor R5 is equal to the resistor R7, and the resistor R6 is equal to the resistor R8.

[0007] Preferably, the transistors Q5 to Q11 are respectively of current mirror structures, and the current ratio between any two transistors among the transistors Q5 to Q11 is 1:1.

[0008] Preferably, the transistors Q10 and Q11 are NPN transistors.

[0009] Preferably, the transistors Q1 to Q9 are PNP transistors.

[0010] The present invention has at least the following beneficial effects

[0011] The present invention provides a composite error amplifier circuit for a step-up / inversion DC / DC converter, which significantly reduces the number of necessary circuit elements and the overall design complexity by integrating the functions of multiple reference voltage comparisons in a single circuit structure; by forming a differential pair of transistors Q1 and Q2, and forming a differential pair of transistors Q3 and Q4, the design of two differential pairs and current mirrors Q5 to Q11 improves the stability and response speed of the circuit; the two differential pair structures can effectively suppress external noise and internal interference, and improve the accuracy of the signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is the structure diagram of the traditional error amplifier;

[0013] Figure 2 This is a circuit diagram of the composite error amplifier of the present invention. DETAILED DESCRIPTION

[0014] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0015] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0016] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0017] See also Figure 2The present invention provides a composite error amplifier circuit for a boost / inverting DC / DC converter, comprising: transistors Q1-Q11, resistors R1-R11 and a bias current source IB1; the bases of the transistors Q5-Q9 are connected together; the positive electrode of the current source IB1, the collector of the transistor Q5 and the base of the transistor Q5 are connected; the emitter of the transistor Q8 and one end of the resistor R9 are connected; the collector of the transistor Q8, the collector of the transistor Q10, the base of the transistor Q10, one end of the resistor R11 and the base of the transistor Q11 are connected; the emitter of the transistor Q9 and one end of the resistor R10 are connected; the collector of the transistor Q9, the other end of the resistor R11, the collector of the transistor Q11 and the output end EAOUT of the composite error amplifier are connected; the emitter of the transistor Q11 and one end of the resistor R7 are connected The emitter of transistor Q10 is connected to one end of resistor R5; the collector of transistor Q6, the emitter of transistor Q1 and the emitter of transistor Q3 are connected; the collector of transistor Q1, the collector of transistor Q2, the other end of resistor R7 and one end of resistor R8 are connected; the collector of transistor Q7, the emitter of transistor Q2 and the emitter of transistor Q4 are connected; the base of transistor Q2 and one end of resistor R4 are connected; the collector of transistor Q3, the collector of transistor Q4, the other end of resistor R5 and one end of resistor R6 are connected; the base of transistor Q3, one end of resistor R1 and the reference voltage input terminal VREF are connected; the other end of resistor R1, one end of resistor R3 and one end of resistor R2 are connected; the other end of resistor R3, the base of transistor Q1, the base of transistor Q4 and the feedback voltage input terminal FB are connected.

[0018] Preferably, the emitter of the transistor Q5 , the emitter of the transistor Q6 , the emitter of the transistor Q7 , the other end of the resistor R9 , and the other end of the resistor R10 are connected to VDD.

[0019] Preferably, the other end of the resistor R6, the other end of the resistor R8, the other end of the resistor R4, the other end of the resistor R2 and the negative electrode of the current source are connected to GND.

[0020] Preferably, the resistor R5 is equal to the resistor R7, and the resistor R6 is equal to the resistor R8.

[0021] Preferably, the transistors Q5 to Q11 are respectively of current mirror structures, and the current ratio between any two transistors among the transistors Q5 to Q11 is 1:1.

[0022] Preferably, the transistors Q10 and Q11 are NPN transistors.

[0023] Preferably, the transistors Q1 to Q9 are PNP transistors.

[0024] The implementation principle of the present invention:

[0025] The overall circuit of the present invention is shown in the attached Figure 1 As shown, the main design includes two differential pairs and a current mirror circuit. The differential pairs are composed of transistors Q1 and Q2, and transistors Q3 and Q4. The current mirror circuit is designed by transistors Q5 to Q11. It adopts a unique dual differential pair structure with a simple structure. The current size is changed by opening and closing different transistors, thereby realizing multi-topology architecture applications.

[0026] The entire composite error amplifier circuit is divided into several parts: differential pairs Q1 / Q2, Q3 / Q4; current mirrors Q5~Q11; resistors R1~R11 and bias current source IB1, among which the ratio of Q5~Q9 is 1:1. The composite error amplifier circuit can be used for both boost / inversion applications.

[0027] In boost applications, if the voltage V at the feedback voltage input terminal FB is FB Greater than the voltage V at the reference voltage input terminal VREF REF , the current mirror Q5~Q9 mirrors the current IB1 of the current source IB1 to each branch; at this time, the transistor Q2 and the transistor Q3 are turned on, and the differential pairs Q1 / Q2 and Q3 / Q4 each flow out the current IB1 to the resistors R6 and R8; at the same time, the current mirror Q5~Q9 mirrors the current IB1 to the collectors of the transistors Q10 and Q11; and then flows out to the resistors R5 and R7 through the transistors Q10 and Q11 respectively; thereby making the emitter potentials of the transistors Q10 and Q11 IB1×(R5+2R6) and IB1×(R7+2R8) respectively; since R5=R7 and R6=R8, the emitter potentials of the transistors Q10 and Q11 are the same, so the two transistors Q10 and Q11 are in the same conduction state, and the collector potential of the transistor Q11 is pulled down, that is, the voltage V at the output terminal EAOUT of the composite error amplifier EAOUT Pulled down, the voltage is IB1(R7+2R8)+Vce ，Q11 , Vce ，Q11 represents the voltage between the collector and emitter of transistor Q11;

[0028] In boost applications, if the voltage V at the feedback voltage input terminal FB is FB Less than the voltage V at the reference voltage input terminal VREF REF, current mirrors Q5~Q9 mirror the current IB1 of current source IB1 to each branch; at this time, transistors Q1 and Q2 are turned on, and transistors Q3 and Q4 are turned off; the differential pair Q1 / Q2 flows out a current 2×IB1 to resistor R8; differential pair Q3 / Q4 is turned off and therefore does not provide current to resistor R6, resulting in an imbalance in the voltages on resistors R6 and R8, that is, the emitter potential of transistor Q11 is higher than the emitter potential of transistor Q10; at the same time, current mirrors Q5~Q9 still mirror the current IB1 to the collectors of transistors Q10 and Q11; and then flows out to resistor R through transistors Q10 and Q11. 5 and R7; since the transistor Q11 emitter potential is higher, part of the transistor Q11 branch current △IB1 is transferred to the transistor Q10 branch through the base; therefore, the transistor Q10 emitter outflow current is IB1+△IB1, and the transistor Q11 emitter outflow current is IB1-△IB1, so the transistor Q10 emitter voltage is (IB1+△IB1)×(R5+R6), and the transistor Q11 emitter voltage is (IB1-△IB1)×R7+(3IB1-△IB1)×R8; the transistor Q11 collector potential is pulled up, that is, the composite error amplifier output terminal EAOUT voltage V EAOUT Pulled up, the voltage is IB1×(R7+3R8)-△IB1×(R7+R8)+Vce ，Q11 , Vce ，Q11 Represents the voltage between the collector and emitter of transistor Q11.

[0029] In reverse application, when the circuit has not reached the preset output voltage stably, transistors Q1 and Q2 are both turned on, transistors Q3 and Q4 are turned off, and the base voltage of transistor Q2 is: R4×IC Q7 / β, where R4 is the resistance value of resistor R4, IC Q7 is the collector current of transistor Q7, β is the current amplification factor of transistor Q2, at this time V EAOUT Output low level; as the circuit starts, V FB The voltage gradually decreases, transistors Q1, Q2, and Q4 are turned on, the emitter current of transistor Q2 gradually decreases, and the emitter voltage of transistor Q4 gradually increases. When the emitter current of transistor Q2 is equal to the emitter current of transistor Q4, the loop is stable, and VEAOUT outputs a high level at this time. The present invention adopts a unique differential pair design, combined with a current mirror and a feedback mechanism, which not only simplifies the overall layout of the circuit, but also improves the response speed and stability of the circuit. Through precise voltage comparison and regulation, the error amplifier of the present invention can automatically detect and adjust the output voltage to match changes in load demand or operating conditions.

[0030] In summary, the composite error amplifier circuit for a boost / inverting DC / DC converter provided by the present invention significantly reduces the number of necessary circuit elements and the overall design complexity by integrating the functions of multiple reference voltage comparisons in a single circuit structure; by forming a differential pair of transistors Q1 and Q2, and forming a differential pair of transistors Q3 and Q4, the design of two differential pairs and current mirrors Q5 to Q11 improves the stability and response speed of the circuit; the two differential pair structures can effectively suppress external noise and internal interference, and improve the accuracy of the signal.

[0031] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

[0032] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A composite error amplifier circuit for a step-up / inverting DC / DC converter, characterized in that: include: The invention is composed of transistors Q1~Q11, resistors R1~R11 and bias current source IB1; the bases of the transistors Q5~Q9 are connected together; the positive electrode of the current source IB1, the collector of the transistor Q5 and the base of the transistor Q5 are connected; the emitter of the transistor Q8 is connected to one end of the resistor R9; the collector of the transistor Q8, the collector of the transistor Q10, the base of the transistor Q10, one end of the resistor R11 and the base of the transistor Q11 are connected; the emitter of the transistor Q9 is connected to one end of the resistor R10; the collector of the transistor Q9, the other end of the resistor R11, the collector of the transistor Q11 and the output end EAOUT of the composite error amplifier are connected; the emitter of the transistor Q11 is connected to one end of the resistor R7; the emitter of the transistor Q10 is connected to the end of the resistor R5 one end is connected; the collector of transistor Q6, the emitter of transistor Q1 and the emitter of transistor Q3 are connected; the collector of transistor Q1, the collector of transistor Q2, the other end of resistor R7 and one end of resistor R8 are connected; the collector of transistor Q7, the emitter of transistor Q2 and the emitter of transistor Q4 are connected; the base of transistor Q2 and one end of resistor R4 are connected; the collector of transistor Q3, the collector of transistor Q4, the other end of resistor R5 and one end of resistor R6 are connected; the base of transistor Q3, one end of resistor R1 and the reference voltage input terminal VREF are connected; the other end of resistor R1, one end of resistor R3 and one end of resistor R2 are connected; the other end of resistor R3, the base of transistor Q1, the base of transistor Q4 and the feedback voltage input terminal FB are connected.

2. A composite error amplifier circuit for a boost / inverting DC / DC converter according to claim 1, characterized in that: The emitter of the transistor Q5 , the emitter of the transistor Q6 , the emitter of the transistor Q7 , the other end of the resistor R9 and the other end of the resistor R10 are connected to VDD.

3. A composite error amplifier circuit for a boost / inverting DC / DC converter according to claim 1, characterized in that: The other end of the resistor R6 , the other end of the resistor R8 , the other end of the resistor R4 , the other end of the resistor R2 , and the negative electrode of the current source are connected to GND.

4. A composite error amplifier circuit for a boost / inverting DC / DC converter according to claim 1, characterized in that: The resistor R5 is equal to the resistor R7, and the resistor R6 is equal to the resistor R8.

5. A composite error amplifier circuit for a boost / inverting DC / DC converter according to claim 1, characterized in that: The transistors Q5 to Q11 are respectively current mirror structures, and the current ratio between any two transistors among the transistors Q5 to Q11 is 1:

1.

6. A composite error amplifier circuit for a boost / inverting DC / DC converter according to claim 1, characterized in that: The transistors Q10 and Q11 are NPN transistors.

7. A composite error amplifier circuit for a boost / inverting DC / DC converter according to claim 1, characterized in that: The transistors Q1 to Q9 are PNP transistors.

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