A floating inverting amplifier based on capacitor stack and its application

Abstract

The present invention discloses a floating inverting amplifier based on capacitor stacking, which increases the power supply of the floating inverting amplifier to 2 times V by capacitor stacking. DD Under this condition, the transistors in the inverter can be turned on better, and the common source and common gate structure can be applied to the inverting amplifier with low power supply voltage. In addition, the ADC system using the floating inverting amplifier of the present invention can handle the common mode voltage of V DD Amplitude up to 2 times V DD The input signal can effectively solve the problem of reduced input signal amplitude under ultra-low voltage and improve the system signal-to-noise ratio.

Description

Technical Field

[0001] The invention belongs to the technical field of amplifiers, and in particular relates to a floating inverting amplifier based on capacitor stacking and applications thereof. Background Art

[0002] As integrated circuit technology continues to advance, the power supply voltage is gradually reduced, but the threshold voltage of the device does not decrease proportionally with the power supply voltage. Under this condition, the gate-source voltage and overdrive voltage of the transistor decrease, which will cause it to work more in the subthreshold region, leading to problems such as reduced speed and increased noise. Similarly, the speed, gain, and swing of the amplifier will also decrease, and the noise performance will also deteriorate; how to design a higher performance amplifier at a low power supply voltage has become a difficult problem.

[0003] The method of increasing the overdrive voltage under low power supply voltage mainly lies in reducing the threshold voltage of the transistor or increasing the gate-source voltage of the transistor. Reducing the threshold voltage can be achieved by forward body bias, but forward body bias will make the parasitic PN junction between the transistor and the substrate forward biased, increasing the transistor leakage current, and will also introduce additional noise, affecting the performance of the amplifier; increasing the gate-source voltage of the transistor can be achieved by capacitor bias, but it usually requires the introduction of additional thermal noise.

[0004] For example, the literature [Liu Baohong, Chen Dongpo, Mao Junfa. A low voltage, low power consumption, low noise amplifier using positive body bias and gain enhancement technology [C] / / China Electronics Society. Proceedings of the 2009 National Microwave Millimeter Wave Conference (Volume 2). School of Electronic Information and Electrical Engineering, Shanghai Jiaotong University, 2009:4] proposed an amplifier based on the forward body bias technology, which connects the body terminal of the N-type MOS tube to a forward bias voltage, thereby equivalently reducing the threshold voltage of the MOS tube and increasing the overdrive voltage of the transistor; however, the forward body bias technology will make the parasitic PN junction between the transistor and the substrate forward biased, increase the transistor leakage current, and introduce additional noise. The Chinese patent application with publication number CN117728778A proposed a floating inverting amplifier based on capacitor bias technology, which increases the gate-source voltage of the transistor by using capacitor bias, so that the floating inverting amplifier can work under a power supply of less than 1V, but the amplifier requires an additional bias circuit and will also introduce additional sampling thermal noise, affecting the performance of the amplifier. Summary of the invention

[0005] In view of the above, the present invention provides a floating inverting amplifier based on capacitor stacking, which creates a 2 times V DD The floating power supply increases the gate-source voltage of the transistor at low power supply voltage, thereby improving the performance of the amplifier.

[0006] A floating inverting amplifier based on capacitor stacking comprises an inverter with a differential structure and a capacitor charge-discharge array. The capacitor charge-discharge array supplies power to the inverter by using two capacitors which are reset first and then stacked end to end.

[0007] Further, the inverter includes two PMOS tubes M1 and M2, two NMOS tubes M3 and M4, and two switches S8 and S9, wherein the source of M1 is connected to the source of M2 and connected to the floating power rail of the capacitor charge and discharge array, the source of M3 is connected to the source of M4 and connected to the floating ground rail of the capacitor charge and discharge array, the drain of M1 is connected to the drain of M3 and one end of S8 as the inverting output end of the inverter, the drain of M2 is connected to the drain of M4 and one end of S9 as the positive output end of the inverter, the gate of M1 is connected to the gate of M3 as the positive input end of the inverter, the gate of M2 is connected to the gate of M4 as the inverting input end of the inverter, and the other end of S8 is connected to the other end of S9 and connected to the power supply voltage V DD The on and off of switches S8 and S9 are controlled by the clock signal φ1.

[0008] Furthermore, the capacitor charging and discharging array includes seven switches S1 to S7 and two capacitors C RES1 and C RES2 , where one end of S1 is connected to the power supply voltage V DD , the other end of S1 is connected to C RES1 One end of S2 is connected to the power supply voltage V DD , the other end of S2 is connected to C RES2 One end of S6 is connected to one end of S5, the other end of S5 is the floating power rail of the capacitor charging and discharging array, and the other end of S6 is connected to C RES2 The other end of S4 is connected to the ground. RES1 The other end is connected to one end of S3 and one end of S7, the other end of S3 is grounded, and the other end of S7 is the floating ground rail of the capacitor charge and discharge array. The on-off of switches S1~S4 is controlled by clock signal φ1, and the on-off of switches S5~S7 is controlled by clock signal φ2.

[0009] Furthermore, the clock signals φ1 and φ2 are complementary in phase and have a certain non-overlapping dead time.

[0010] Furthermore, the common mode voltage between the positive input terminal and the negative input terminal of the inverter is V DD , the common mode voltage between the positive output and the negative output is V DD , the inverter power supply is 2 times V DD .

[0011] Furthermore, the inverter is based on a common source and common gate structure, which includes six PMOS tubes M1, M2, M5, M6, M7, M8, six NMOS tubes M3, M4, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, and six NMOS tubes M3, M4, M5, M6, M7, M8. 10 、M 11 、M 12 and two switches S8 and S9, wherein the source of M1 is connected to the source of M2 and connected to the floating power rail of the capacitor charge and discharge array, the drain of M1 is connected to the source of M5 and the source of M6, the drain of M2 is connected to the source of M7 and the source of M8, the source of M3 is connected to the source of M4 and connected to the floating ground rail of the capacitor charge and discharge array, the drain of M3 is connected to the source of M9 and the source of M 10 The source of M4 is connected to the drain of M 11 The source and M 12 The source of M5 is connected to the drain of M6, the drain of M9, and the drain of M 10 The drain of M7 is connected to the drain of M8 and one end of S8 as the inverting output end of the inverter. 11 The drain, M 12 The drain of S1 and one end of S9 are connected as the positive output end of the inverter, and the gate of M1 is connected to the gate of M3, the gate of M5, the gate of M8, the gate of M9 and the gate of M 12 The gate of M2 is connected to the gate of M4, the gate of M6, the gate of M7, and the gate of M 10 The gate and M 11 The gate of S8 is connected as the inverting input of the inverter, and the other end of S8 is connected to the other end of S9 and connected to the power supply voltage V DD The on and off of switches S8 and S9 are controlled by the clock signal φ1.

[0012] A low power supply voltage discrete time Δ-Σ analog-to-digital converter, which is composed of a switched capacitor array, a first-stage integrator, a second-stage integrator, a switched capacitor analog adder, and a SAR (successive approximation) quantizer connected in sequence from input to output; the first-stage integrator and the second-stage integrator both adopt the above-mentioned floating inverting amplifier based on capacitor stacking.

[0013] The floating inverting amplifier of the present invention increases the power supply of the floating inverting amplifier to 2 times V by stacking capacitors. DD Under this condition, the transistors in the inverter can be turned on better, and the common source and common gate structure can be applied to the inverting amplifier with low power supply voltage. In addition, the ADC system using the floating inverting amplifier of the present invention can handle the common mode voltage of V DD Amplitude up to 2 times V DD The input signal can effectively solve the problem of reduced input signal amplitude under ultra-low voltage and improve the system signal-to-noise ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematic diagram of the structure of a floating inverting amplifier circuit based on capacitor stacking in Example 1 of the present invention.

[0015] Figure 2 Schematic diagram of the switching timing of the floating inverting amplifier circuit in Embodiment 1 of the present invention.

[0016] Figure 3 Schematic diagram of the structure of a floating inverting amplifier circuit based on a common source and common gate structure and capacitor stacking in Example 2 of the present invention.

[0017] Figure 4 Schematic diagram of the circuit structure of a second-order 6-bit Δ-Σ analog-to-digital converter in Example 3 of the present invention.

[0018] Figure 5 Schematic diagram of the structure of the chopper switch circuit in Example 3 of the present invention.

[0019] Figure 6 Schematic diagram of the structure of the clock signal generating module in Embodiment 3 of the present invention.

[0020] Figure 7 Schematic diagram of the overall timing of the delta-sigma analog-to-digital converter in embodiment 3 of the present invention. DETAILED DESCRIPTION

[0021] In order to describe the present invention more specifically, the technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and specific implementation methods. Example 1

[0022] like Figure 1 As shown, this embodiment provides a floating inverting amplifier based on capacitor stacking for low power supply voltage discrete time Delta-Sigma ADC, wherein the inverter is powered by two capacitors which are first reset and then stacked end to end, and its differential input terminal V IP With V IN The common mode voltage is the power supply voltage V DD , differential output V OP With V ON The common mode voltage is the power supply voltage V DD , the inverter power supply is twice the power supply voltage V DD .

[0023] The specific structure of the floating inverting amplifier includes two PMOS tubes M1 and M2, two NMOS tubes M3 and M4, nine switches S1~S9 and two capacitors C RES1 With C RES2 , where the gates of M1 and M3 are connected to the positive input terminal V IP, the gates of M2 and M4 are connected to the inverting input terminal V IN , the sources of M1 and M2 are connected to one end of switch S5 and connected to the floating power rail V SP , the drain of M1 is connected to the drain of M3 and serves as the inverting output terminal V ON , the source of M3, M4 is connected to one end of switch S7 and connected to the floating ground rail V SN , the drain of M4 is connected to the drain of M2 and serves as the positive output terminal V OP , one end of switch S1 is connected to V DD The other end of switch S1 is connected to one end of switch S6 and capacitor C RES1 One end of the capacitor C RES1 The other end of the switch S3 is connected to one end of the switch S7, the other end of the switch S3 is connected to the ground GND, and one end of the switch S2 is connected to V DD The other end of switch S2 is connected to the other end of switch S5, capacitor C RES2 One end of the capacitor C RES2 The other end of the switch S6 is connected to the other end of the switch S4, the other end of the switch S4 is connected to the ground GND, and one end of the switch S8 is connected to the inverting output terminal V ON One end of switch S9 is connected to the positive phase output terminal V OP The other end of switch S8 and the other end of switch S9 are connected to V DD The on-off of switches S1~S4 and S8~S9 is controlled by clock signal φ1, and the on-off of switches S5~S7 is controlled by clock signal φ2.

[0024] like Figure 2 As shown, the clock signal φ1 is used to close the switch in the system reset phase, and the clock signal φ2 is used to close the switch in the system amplification phase. The phases of φ1 and φ2 are complementary and there is a certain non-overlapping time. Example 2

[0025] like Figure 3 As shown, in this embodiment, a floating inverting amplifier based on a capacitor stack and a common source and common gate structure is provided, which includes 6 PMOS tubes M1~M2 and M5~M8, 6 NMOS tubes M3~M4 and M9~M10. 12 , 9 switches S1~S9 and 2 capacitors C RES1 and C RES2 , among which M1, M3, M5, M8, M9 and M 12 The gate is connected to the positive input terminal V IP , M2, M4, M6, M7, M 10 and M 11 The gate is connected to the inverting input terminal V IN, the sources of M1 and M2 are connected to one end of switch S5 and connected to the floating power rail V SP , the drain of M1 is connected to the source of M5 and M6, and M5, M6, M9 and M 10 The drain of the inverter is connected to the inverting output terminal V ON , M9, M 10 The source of M3 is connected to the drain of M3, and the source of M3 and M4 is connected to one end of switch S7 and connected to the floating ground rail V SN , the drain of M4 and M 11 、M 12 The source of M7, M8, M 11 and M 12 The drain of the positive output terminal V OP , the sources of M7 and M8 are connected to the drain of M2, and one end of switch S1 is connected to V DD The other end of switch S1 is connected to one end of switch S6 and capacitor C RES1 One end of the capacitor C RES1 The other end of the switch S3 is connected to one end of the switch S7, the other end of the switch S3 is connected to the ground GND, and one end of the switch S2 is connected to V DD The other end of switch S2 is connected to the other end of switch S5, capacitor C RES2 One end of the capacitor C RES2 The other end of the switch S6 is connected to the other end of the switch S4, the other end of the switch S4 is connected to the ground GND, and one end of the switch S8 is connected to the inverting output terminal V ON One end of switch S9 is connected to the positive phase output terminal V OP The other end of switch S8 and the other end of switch S9 are connected to V DD The on-off of switches S1~S4 and S8~S9 is controlled by clock signal φ1, and the on-off of switches S5~S7 is controlled by clock signal φ2. Example 3

[0026] like Figure 4 As shown, the floating inverting amplifier in Embodiment 2 is applied to a 2nd-order 6-bit Δ-Σ analog-to-digital converter, which includes a feedback signal selection module, a switched capacitor array, a first-stage integrator, a second-stage integrator, a switched capacitor analog adder, a SAR quantizer (6-bit SAR QTZ), a digital logic control unit, a clock signal generation module and a charge pump module (Charge Pump), wherein:

[0027] The common-mode voltage of the input signal is V DD , the common-mode voltage of the ΔΣ ADC is V DD The analog-to-digital converter reference voltages VREFP and VREFN are 2V respectively. DDThe feedback signal selection module controls the switch S according to the output of the digital logic control unit. 3,1-63 and S 4,1-63 One end of S is connected to VREFP or VREFN; when the output of the SAR quantizer is k (0≤k≤63), S 3,1-63 There are k ports connected to VREFP, 63-k ports connected to VREFN, S 4,1-63 There are k ports connected to VREFN and 63-k ports connected to VREFP.

[0028] The switched capacitor array consists of 126 unit capacitors C S1A,1-63 With C S1B,1-63 and 252 switches S 1,1-63 , S 2,1-63 , S 3,1-63 With S 4,1-63 Composition, equivalent to C S1A , C S1B , S1, S2, S3, and S4 each consist of 63 identical copies (63×Slices), where switch S 1,1-63 and S 2,1-63 One end of the differential input signal V IP With V IN , switch S 1,1-63 The other end of the switch S 3,1-63 The other end of the sampling capacitor C S1A,1-63 One end of the switch S 2,1-63 The other end is connected to the switch S 4,1-63 The other end of the sampling capacitor C S1B,1-63 One end of the switch S 3,1-63 With switch S 4,1-63 The other end is connected to the feedback signal selection module, and the switch S 1,1-63 With S 2,1-63 The on-off of 1D Control, switch S 3,1-63 With S 4,1-63 The on-off of 2D control.

[0029] The first stage integrator includes a floating inverting amplifier AMP1 based on capacitor stacking and common source and common gate structure in Embodiment 2, two integrating capacitors C INT1A and C INT1B , capacitor array, 4 switches S5~S8 and a group of chopper switches CH1 and CH2, one end of switches S5 and S6 are connected to the capacitor array, one end of switch S5 and one end of switch S7 are connected to one input end of the chopper switch CH1, the other end of switch S5 is connected to the common mode voltage, and the other end of switch S7 is connected to the integral capacitor C INT1AOne end of the switch S6 and one end of the switch S8 are connected to the other input end of the chopper switch CH1, the other end of the switch S6 is connected to the common mode voltage, and the other end of the switch S8 is connected to the integral capacitor C INT1B One end of the integrating capacitor C INT1A and C INT1B The other end is connected to the two output ends of the chopper switch CH2 respectively, the two output ends of the chopper switch CH1 are connected to the two input ends of AMP1, the two output ends of AMP1 are connected to the two input ends of the chopper switch CH2, the on-off of switches S5 and S6 is controlled by the clock signal φ1, and the on-off of switches S7 and S8 is controlled by the clock signal φ2.

[0030] The second stage integrator includes a floating inverting amplifier AMP2 based on capacitor stacking and common source and common gate structure in embodiment 2, two sampling capacitors C S2A and C S2B , 2 integrating capacitors C INT2A and C INT2B And 8 switches S9~S 16 , switches S9 and S 10 One end is connected to the output end V of the first stage integrator INT1+ and V INT1- The other end of switch S9 and switch S 11 One end and the sampling capacitor C S2A One end of the switch S 11 The other end is connected to the common mode voltage, and the sampling capacitor C S2A The other end of the switch S 13 One end of the switch S 15 One end of the switch S is connected to the positive input of AMP2. 13 The other end of the switch S 15 The other end of the integrating capacitor C INT2A One end of the integrating capacitor C INT2A The other end is connected to the negative output terminal of AMP2, and the switch S 10 The other end of the switch S 12 One end and the sampling capacitor C S2B One end of the switch S 12 The other end is connected to the common mode voltage, and the sampling capacitor C S2B The other end of the switch S 14 One end of the switch S 16 One end of the switch S is connected to the negative input terminal of AMP2. 14 The other end of the switch S 16 The other end of the integrating capacitor C INT2B One end of the integrating capacitor C INT2B The other end is connected to the positive output terminal of AMP2, and switches S9 and S10 , S 13 , S 14 The on-off of switch S is controlled by clock signal φ2. 11 , S 12 , S 15 , S 16 The on and off of is controlled by the clock signal φ1.

[0031] The switched capacitor analog adder consists of six feedforward capacitors C F1A , C F1B , C F2A , C F2B , C F3A , C F3B and 16 switches S 17 ~S 32 , switch S 17 One end is connected to the input signal V IP , switch S 17 The other end of the switch S 19 One end of the feedforward capacitor C F1A One end of the switch S 19 The other end of the switch S 18 One end is connected to the input signal V IN , switch S 18 The other end of the switch S 20 One end of the feedforward C F1B One end of the switch S 20 The other end of the switch S 21 One end is connected to the output terminal V of the first stage integrator INT1+ Connected, switch S 21 The other end of the switch S 23 One end of the feedforward capacitor C F2A One end of the switch S 23 The other end of the switch S 22 One end is connected to the output terminal V of the first stage integrator INT1- Connected, switch S 22 The other end of the switch S 24 One end of the feedforward capacitor C F2B One end of the switch S 24 The other end of the switch S 25 One end of the feedforward capacitor C F3A One end of the second stage integrator is connected to the output terminal V INT2+ Connected, switch S 25 The other end of the switch S 26 One end of the feedforward capacitor C F3B One end of the integrator is connected to the output terminal V INT2- Connected, switch S26 The other end of the feedforward capacitor C F1A , C F2A , C F3A The other end of the switch S 27 ~S 29 One end of the feedforward capacitor C is connected to the negative input of the SAR quantizer. F1B , C F2B , C F3B The other end of the switch S 30 ~S 32 One end of the switch is connected to the positive input of the SAR quantizer. 27 ~S 32 The other end of the switch S 17 , S 18 , S 27 , S 29 , S 30 , S 32 The on-off of switch S is controlled by clock signal φ1. 21 , S 22 , S 28 , S 31 The on-off of 2-ADD Control, switch S 19 , S 20 , S 23 ~S 26 The on-off of ADD control.

[0032] The SAR quantizer is implemented using a six-bit successive approximation ADC, which generates the total output of the system Y OUT The signal feedback part is composed of B / T (Binary to Thermometer Code) & DWA (Date Weighted Averaging) module and charge pump module. The B / T & DWA module first converts the output result Y of SAR quantizer to OUT The module converts the thermometer code into a thermometer code, and then uses the internal register to perform a circular shift on the thermometer code to generate the module output result Code, where the bit width of Code is 63; the charge pump module converts the high level voltage of Code from V DD Increase to 2 times V DD Then CodeB is output to control the switch in the feedback signal selection module.

[0033] like Figure 5 As shown, the chopper switch includes four switches S1~S4, where one end of switches S1 and S3 is connected to V IN1 , one end of switches S2 and S4 is connected to V IN2, the other end of switches S1 and S4 are connected to V OUT1 , the other end of switches S2 and S3 are connected to V OUT2 , the on and off of switches S1 and S2 are controlled by the clock f CH The on and off of switches S3 and S4 are controlled by the clock f CHB control.

[0034] like Figure 6 As shown, the clock signal generating module includes 20 inverters INV1~INV20, 5 NAND gates NAND1~NAND5 and 1 D flip-flop DFF1, wherein the first input end of the NAND gate NAND1 is connected to the input clock CLK, the output end of NAND1 is connected to the input end of the inverter INV1 and the first input end of the NAND gate NAND2, the output end of the inverter INV1 is connected to the input end of the inverter INV2 and the input end of the inverter INV5, the output end of the inverter INV2 is connected to the second input end of the NAND gate NAND2, the output end of the NAND gate NAND2 is connected to the input end of the inverter INV3, the output end of the inverter INV3 is connected to the input end of the inverter INV4, the output end of the inverter INV4 is connected to the input end of the inverter INV8, and the clock φ is generated. 1D , the output end of the inverter INV5 is connected to the input end of the inverter INV6, the output end of INV6 generates the clock φ1, the input end of the inverter INV9 is connected to the input clock CLK, the input end of the inverter INV9 is connected to the second input end of the NAND gate NAND3, the second input end of the NAND gate NAND3 is connected to the output end of INV8, the output end of the NAND gate NAND3 is connected to the input end of the inverter INV10 and the second input end of the NAND gate NAND4, the output end of the inverter INV10 is connected to the input end of the inverter INV11 and the input end of the inverter INV14, the output end of the inverter INV11 is connected to the first input end of the NAND gate NAND4, the output end of the NAND gate NAND4 is connected to the input end of the inverter INV12, the output end of the inverter INV12 is connected to the input end of the inverter INV13, the output end of the inverter INV13 is connected to the input end of the inverter INV7, and the clock φ is generated. 2D The output end of the inverter INV7 is connected to the second input end of the NAND gate NAND1, the output end of the inverter INV14 is connected to the input end of the inverter INV15, the output end of the inverter INV15 is connected to the second input end of the NAND gate NAND5, and a clock φ2 is generated. The first input end of the NAND gate NAND5 is connected to the input clock φ ADD The output of the NAND gate NAND5 is connected to the input of the inverter INV20, and the output of the inverter INV20 generates a clock φ 2-ADD , the clk terminal of the D flip-flop DFF1 is connected to the clock φ1, and the vin terminal of the D flip-flop DFF1 and the qb The output end of the inverter INV18 is connected to the input end of the inverter INV19, and the output end of the inverter INV19 generates a clock f CHB The q end of the D flip-flop DFF1 is connected to the input end of the inverter INV16, the output end of the inverter INV16 is connected to the input end of the inverter INV17, and the output end of the inverter INV17 generates a clock f CH .

[0035] like Figure 7 As shown, the overall clock of the system includes 6 clocks φ1, φ 1D ,φ2,φ 2D ,φ 2-ADD ,φ ADD , where φ1 and φ 1D The rising edge of 1D The falling edge of φ1 is delayed, φ2, φ 2D and φ 2-ADD The rising edge of 2D The falling edge of φ1 is delayed than that of φ2. φ1 and φ2 are non-overlapping clocks. 2-ADD and φ ADD is the sub-clock of φ2, φ 2-ADD and φ ADD is a non-overlapping clock, φ ADD The falling edge of is aligned with the falling edge of φ2.

[0036] The floating inverting amplifier based on capacitor stacking and common source and common gate structure of the present invention can achieve a gain of more than 40dB at a low power supply voltage, and the discrete time Δ-Σ analog-to-digital converter using the floating inverting amplifier of the present invention can achieve a high precision of more than 90dB SNDR (signal-to-noise ratio).

[0037] The above description of the embodiments is to facilitate the understanding and application of the present invention by those skilled in the art. It is obvious that those skilled in the art can easily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative work. Therefore, the present invention is not limited to the above embodiments. Improvements and modifications made by those skilled in the art to the present invention based on the disclosure of the present invention should be within the protection scope of the present invention.

Claims

1. A floating inverting amplifier based on capacitor stack, characterized in that: It includes an inverter with a differential structure and a capacitor charge-discharge array, wherein the capacitor charge-discharge array uses two capacitors that are reset first and then stacked end to end to power the inverter; The inverter includes two PMOS tubes M1 and M2, two NMOS tubes M3 and M4, and two switches S8 and S9, wherein the source of M1 is connected to the source of M2 and connected to the floating power rail of the capacitor charge and discharge array, the source of M3 is connected to the source of M4 and connected to the floating ground rail of the capacitor charge and discharge array, the drain of M1 is connected to the drain of M3 and one end of S8 as the inverting output end of the inverter, the drain of M2 is connected to the drain of M4 and one end of S9 as the positive output end of the inverter, the gate of M1 is connected to the gate of M3 as the positive input end of the inverter, the gate of M2 is connected to the gate of M4 as the inverting input end of the inverter, and the other end of S8 is connected to the other end of S9 and connected to the power supply voltage V DD , the on and off of switches S8 and S9 are controlled by the clock signal φ1; As another implementation, the inverter is based on a common source and common gate structure, which includes six PMOS tubes M1, M2, M5, M6, M7, M8, six NMOS tubes M3, M4, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, and six NMOS tubes M1, M1, M2, M3, M4, M5, M6, M7, M8. 10 、M 11 、M 12 and two switches S8 and S9, wherein the source of M1 is connected to the source of M2 and connected to the floating power rail of the capacitor charge and discharge array, the drain of M1 is connected to the source of M5 and the source of M6, the drain of M2 is connected to the source of M7 and the source of M8, the source of M3 is connected to the source of M4 and connected to the floating ground rail of the capacitor charge and discharge array, the drain of M3 is connected to the source of M9 and the source of M 10 The source of M4 is connected to the drain of M 11 The source and M 12 The source of M5 is connected to the drain of M6, the drain of M9, and the drain of M 10 The drain of M7 is connected to the drain of M8 and one end of S8 as the inverting output end of the inverter. 11 The drain, M 12 The drain of S1 and one end of S9 are connected as the positive output end of the inverter, and the gate of M1 is connected to the gate of M3, the gate of M5, the gate of M8, the gate of M9 and the gate of M 12 The gate of M2 is connected to the gate of M4, the gate of M6, the gate of M7, and the gate of M 10 The gate and M 11 The gate of S8 is connected as the inverting input of the inverter, and the other end of S8 is connected to the other end of S9 and connected to the power supply voltage V DD , the on and off of switches S8 and S9 are controlled by the clock signal φ1; The capacitor charging and discharging array includes seven switches S1 to S7 and two capacitors C RES1 and C RES2 , where one end of S1 is connected to the power supply voltage V DD , the other end of S1 is connected to C RES1 One end of S2 is connected to the power supply voltage V DD , the other end of S2 is connected to C RES2 One end of S6 is connected to one end of S5, the other end of S5 is the floating power rail of the capacitor charging and discharging array, and the other end of S6 is connected to C RES2 The other end of S4 is connected to the ground. RES1 The other end is connected to one end of S3 and one end of S7, the other end of S3 is grounded, and the other end of S7 is the floating ground rail of the capacitor charge and discharge array. The on-off of switches S1~S4 is controlled by clock signal φ1, and the on-off of switches S5~S7 is controlled by clock signal φ2.

2. The floating inverting amplifier based on capacitor stack according to claim 1, characterized in that: The clock signals φ1 and φ2 are complementary in phase and have a certain non-overlapping dead time.

3. The floating inverting amplifier based on capacitor stack according to claim 1, characterized in that: The common mode voltage between the positive input and the negative input of the inverter is V DD , the common mode voltage between the positive output and the negative output is V DD , the inverter power supply is 2 times V DD .

4. A low power supply voltage discrete time delta-sigma analog-to-digital converter, which is composed of a switched capacitor array, a first stage integrator, a second stage integrator, a switched capacitor analog adder, and a SAR quantizer connected in sequence from input to output, characterized in that: The first-stage integrator and the second-stage integrator both adopt a floating inverting amplifier based on capacitor stacking as described in any one of claims 1 to 3.

5. The low supply voltage discrete time delta-sigma analog-to-digital converter according to claim 4, characterized in that: The floating inverting amplifier can achieve a gain of more than 40 dB at a low supply voltage, and the low supply voltage discrete time delta-sigma analog-to-digital converter can achieve an accuracy of more than 90 dB SNDR.

Images