Clock phase adjusting method, system, device and equipment

Abstract

The embodiment of the invention provides a clock phase adjusting method, system, device and equipment. In the embodiment of the invention, the system comprises a fine granularity phase adjusting module and a coarse granularity phase adjusting module, wherein the coarse granularity phase adjusting module comprises a first input end used for receiving a clock signal, a first number of coarse tuning sub-modules used for performing coarse granularity phase adjustment on the clock signal, and a first output end used for outputting the clock signal after coarse tuning; each coarse tuning sub-module is composed of two phase inverters which are connected in series and a phase inverter which is connected in parallel, and the coarse tuning sub-modules of the first number are connected in series; and the fine granularity phase adjusting module comprises a second input end for receiving the clock signal subjected to coarse adjustment, a second number of fine adjustment sub-modules for performing fine granularity phase adjustment on the clock signal subjected to coarse adjustment, and a second output end for outputting the clock signal subjected to fine adjustment.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a clock phase adjustment method, system, device and equipment. Background Art

[0002] At present, a clock phase adjustment module is usually required in an interface chip to adjust the phase of a received clock signal. As the requirements for data transmission accuracy between chips become higher and higher, existing interface chips also put forward higher requirements for the adjustment range and adjustment accuracy of the clock phase adjustment module. How to achieve the purpose of achieving high-precision clock phase adjustment within a larger clock phase adjustment range still requires further solutions. Summary of the invention

[0003] Multiple aspects of the present application provide a clock phase adjustment method, system, apparatus and device for achieving a high-precision clock phase adjustment purpose within a larger clock phase adjustment range.

[0004] An embodiment of the present application provides a clock phase adjustment system, including: the system includes a fine-grained phase adjustment module and a coarse-grained phase adjustment module, wherein: the coarse-grained phase adjustment module includes a first input end for receiving a clock signal, a first number of coarse adjustment sub-modules for performing coarse-grained phase adjustment on the clock signal, and a first output end for outputting a coarsely adjusted clock signal, one of the coarse adjustment sub-modules is composed of two inverters connected in series and one inverter connected in parallel, and the first number of coarse adjustment sub-modules are connected in series; the fine-grained phase adjustment module includes a second input end for receiving the coarsely adjusted clock signal, a second number of fine adjustment sub-modules for performing fine-grained phase adjustment on the coarsely adjusted clock signal, and a second output end for outputting the fine-adjusted clock signal, one of the fine adjustment sub-modules is composed of a phase interpolator with a specified number of steps and two inverters connected in series, and the second number of fine adjustment sub-modules are connected in parallel.

[0005] An embodiment of the present application also provides an integrated circuit, which includes a clock phase adjustment system.

[0006] An embodiment of the present application also provides a clock phase adjustment method, which is applied to a clock phase adjustment system, including: determining the phase difference between a clock signal to be adjusted and a target clock signal; using the clock signal to be adjusted as an input signal of the coarse-grained phase adjustment module, and performing coarse-grained phase adjustment on the clock signal to be adjusted based on the phase difference to obtain the clock signal after the coarse-grained phase adjustment; using the clock signal after the coarse-grained phase adjustment as an input signal of the fine-grained phase adjustment module, and performing fine-grained phase adjustment on the clock signal after the coarse-grained phase adjustment based on the phase difference through the fine-grained phase adjustment module.

[0007] An embodiment of the present application also provides a clock phase adjustment device, including: a phase difference determination module, used to determine the phase difference between a clock signal to be adjusted and a target clock signal; a signal coarse adjustment module, used to use the clock signal to be adjusted as an input signal of the coarse-grained phase adjustment module, and perform coarse-grained phase adjustment on the clock signal to be adjusted based on the phase difference to obtain the clock signal after the coarse-grained phase adjustment; a signal fine adjustment module, used to use the clock signal after the coarse-grained phase adjustment as an input signal of the fine-grained phase adjustment module, and perform fine-grained phase adjustment on the clock signal after the coarse-grained phase adjustment based on the phase difference through the fine-grained phase adjustment module.

[0008] The clock phase adjustment system provided in the embodiment of the present application includes a fine-grained phase adjustment module and a coarse-grained phase adjustment module. Since the fine-grained phase adjustment module is composed of a plurality of fine-tuning submodules connected in parallel, and each fine-tuning submodule is composed of a phase interpolator with a specified number of steps and two inverters connected in series, the load of the input clock signal of each phase interpolator is effectively reduced, thereby enabling the entire clock phase adjustment system to achieve a higher operating frequency. At the same time, since the fine-grained phase adjustment module adopts a parallel structure, the fine adjustment range of the plurality of parallel fine-tuning submodules is the superposition value of the fine adjustment range of each fine-tuning submodule, therefore, it can also ensure that the clock phase adjustment system has a larger fine-grained phase adjustment range. Similarly, the coarse-grained phase adjustment module adopts a structure in which a plurality of coarse-tuning submodules are connected in series, which can also ensure that the clock phase adjustment system has a larger coarse-grained phase adjustment range, thereby ensuring that the overall phase adjustment range of the clock phase adjustment system is larger. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0010] Figure 1A circuit diagram of a clock phase adjustment system provided by the prior art;

[0011] Figure 2 It is a structural diagram of a phase interpolator with an interpolation number of 24 steps;

[0012] Figure 3 A schematic diagram of the structure of a clock phase adjustment system provided for an exemplary embodiment of the present application;

[0013] Figure 4 A schematic diagram of the phase delay of the clock signal ckin to be adjusted input to the clock phase adjustment system relative to the clock signal ckout output;

[0014] Figure 5 A schematic diagram of the structure of a target fine adjustment submodule of a fine-grained phase adjustment module in a clock phase adjustment system provided in an embodiment of the present application;

[0015] Figure 6 A schematic diagram of the relationship between the coarse-adjusted delay and the fine-adjusted delay in the phase delay of the clock signal ckin to be adjusted input to the clock phase adjustment system relative to the output clock signal ckout;

[0016] Figure 7 An example diagram of a clock phase adjustment system provided in an embodiment of the present application;

[0017] Figure 8 The control module in the clock phase adjustment system provided in the embodiment of the present application Figure 7 Schematic diagram of each phase interpolator sending a control signal;

[0018] Fig. 9 To adopt Figure 7 A schematic diagram of the size of the phase delay adjusted by a fine adjustment step and the difference between the phase delays adjusted by different fine adjustment steps obtained by the clock phase adjustment system shown;

[0019] Fig.10 A schematic diagram of the structure of an integrated circuit / interface chip / system on chip / electronic device provided in an embodiment of the present application;

[0020] Fig.11 A schematic diagram of an implementation flow of a clock phase adjustment method provided in an exemplary embodiment of the present application;

[0021] Fig.12 A schematic diagram of the structure of a clock phase adjustment device provided in an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0023] First, the terms involved in one or more embodiments of the present application are explained.

[0024] Interface chip: An interface chip is a chip with internal interface circuits. The interface circuits have the following functions: (1) Setting data storage and buffering logic to adapt to the speed difference between the CPU and external devices. The interface is usually composed of some registers or RAM chips. As long as these chips are large enough, batch data transmission can be performed; (2) Information format conversion, such as serial and parallel conversion; (3) Ability to coordinate the type and level differences between the CPU and external devices in the information, such as level conversion drivers, digital / analog or analog / digital converters, etc.; (4) Coordinate timing differences; (5) Address decoding and selection functions; (6) Setting interrupt and DMA control logic to ensure that interrupt and DMA request signals are generated when DMA is allowed, and interrupt processing and DMA transfer are completed after the interrupt and DMA response are received.

[0025] System on chip, whose English name is System on Chip, abbreviated as SoC, is called system-level chip, also known as, meaning that it is a product, an integrated circuit with a dedicated purpose, which contains all the contents of a complete system and embedded software.

[0026] Clock signal: A clock signal is a square wave with a fixed period. The period is the time interval between one clock edge and the next clock edge, for example, the time interval between one rising edge and the next rising edge. The frequency of a clock is equal to the inverse of the clock period.

[0027] Phase: The relative position of a system in a cycle of vibration or fluctuation. If the relative positions are the same, they are in phase; if the relative positions are opposite, they are in opposite phases; if the relative position is less than half a cycle, it is called phase advance; if it is greater than half a cycle, it is phase lag.

[0028] Phase interpolator: A phase interpolator interpolates the phase. A phase interpolator requires multiple input clocks of different phases, usually four-phase or eight-phase inputs, and then selects two adjacent input phases and performs weighted interpolation on them. By adjusting the weights of the two phases, the phase interpolator can output a clock of any phase.

[0029] Inverter: The inverter can reverse the phase of the input signal by 180 degrees. This circuit is used in analog circuits, such as audio amplifiers, clock oscillators, etc.

[0030] Figure 1 A circuit diagram of a clock phase adjustment system provided by the prior art, the system includes a coarse-grained phase adjustment module CT0 and a fine-grained phase adjustment module FT0. The coarse-grained phase adjustment module CT0 includes a first input terminal I11 for receiving a clock signal, N coarse adjustment submodules CT01 to CT0 for coarse-grained phase adjustment of the clock signal, N , and a first output terminal O11 for outputting a coarsely adjusted clock signal. A coarse adjustment submodule is composed of two inverters connected in series and one inverter connected in parallel. N coarse adjustment submodules CT01 to CT0 N The inverters N11 and N12 in the coarse tuning submodule CT01 are connected in series and then connected in parallel with the inverter N13. The inverters N21 and N22 in the coarse tuning submodule CT02 are connected in series and then connected in parallel with the inverter N23. N The inverters Nn1 and Nn2 are connected in series and then connected in parallel with the inverter Nn3. The states of these inverters can be controlled by the control signal of the coarse-grained phase adjustment module CT0. The fine-grained phase adjustment module FT0 includes a second input terminal I12 for receiving the coarsely adjusted clock signal, a fine-tuning module FT0 for performing fine-grained phase adjustment on the coarsely adjusted clock signal, an inverter N0 for inverting the output signal pi_out of the fine-tuning module FT0, and a second output terminal O12 for outputting the fine-tuned clock signal (i.e., the output signal of the inverter N0), wherein the fine-tuning module FT01 is composed of a phase interpolator "PI 24step" with an interpolation number of 24 steps and six inverters N1 to N6 connected in series, the front end of the phase interpolator "PI 24step" is connected to the input ends of the six inverters N1 to N6 connected in series, and the rear end of the phase interpolator "PI 24step" is connected to the output ends of the six inverters N1 to N6 connected in series. Figure 1 The inverter models shown are all X8 inverters. The "8" in X8 is used to characterize the driving capability of the inverter. The larger the number, the greater the driving capability.

[0031] Depend on Figure 1It can be seen that although the N coarse-tuning submodules CT01 to CT0 of the coarse-grained phase adjustment module CT0 N The two modules are connected in parallel, and the number of coarse adjustment submodules can be dynamically expanded according to actual needs, thereby expanding the coarse adjustment range of the coarse-grained phase adjustment module CT0. However, the fine adjustment module FT01 of the fine-grained phase adjustment module FT0 is composed of a phase interpolator with an interpolation number of 24 steps and six inverters in series. When expanding the fine adjustment range, the fine adjustment module can only increase the interpolation number of the phase interpolator in the fine adjustment module FT01.

[0032] Figure 2 The schematic diagram of the structure of the phase interpolator with 24 interpolation steps is shown in Figure 2 In the figure, there is a group of inverters connected in parallel on both sides of the phase interpolator, and the number of inverters in each group is 24. The input end of the left group of inverters is connected to the front end of the phase interpolator, and the input end of the right group of inverters is connected to the back end of the phase interpolator. The output ends of these two groups of inverters are connected to the output end of the phase interpolator. Obviously, as the number of interpolations of the phase interpolator in the fine-tuning module FT01 continues to increase, the number of inverters on the left and right sides of the phase interpolator also increases, which makes the load on the front and back ends of the phase interpolator larger and larger.

[0033] Ideally, the rising edge of the clock signal is vertically upward, and the falling edge is also vertically downward. The phase interpolator is essentially equivalent to a capacitor for the signal of the previous stage. As the number of inverters on the left and right sides of the phase interpolator continues to increase, the load of the capacitor is getting larger and larger, and the rate of charging and discharging of the capacitor is getting slower and slower. This causes the rising and falling edges of the clock signal driven by the phase interpolator to no longer be vertically upward and vertically downward, but to slowly rise and slowly fall with a certain slope. Moreover, in the case of heavy load, since the rising edge rises relatively slowly, it often has not reached the top of the clock signal (high level) and may slowly fall to the bottom of the clock signal (low level). This makes the overall high level duration of the clock signal shorter than that of a normal clock signal. Since the operating frequency of the clock signal is positively correlated with the duration of the high level (generally speaking, the duration of the high level of the clock signal often accounts for about 45% of the entire clock signal cycle. If it is lower than this ratio, the clock signal will not work. It should be understood that the ratio is only an example and should not constitute any limitation). Therefore, excessive load will greatly limit the operating frequency of the clock signal.

[0034] When the clock signal is coarsely adjusted by the coarse-grained phase adjustment module, the control signal of the coarse-grained phase adjustment module can be used to control the clock signal to reach O11 via the inverters N11 and N12 in the coarse adjustment submodule CT01, and the clock signal reaching O11 via two inverters can be considered as a coarse adjustment step. The control signal of the coarse-grained phase adjustment module can also be used to control the clock signal to reach O11 via the inverter N11 in the coarse adjustment submodule CT01, the inverters N12 and N22 in the coarse adjustment submodule CT02, and the inverter N13 in the coarse adjustment submodule CT01. In this process, the process in which the clock signal reaches O11 via four inverters can be called two coarse adjustment steps. Similarly, the number of coarse adjustment steps can be gradually increased as needed to increase the coarse adjustment range of the phase of the clock signal. Figure 1 In the figure, there are 6 inverters N1 to N6 between the front end and the back end of the phase interpolator "PI 24step". Ideally, the clock signals between the front end and the back end of the phase interpolator "PI 24step" should differ by 3 coarse adjustment steps. If the front end load of the phase interpolator "PI 24step" is large, the rising and falling edges of the clock signal driven by it will no longer be vertically upward and vertically downward, but will become a state of relatively slow rise and fall. This will make the high-level duration of the clock signal in the fine adjustment stage, which should be equivalent to 3 coarse adjustment steps, become a high-level duration of the clock signal less than 3 coarse adjustment steps, thereby making the matching between coarse adjustment and fine adjustment worse.

[0035] To summarize, when there is only one phase interpolator in the fine-grained phase adjustment module, simply relying on continuously increasing the number of inverters in the phase interpolator to expand the clock phase adjustment range of the fine-grained phase adjustment module will not only cause excessive load to limit the operating frequency of the phase interpolator, but also cause the matching between the fine-grained phase adjustment module and the coarse-grained phase adjustment module to deteriorate due to the excessive load.

[0036] To this end, an embodiment of the present application provides a clock phase adjustment system, which includes a fine-grained phase adjustment module and a coarse-grained phase adjustment module, wherein the coarse-grained phase adjustment module includes a first input end for receiving a clock signal, a first number of coarse adjustment sub-modules for performing coarse-grained phase adjustment on the clock signal, and a first output end for outputting a coarsely adjusted clock signal, a coarse adjustment sub-module is composed of two inverters connected in series and one inverter connected in parallel, and the first number of coarse adjustment sub-modules are connected in series, and the fine-grained phase adjustment module includes a second input end for receiving a coarsely adjusted clock signal, a second number of fine adjustment sub-modules for performing fine-grained phase adjustment on the coarsely adjusted clock signal, and the second number of fine adjustment sub-modules are connected in parallel, and a second output end for outputting a finely adjusted clock signal, and a fine adjustment sub-module is composed of a phase interpolator with a specified number of steps and two inverters connected in series.

[0037] Since the fine-grained phase adjustment module is composed of multiple fine-tuning submodules connected in parallel, and each fine-tuning submodule is composed of a phase interpolator with a specified number of steps and two inverters connected in series, the load of the input clock signal of each phase interpolator is effectively reduced, thereby enabling the entire clock phase adjustment system to achieve a higher operating frequency. At the same time, since the fine-grained phase adjustment modules all adopt a parallel structure, the fine adjustment range of multiple parallel fine-tuning submodules is the superposition value of the fine adjustment range of each fine-tuning submodule, therefore, it can also ensure that the clock phase adjustment system has a larger fine-grained phase adjustment range. Similarly, the coarse-grained phase adjustment module adopts a structure in which multiple coarse-tuning submodules are connected in series, which can ensure that the clock phase adjustment system has a larger coarse-grained phase adjustment range, thereby ensuring that the overall phase adjustment range of the clock phase adjustment system is larger.

[0038] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0039] Figure 3 The structure diagram of a clock phase adjustment system provided by the exemplary embodiment of the present application is shown in FIG. Figure 3 As shown, the system may include a fine-grained phase adjustment module FT1 and a coarse-grained phase adjustment module CT1, wherein:

[0040] The coarse-grained phase adjustment module CT1 comprises a first input terminal I21 for receiving a clock signal, a first number N of coarse adjustment submodules CT11 to CT12 for performing coarse-grained phase adjustment on the clock signal, and a first number N of coarse adjustment submodules CT11 to CT13 for performing coarse-grained phase adjustment on the clock signal. N , and a first output terminal O21 for outputting a coarsely adjusted clock signal, wherein a coarse adjustment submodule is composed of two inverters connected in series and one inverter connected in parallel, and a first number of coarse adjustment submodules are connected in series;

[0041] The fine-grained phase adjustment module FT1 comprises a second input terminal I22 for receiving a coarsely adjusted clock signal, a second number M of fine adjustment submodules FT11 to FT12 for performing fine-grained phase adjustment on the coarsely adjusted clock signal, and a second number M of fine adjustment submodules FT11 to FT13 for performing fine-grained phase adjustment on the coarsely adjusted clock signal. M , and a second output terminal O22 for outputting a fine-tuned clock signal, a fine-tuning submodule is composed of a phase interpolator with a specified number of steps and two inverters connected in series, a second number of fine-tuning submodules FT11 to FT1 M Connect in parallel.

[0042] There is no direct constraint relationship between the first number and the second number, and the numerical values ​​of the first number and the second number can be set according to the range requirements of coarse adjustment and fine adjustment.

[0043] After the clock signal ckin to be adjusted is input into the clock signal phase adjustment system through the first input terminal I21, it passes through the coarse-grained phase adjustment module CT1 and the fine-grained phase adjustment module FT1 in sequence, and is finally output from the second output terminal O22. The clock signal ckout output from the second output terminal O22 has a certain phase delay relative to the clock signal ckin to be adjusted, such as Figure 4 As shown, it is a schematic diagram of the phase delay of the clock signal ckin to be adjusted input to the clock phase adjustment system relative to the clock signal ckout output. The function of the clock phase adjustment system provided in the embodiment of the present application is to achieve precise adjustment of the phase delay between the clock signal ckin and the clock signal ckout by controlling the coarse-grained phase adjustment module CT1 and the fine-grained phase adjustment module FT1.

[0044] In the coarse tuning submodule CT11, inverters N11 and N12 are connected in series and then connected in parallel with inverter N13; in the coarse tuning submodule CT12, inverters N21 and N22 are connected in series and then connected in parallel with inverter N23; ..., the coarse tuning submodule CT1 N The inverters Nn1 and Nn2 are connected in series and then in parallel with the inverter Nn3. The states of these inverters can be controlled by a control signal of the coarse-grained phase adjustment module CT1. The control signal can be sent by the control module CM to the coarse-grained phase adjustment module CT1.

[0045] The fine tuning submodule FT11 is composed of a phase interpolator PI with a specified number of steps (X step) and two inverters (N1 and N2) connected in series, the fine tuning submodule FT12 is composed of a phase interpolator PI with a specified number of steps (X step) and two inverters (N3 and N4) connected in series, ..., the fine tuning submodule FT1 MIt is composed of a phase interpolator PI with a specified number of steps (X step) and two inverters (N(2M-1) and N2M) connected in series. The state of the phase interpolator PI in each fine tuning submodule can be controlled by the control signal of the fine granularity phase adjustment module FT1, and the control signal can be sent by the control module CM to the fine granularity phase adjustment module FT1.

[0046] In some exemplary embodiments, in order to facilitate the control of the coarse adjustment range of the coarse-grained phase adjustment module CT1 and the fine adjustment range of the fine-grained phase adjustment module FT1, thereby combining the coarse adjustment and fine adjustment ranges to achieve refined clock phase adjustment, the system may also include a control module CM, which is connected to the fine-grained phase adjustment module FT1 and is used to input a control signal to the phase interpolator in each fine adjustment submodule in the fine-grained phase adjustment module FT1 to control the state of each inverter in the phase interpolator. The control module CM may also be connected to the coarse-grained phase adjustment module CT1 and is used to input a control signal to the coarse-grained phase adjustment module CT1 to control the state of the inverter in each coarse adjustment submodule.

[0047] In some exemplary embodiments, the control signal from the control module CM includes a first control signal and a second control signal, the first control signal is used to control the state of the phase interpolator of the target fine tuning submodule in the fine-grained phase adjustment module, and the second control signal is used to control the state of each inverter in the phase interpolator of the target fine tuning submodule, and the second control signal is input to the target fine tuning submodule by the control module after a preset time period after the first control signal is output.

[0048] When adjusting the clock phase signal, since it may involve repeated adjustment operations, for example, after the fine tuning submodule FT12 is turned on, the phase delay of the clock signal obtained exceeds the phase delay of the target clock signal. In this case, the phase interpolator and inverters N2 and N3 in the fine tuning submodule FT12 may need to be turned off, and the fine tuning submodule FT11 may be turned on again. In this case, since each component needs a certain amount of time to respond to the control signal, the fine tuning submodule FT12 and the fine tuning submodule FT11 may be in a closed state within a very short period of time, resulting in an uncertain state of the output signal. At this time, a glitch signal with a very short high level duration will appear in the clock signal. In order to avoid this situation, the embodiment of the present application separates the sending time of the second control signal and the first control signal by a preset time period. The preset time period can be the average time length of the phase interpolator receiving the control signal and fully responding to the control signal, that is, the second control signal can be input to the target fine tuning submodule by the control module after the preset time period after the first control signal is output.

[0049] In some exemplary embodiments, the second control signal is also used to control the state of each inverter in the phase interpolator of other fine tuning submodules in the fine-grained phase adjustment module. And in order to further avoid the phenomenon of a glitch signal with a very short high-level duration in the adjusted clock signal, the embodiment of the present application is also designed for the initial state of the inverter of the phase interpolator in other fine tuning submodules when the target fine tuning submodule is turned on. Specifically, after determining to turn on the target fine tuning submodule in FT1 in the fine-grained phase adjustment module based on the first control signal, the initial state of the phase interpolator in the target fine tuning submodule can be set to a state in which all the inverters in the left group are turned on and all the inverters in the right are turned off, and at the same time, the initial state of the phase interpolator in the fine tuning submodule on the left side of the target fine tuning submodule is set to an initial state in which all the inverters in the right group are turned on and all the inverters in the left side are turned off, and at the same time, the phase interpolator in the fine tuning submodule on the right side of the target fine tuning submodule is set to a closed state. When the phase interpolator in each fine tuning submodule is in the off state, it can also be set to an initial state in which a group of inverters on the left are all turned on and a group of inverters on the right are all turned off.

[0050] Among them, in the second control signal, the control signal for controlling the state of each inverter in the phase interpolator of the target fine tuning submodule and the control signal for controlling the state of each inverter in the phase interpolator of other fine tuning submodules in the fine-grained phase adjustment module can be issued simultaneously, that is, the state of each inverter in the phase interpolator of the target fine tuning submodule and the state of each inverter in the phase interpolator of other fine tuning submodules are carried in one control signal.

[0051] In addition, the control signal from the control module CM may also include a third control signal, which is used to control the state of the inverter in each coarse adjustment module in the coarse granularity phase adjustment module. For example, when it is desired to adjust the clock phase of the clock signal input to I21 within a range of 1 coarse adjustment step, the third control signal may carry a control signal indicating that the inverters N11 and N12 in the coarse adjustment submodule CT11 are turned on. On this basis, if it is desired to adjust the clock phase of the clock signal input to I21 within a range of 2 coarse adjustment steps, the third control signal may carry a control signal indicating that the inverters N21 and N22 in the coarse adjustment submodule CT12 and the inverter N13 in the coarse adjustment submodule CT11 are turned on, and indicating that the inverter N12 in the coarse adjustment submodule CT11 is turned off. The embodiment of the present application does not limit the specific form of expression of the third control signal, for example, the third control signal may be formed in the form of the identifier of each inverter + a number used to indicate whether the inverter is turned on (1) or off (0).

[0052] It should be understood that after obtaining the clock signal to be adjusted, the values ​​of the coarse adjustment step and the fine adjustment step can be preliminarily determined according to the phase delay between the clock signal to be adjusted and the target clock signal (i.e., the adjustment target of the clock signal to be adjusted), and the first control signal, the second control signal and the third control signal can be determined based on the values ​​of the coarse adjustment step and the fine adjustment step, that is, the state (on or off) of the inverter in each coarse adjustment module in the coarse-grained phase adjustment module CT1 is respectively determined, that is, which coarse adjustment module is used, the state of each fine adjustment module in FT1 in the fine-grained phase adjustment module (determine which fine adjustment module is turned on), and the state of the inverter in each fine adjustment module.

[0053] In some exemplary embodiments, a phase interpolator with a specified number of steps is composed of two groups of specified numbers of inverters, one group of specified number of inverters is composed of a specified number of inverters connected in parallel, and the output ends of the two groups of specified number of inverters are connected to the output end of the phase interpolator, wherein the input end of the left group of specified number of inverters is connected to the front end of the phase interpolator, and the input end of the right group of specified number of inverters is connected to the back end of the phase interpolator.

[0054] In some exemplary embodiments, a front end of a phase interpolator with a specified number of steps is connected to the input ends of two inverters, a rear end of a phase interpolator with a specified number of steps is connected to the output ends of the two inverters, and the two inverters are connected in series.

[0055] In some exemplary embodiments, the fine-grained phase adjustment module also includes a first inverter, whose input end is connected to the output end of a second number of fine adjustment submodules, and is used to process the fine-tuned clock signals output by the second number of fine adjustment submodules to obtain a phase-adjusted clock signal as an output signal of the second output end.

[0056] Figure 5 This is a schematic diagram of the structure of a target fine adjustment submodule of a fine-grained phase adjustment module in a clock phase adjustment system provided in an embodiment of the present application. Figure 5 As shown, the target fine tuning submodule consists of a phase interpolator with an interpolation number of 8 steps ( Figure 5The PI 8step shown in the figure is connected in series with two inverters with a driving capability of X8. Among them, the phase interpolator with an interpolation number of 8 steps is composed of two groups of inverters, and each group of inverters is composed of 8 inverters with a driving capability of X1 in parallel. The input end of the inverter of the left group of these two groups of inverters is connected to the front end of the phase interpolator, and the input end of the inverter of the right group is connected to the back end of the phase interpolator. The output ends of these two groups of inverters are connected to the output end pi_out of the phase interpolator. Since the input signals of the front end and the back end of the phase differentiator are separated by two inverters with a driving capability of X8, it can be considered that the phase delay between the input signals of the front end and the back end of the phase differentiator is a coarse adjustment step.

[0057] Theoretically, the driving capability of 8 x1 inverters in parallel is usually the same as that of 1 x8 inverter, and the phase delay of the clock signal processed is also the same. Figure 5 The left group of inverters of the phase interpolator shown are all turned on, and the right group of inverters are all turned off. Then the clock signal input to the phase interpolator is only the clock signal input from the front end, that is, at this time, the clock signal output by the output terminal pi_out of the phase interpolator is only the clock signal input from the front end processed by two X8 inverters (equivalent to the signal input from the front end after a coarse adjustment step).

[0058] If Figure 5 The phase interpolator shown has 7 inverters on the left side and 1 inverter on the right side. The clock signal input to the phase interpolator is composed of the clock signal input from the front end and the clock signal input from the back end. The clock signal output from the output terminal pi_out of the phase interpolator can be obtained by subtracting the clock signal input from the front end through 7 parallel x1 inverters and the clock signal input from the back end through 1 x1 inverter. At this time, the clock signal output from the output terminal pi_out of the phase interpolator is a clock signal obtained by a fine-tuning step relative to the clock signal obtained by fully opening the left inverter in the phase interpolator. That is, the phase of the clock signal obtained in this case has a phase delay of a fine-tuning step relative to the phase of the clock signal obtained by fully opening the left inverter in the phase interpolator.

[0059] If Figure 5The phase interpolator shown has 6 inverters on the left side and 2 inverters on the right side. The clock signal input to the phase interpolator is composed of the clock signal input from the front end and the clock signal input from the back end. The clock signal output from the output terminal pi_out of the phase interpolator can be obtained by subtracting the clock signal input from the front end through 6 parallel x1 inverters and the clock signal input from the back end through 2 parallel x1 inverters. At this time, the clock signal output from the output terminal pi_out of the phase interpolator is a clock signal obtained by 2 fine-tuning steps relative to the clock signal obtained by fully opening the left inverter in the phase interpolator. That is, the phase of the clock signal obtained in this case has a phase delay of 2 fine-tuning steps relative to the phase of the clock signal obtained by fully opening the left inverter in the phase interpolator.

[0060] ... and so on. If Figure 5 The right group of inverters of the phase interpolator shown in the figure are all turned on, and the left group of inverters are all turned off. Then, the clock signal input to the phase interpolator is only the clock signal input from the back end, that is, the clock signal output by the output terminal pi_out of the phase interpolator at this time is only the clock signal input from the back end through two X8 inverters (equivalent to the signal input from the back end after one coarse adjustment step, that is, 8 fine adjustment steps). Since the clock signals input from the front end and the back end differ by one coarse adjustment step, the fine adjustment submodule of a phase interpolator with an interpolation number of 8 steps can adjust the fine adjustment range to one coarse adjustment step. Based on Figure 5 The principle of the phase interpolator shown in the figure can be used to determine the phase delay obtained by a coarse adjustment step and the phase delay obtained by a fine adjustment step through simulation. As an example, through simulation, it can be determined that the phase delay of a coarse adjustment step is 16ps and the phase delay of a fine adjustment step is 2ps, that is, using Figure 5 The fine adjustment submodule shown can achieve an adjustment accuracy of 2ps for clock phase adjustment. Therefore, the first control signal, the second control signal and the third control signal can be determined based on the phase difference between the clock signal to be adjusted and the target clock signal, that is, it can be determined how many coarse adjustment steps and how many fine adjustment steps are needed to adjust the clock signal to be adjusted to a clock phase consistent with the target clock signal.

[0061] Obviously, when the number of x1 inverters turned on in the left group of the phase interpolator is greater than the number of x1 inverters turned on in the right group, the phase of the clock signal output by the phase interpolator is closer to the clock signal input at the front end, and when the number of x1 inverters turned on in the right group of the phase interpolator is greater than the number of x1 inverters turned on in the left group, the phase of the clock signal output by the phase interpolator is closer to the clock signal input at the back end.

[0062] in, Figure 5 The states of the inverters on the left and right sides of the phase interpolator of the target fine tuning submodule shown can be controlled by a second control signal, which can be in the form of two groups of binary digits, such as "111111111, 0000000", which is used to indicate that the inverters in the left group are all turned on and the inverters in the right group are all turned off. Figure 6 Schematic diagram of the relationship between the coarse adjustment delay and the fine adjustment delay in the phase delay of the clock signal ckin to be adjusted input to the clock phase adjustment system relative to the output clock signal ckout. Figure 6 It can be seen that the fine adjustment of the clock signal is performed within the range of the coarse adjustment phase delay.

[0063] Figure 7 An example diagram of a clock phase adjustment system provided in an embodiment of the present application. Figure 7 In the embodiment, the fine-grained phase adjustment module FT1 includes three fine-tuning submodules FT11 to FT13, each of which is composed of a phase interpolator with an interpolation number of 8 steps and two inverters connected in series, and the three fine-tuning submodules FT11 to FT13 are connected in parallel. Among them, the fine-tuning submodule FT11 is composed of a phase interpolator with an interpolation number of 8 steps and inverters N1 and N2 connected in series, the fine-tuning submodule FT12 is composed of a phase interpolator with an interpolation number of 8 steps and inverters N3 and N4 connected in series, and the fine-tuning submodule FT13 is composed of a phase interpolator with an interpolation number of 8 steps and inverters N5 and N6 connected in series. As an example, Figure 7 The inverter in the clock phase adjustment system shown uses an inverter with a driving capability of x8. Figure 7 The inverter in the phase interpolator shown adopts an inverter with a driving capability of x1. When the phase interpolator in the fine tuning submodule FT11 is turned on, the phase of the output clock signal is within the phase interval of the clock signals output by the front end and the front end 2, when the phase interpolator in the fine tuning submodule FT12 is turned on, the phase of the output clock signal is within the phase interval of the clock signals output by the front end 2 and the back end 2, and when the phase interpolator in the fine tuning submodule FT13 is turned on, the phase of the output clock signal is within the phase interval of the clock signals output by the back end 2 and the back end.

[0064] Obviously, compared to Figure 1 The clock phase adjustment system shown uses a phase interpolator with an interpolation number of 24 steps for fine adjustment. The present application connects three phase interpolators with an interpolation number of 8 steps in parallel, which can effectively reduce the load of the input clock of each phase interpolator, so that the fine-grained phase adjustment module FT1 can operate at a higher frequency. The fine-tuning range of the fine-tuning module FT1 composed of multiple fine-tuning sub-modules connected in parallel is also the sum of the fine-tuning ranges of these multiple fine-tuning sub-modules. The fine-tuning sub-modules connected in parallel can be increased according to demand, so as to ensure that the range of the fine-tuning sub-module is large enough. In addition, the fine-tuning sub-module composed of a phase interpolator with a smaller interpolation number has a smaller load, and its rising edge and falling edge are closer to vertical upward and vertical downward, so the linearity of its fine-tuning step will also be better.

[0065] Figure 8 The control module in the clock phase adjustment system provided in the embodiment of the present application Figure 7 The schematic diagram of each phase interpolator sending a control signal is shown in FIG. Figure 8 In the embodiment, after Data_ft<4:3> is used to select and open the phase interpolator in a fine tuning submodule, the control signal also sends a second control signal to the phase interpolator in each fine tuning submodule. The second control signal can be integrated and sent to the decoder via the multiplexer MUX, and the decoder decodes to obtain the control instructions with a length of 16 bits in the first control signal and the second control signal. Among them, Data_ft<2:0> is used to indicate the state of each inverter in the turned-on phase interpolator, which belongs to the second control signal. Code=7lag or Code=0ahead (wherein Code=7lag is used to indicate the fully-on state of the inverters in the right group, and Code=0ahead is used to indicate the fully-on state of the inverters in the left group) is used to indicate the initial state of the phase interpolator of each fine tuning submodule in the fine-grained phase adjustment module FT1, which also belongs to the second control signal.

[0066] Combined with the figure, we can see that there are 3 parallel 8-step PIs. Note that only one of the PIs is turned on at a time. When PI0 is turned on, the pi_out output clock phase is between ahead and ahead2; when PI1 is turned on, the pi_out output clock phase is between ahead2 and lag2; when PI2 is turned on, the pi_out output clock phase is between lag2 and lag; and there is just a delay of about 3 coarse adjustment steps between ahead and lag; so the fine adjustment range of LCDL in this solution is wider.

[0067] Fig. 9 To adopt Figure 7The schematic diagram shows the size of the phase delay adjusted by a fine adjustment step and the difference between the phase delays adjusted by different fine adjustment steps obtained by the clock phase adjustment system through clock phase adjustment statistics. Fig. 9 The ordinate is the mark of the fine-tuning step, and the ordinate is time, with the unit being ps. It can be seen that the size of a fine-tuning step jumps around 2ps, and the phase delay adjusted by different fine-tuning steps jumps around 0, indicating that the overall fine-tuning linearity is good.

[0068] The clock phase adjustment system provided by the embodiment of the present application includes a fine-grained phase adjustment module and a coarse-grained phase adjustment module. Since the fine-grained phase adjustment module is composed of a plurality of fine-tuning submodules connected in parallel, and each fine-tuning submodule is composed of a phase interpolator with a specified number of steps and two inverters connected in series, the load of the input clock signal of each phase interpolator is effectively reduced, thereby enabling the entire clock phase adjustment system to achieve a higher operating frequency. At the same time, since both the coarse-grained phase adjustment module and the fine-grained phase adjustment module adopt a parallel structure, taking the fine-grained phase adjustment module as an example, the fine adjustment range of the plurality of fine-tuning submodules in parallel is the superposition value of the fine adjustment range of each fine-tuning submodule, therefore, it can also ensure that the clock phase adjustment system has a larger fine-grained phase adjustment range. Similarly, the coarse-grained phase adjustment module also adopts a structure of a plurality of coarse-tuning submodules in parallel, which can also ensure that the clock phase adjustment system has a larger coarse-grained phase adjustment range, thereby ensuring that the overall phase adjustment range of the clock phase adjustment system is larger.

[0069] Fig.10 This is a schematic diagram of the structure of an integrated circuit / interface chip / system on chip / electronic device 3000 provided by an exemplary embodiment of the present application. The integrated circuit / interface chip / system on chip / electronic device includes Figure 1 A clock phase adjustment system 300 is shown.

[0070] about Fig.10 The specific implementation of the integrated circuit / interface chip / system on chip / electronic device shown has been described in detail in the embodiment of the clock phase adjustment system, and will not be elaborated here.

[0071] Fig.11 The following is a flow chart of a clock phase adjustment method provided by an exemplary embodiment of the present application. Fig.11 As shown, the method may include:

[0072] Step 1110: determine the phase difference between the clock signal to be adjusted and the target clock signal.

[0073] The phase of the target clock signal is the adjustment target of the clock signal to be adjusted. The phase difference between the two can be represented by the phase delay between the nearest rising edges or falling edges.

[0074] Step 1120: Using the clock signal to be adjusted as an input signal of a coarse-grained phase adjustment module, and performing coarse-grained phase adjustment on the clock signal to be adjusted based on the phase difference to obtain a clock signal after coarse-grained phase adjustment.

[0075] Assuming that the phase difference between the clock signal to be adjusted and the target clock signal is 40ps, and assuming that the phase delay obtained by one coarse adjustment step in the coarse-grained phase adjustment is 16ps, it can be determined based on the phase difference that the coarse-grained phase adjustment module needs to perform 40 / 16=2 coarse adjustment steps of coarse-grained phase adjustment on the clock signal to be adjusted. Specifically, a third control signal can be sent to the coarse-grained phase adjustment module CT1 to instruct the inverters N11 and N13 in the coarse adjustment submodule CT11 and the inverters N21 and N22 in the coarse adjustment submodule to turn on, and to instruct other inverters to turn off.

[0076] Step 1130: using the coarse-grained phase-adjusted clock signal as an input signal of a fine-grained phase adjustment module, and performing fine-grained phase adjustment on the coarse-grained phase-adjusted clock signal based on the phase difference through the fine-grained phase adjustment module.

[0077] Continuing with the above example, since the phase difference between the clock signal to be adjusted and the target clock signal is 40ps, it has been determined that the clock signal to be adjusted needs to be subjected to a coarse-grained phase adjustment of 2 coarse-adjustment steps. The clock signal to be adjusted still has a remaining phase delay of 40-2×16=8ps that needs to be adjusted. Assuming that the phase delay obtained by one fine-adjustment step in the fine-grained phase adjustment is 2ps, it can be determined based on the phase difference that the fine-grained phase adjustment module needs to perform 8 / 2=4 fine-adjustment steps of fine-grained phase adjustment on the clock signal to be adjusted.

[0078] In some exemplary embodiments, fine-grained phase adjustment is performed on the coarse-grained phase-adjusted clock signal based on the phase difference by a fine-grained phase adjustment module, including:

[0079] Based on the phase difference, determining a control signal;

[0080] Based on the control signal, the state of the phase interpolator of the target fine tuning submodule to be turned on is controlled from the fine granularity phase adjustment module, as well as the states of each inverter in the phase interpolator of other fine tuning submodules in the fine granularity phase adjustment module;

[0081] When the fine-grained phase adjustment module is controlled by the control signal, a clock signal after the coarse-grained phase adjustment is obtained, which is a fine-adjusted clock signal;

[0082] The control signal is updated based on a phase difference between the fine-tuned clock signal and the target clock signal, and the fine-tuned clock signal is updated based on the updated control signal.

[0083] Specifically, a first control signal instructing the fine tuning submodule FT11 to turn on, and a second control signal instructing the fine tuning submodule FT11 to turn on 6 inverters in a left group and 2 inverters in a right group, may be sent to the fine granularity phase adjustment module FT1.

[0084] It should be understood that in the actual phase adjustment process, the simulation data and the actual adjustment data of the clock phase adjustment system may have a certain deviation. In this case, the specific values ​​of the coarse adjustment step and the fine adjustment step obtained based on theoretical calculation may not be able to adjust the clock signal to the phase of the target clock signal. In view of this, the control signal can be updated according to the phase difference between the clock signal obtained by actual adjustment and the target clock signal. For example, when it is determined that the phase difference between the clock signal obtained by actual adjustment and the target clock signal is a negative number, that is, when the value of the determined fine adjustment step is not enough, the value of the fine adjustment step can be increased, that is, in the above example, the number of inverters in the left group of the fine adjustment submodule FT11 that are turned on is reduced, and the number of inverters in the right group of the fine adjustment submodule FT11 that are turned on is increased. If it is determined that the phase difference between the clock signal obtained by actual adjustment and the target clock signal is a positive number, that is, when the value of the determined fine adjustment step is too high, the value of the fine adjustment step can also be reduced, that is, in the above example, the number of inverters in the left group of the fine adjustment submodule FT11 that are turned on is increased, and the number of inverters in the right group of the fine adjustment submodule FT11 that are turned on is reduced. That is, when the clock phase system provided in the embodiment of the present application is used to adjust the clock phase, it not only supports the adjustment operation of increasing the adjusted clock phase delay but also supports the adjustment operation of reducing the adjusted clock phase delay.

[0085] Fig.11 For details on the implementation of the clock phase adjustment method shown in FIG. Figure 3 to Figure 9 The clock phase adjustment system of the illustrated embodiment will not be described in detail.

[0086] The clock phase adjustment method provided in the embodiment of the present application is applied to the clock phase adjustment system, and can determine the phase difference between the clock signal to be adjusted and the target clock signal, and use the clock signal to be adjusted as the input signal of the coarse-grained phase adjustment module, and perform coarse-grained phase adjustment on the clock signal to be adjusted based on the phase difference to obtain the clock signal after coarse-grained phase adjustment, and finally use the clock signal after coarse-grained phase adjustment as the input signal of the fine-grained phase adjustment module, and perform fine-grained phase adjustment on the clock signal after coarse-grained phase adjustment based on the phase difference through the fine-grained phase adjustment module. Since both the coarse-grained phase adjustment module and the fine-grained phase adjustment module adopt a parallel structure, the fine adjustment range of the parallel multiple fine adjustment submodules is the superposition value of the fine adjustment range of each fine adjustment submodule, therefore, it can also ensure that the clock phase adjustment system has a larger fine-grained phase adjustment range, and the use of multiple fine adjustment submodules in parallel can also effectively reduce the load of each fine adjustment submodule, thereby avoiding the problem of limited working frequency and mismatch between coarse adjustment and fine adjustment caused by excessive load. Similarly, the coarse-grained phase adjustment module also adopts a structure in which multiple coarse-grained adjustment submodules are connected in parallel, which can also ensure that the clock phase adjustment system has a larger coarse-grained phase adjustment range, thereby ensuring that the overall phase adjustment range of the clock phase adjustment system is larger.

[0087] It should be noted that the execution subject of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, the execution subject of steps 1110 to 1130 can be device A; for another example, the execution subject of steps 1110 to 1120 can be device A, and the execution subject of step 1130 can be device B; and so on.

[0088] In addition, in some of the processes described in the above embodiments and the accompanying drawings, multiple operations that appear in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this article or executed in parallel, and the sequence numbers of the operations, such as 1110, 1120, etc., are only used to distinguish between different operations, and the sequence numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this article are used to distinguish different messages, devices, modules, etc., do not represent the order of precedence, and do not limit the "first" and "second" to be different types.

[0089] Fig.12 FIG. 1 is a schematic diagram of a clock phase adjustment device 1200 provided in an exemplary embodiment of the present application. Fig.12 As shown, the device includes: a phase difference determination module 1210, a signal coarse adjustment module 1220 and a signal fine adjustment module 1230, wherein:

[0090] A phase difference determination module 1210, configured to determine a phase difference between a clock signal to be adjusted and a target clock signal;

[0091] A signal coarse adjustment module 1220, configured to use the clock signal to be adjusted as an input signal of the coarse-grained phase adjustment module, and perform coarse-grained phase adjustment on the clock signal to be adjusted based on the phase difference to obtain the clock signal after the coarse-grained phase adjustment;

[0092] The signal fine adjustment module 1230 is used to use the clock signal after the coarse-grained phase adjustment as the input signal of the fine-grained phase adjustment module, and to perform fine-grained phase adjustment on the clock signal after the coarse-grained phase adjustment based on the phase difference through the fine-grained phase adjustment module.

[0093] The structure of the clock phase adjustment device, the signal flow and processing process, and the technical effects achieved can be found in the following Figure 3 to Figure 9 The structure of the clock phase adjustment system of the illustrated embodiment will not be described in detail.

[0094] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0095] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A clock phase adjustment system, characterized in that: The system includes a fine-grained phase adjustment module and a coarse-grained phase adjustment module, wherein: The coarse-grained phase adjustment module comprises a first input terminal for receiving a clock signal, a first number of coarse-grained adjustment submodules for performing coarse-grained phase adjustment on the clock signal, and a first output terminal for outputting the coarsely adjusted clock signal, wherein one of the coarse-grained adjustment submodules is composed of two inverters connected in series and one inverter connected in parallel, and the first number of coarse-grained adjustment submodules are connected in parallel; The fine-grained phase adjustment module includes a second input terminal for receiving the coarsely adjusted clock signal, a second number of fine-tuning sub-modules for performing fine-grained phase adjustment on the coarsely adjusted clock signal, and a second output terminal for outputting the fine-tuned clock signal, wherein one of the fine-tuning sub-modules is composed of a phase interpolator with a specified number of steps and two inverters connected in series, and the second number of fine-tuning sub-modules are connected in series.

2. The system according to claim 1, characterized in that The system also includes a control module, which is connected to the fine-grained phase adjustment module and is used to input a control signal to the phase interpolator in each fine adjustment submodule in the fine-grained phase adjustment module to control the state of each inverter in the phase interpolator.

3. The system according to claim 2, characterized in that The control signal from the control module includes a first control signal and a second control signal. The first control signal is used to control the state of the phase interpolator of the target fine adjustment submodule in the fine-grained phase adjustment module, and the second control signal is used to control the state of each inverter in the phase interpolator of the target fine adjustment submodule. The second control signal is input from the control module to the target fine adjustment submodule after a preset time period after the first control signal is output.

4. The system according to claim 3, characterized in that The second control signal is also used to control the state of each inverter in the phase interpolator of other fine adjustment submodules in the fine granularity phase adjustment module.

5. The system according to any one of claims 1 to 4, characterized in that: A phase interpolator with the specified number of steps is composed of two groups of inverters with a specified number, one group of the specified number of inverters is composed of the specified number of inverters connected in parallel, and the output ends of the two groups of inverters with the specified number are connected to the output end of the phase interpolator, wherein the input end of the left group of inverters with the specified number is the front end of the phase interpolator, and the input end of the right group of inverters with the specified number is the back end of the phase interpolator.

6. The system according to claim 5, characterized in that A front end of a phase interpolator with the specified number of steps is connected to the input ends of the two inverters, a rear end of a phase interpolator with the specified number of steps is connected to the output ends of the two inverters, and the two inverters are connected in series.

7. The system according to claim 1, characterized in that The fine-grained phase adjustment module also includes a first inverter, whose input end is connected to the output end of the second number of fine adjustment submodules, and is used to process the fine-tuned clock signals output by the second number of fine adjustment submodules to obtain a phase-adjusted clock signal as the output signal of the second output end.

8. An integrated circuit, characterized in that: The integrated circuit comprises the clock phase adjustment system according to any one of claims 1 to 7.

9. An interface chip, characterized in that: The interface chip comprises the clock phase adjustment system according to any one of claims 1 to 7.

10. A system on chip, characterized in that: The system on chip comprises the clock phase adjustment system according to any one of claims 1 to 7.

11. An electronic device, characterized in that: The electronic device comprises the clock phase adjustment system according to any one of claims 1 to 7.

12. A clock phase adjustment method, characterized in that: The method is applied to the clock phase adjustment system according to any one of claims 1 to 7, and the method comprises: Determining a phase difference between a clock signal to be adjusted and a target clock signal; Using the clock signal to be adjusted as an input signal of the coarse-grained phase adjustment module, and performing coarse-grained phase adjustment on the clock signal to be adjusted based on the phase difference to obtain the coarse-grained phase-adjusted clock signal; The coarse-grained phase-adjusted clock signal is used as an input signal of the fine-grained phase adjustment module, and the fine-grained phase adjustment module performs fine-grained phase adjustment on the coarse-grained phase-adjusted clock signal based on the phase difference.

13. The method according to claim 12, characterized in that The fine-grained phase adjustment module performs fine-grained phase adjustment on the coarse-grained phase-adjusted clock signal based on the phase difference, including: determining a control signal based on the phase difference; Based on the control signal, controlling the state of the phase interpolator of the target fine tuning submodule to be turned on in the fine granularity phase adjustment module, and the states of each inverter in the phase interpolator of other fine tuning submodules in the fine granularity phase adjustment module; When the fine-grained phase adjustment module is controlled by the control signal, a clock signal after the coarse-grained phase adjustment is finely adjusted is obtained; The control signal is updated based on a phase difference between the fine-tuned clock signal and the target clock signal, and the fine-tuned clock signal is updated based on the updated control signal.

14. A clock phase adjustment device, characterized in that: The device is applied to the clock phase adjustment system according to any one of claims 1 to 7, comprising: A phase difference determination module, used to determine the phase difference between the clock signal to be adjusted and the target clock signal; A signal coarse adjustment module, used for taking the clock signal to be adjusted as an input signal of a coarse-grained phase adjustment module, and performing coarse-grained phase adjustment on the clock signal to be adjusted based on the phase difference to obtain the clock signal after the coarse-grained phase adjustment; The signal fine adjustment module is used to use the clock signal after the coarse-grained phase adjustment as the input signal of the fine-grained phase adjustment module, and to perform fine-grained phase adjustment on the clock signal after the coarse-grained phase adjustment based on the phase difference through the fine-grained phase adjustment module.

Images