Jitter cancelling circuit, communication unit, and communication system

Abstract

The invention discloses a jitter elimination circuit, a communication unit and a communication system. The jitter elimination circuit comprises a first phase-locked loop and a second phase-locked loop, the first phase-locked loop is used for generating a first clock signal based on a reference clock signal, and the second phase-locked loop is used for generating an adjusting signal for adjusting the frequency dividing ratio of the first phase-locked loop based on an error between the second clock signal and the first clock signal. According to the jitter elimination circuit, the communication unit and the communication system, in the multi-node communication system, the jitter elimination circuit is arranged in the communication unit, jitter elimination can be carried out on the clock signal of any node, and therefore communication of any number of nodes is not limited by clock jitter any more.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a jitter elimination circuit, a communication unit and a communication system. Background Art

[0002] For multi-node communication systems, such as Figure 1 As shown in the figure, each node in the system needs a clock to process and transmit signals. If each node is synchronized to the local crystal oscillator, the clock quality of all nodes can be guaranteed. However, due to the frequency difference between different crystal oscillators, data transmission errors may occur. In order to ensure the correctness of data transmission, the clocks inside all nodes on the link need to be synchronized. For example, the host sends a clock signal to the master node, and then the slave node recovers the clock signal based on the data sent by the upstream node. In this way, the clock signals of the master and slave nodes are synchronized and the correct data transmission is guaranteed. However, the jitter of the clock signal will increase with each additional node the clock signal embedded in the data passes through. As shown in the figure, the clock signal of the master and slave nodes is synchronized with each other. Figure 2 As shown, as the number of transmission nodes increases, the jitter of the clock signals of the last few nodes has become so large that it cannot meet the system requirements, which becomes a factor limiting the maximum number of nodes in a multi-node communication system.

[0003] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0004] The object of the present invention is to provide a jitter elimination circuit, a communication unit and a communication system, which can realize communication of any number of nodes without being restricted by clock signal jitter.

[0005] In order to achieve the above-mentioned object, a technical solution provided by a specific embodiment of the present invention is as follows: a jitter elimination circuit comprises: a first phase-locked loop and a second phase-locked loop;

[0006] The first phase-locked loop is used to generate a first clock signal based on a reference clock signal, and the second phase-locked loop is used to generate an adjustment signal for adjusting a frequency division ratio of the first phase-locked loop based on an error between the second clock signal and the first clock signal.

[0007] In one or more embodiments of the present invention, the jitter elimination circuit includes a first selector and a first reference clock detection module, the first input end of the first selector is used to receive the second clock signal, the second input end of the first selector is used to receive the first clock signal, the input end of the first reference clock detection module is used to receive the reference clock signal, the first reference clock detection module is used to output a first control signal based on the reference clock signal, and the selection control end of the first selector is used to receive the first control signal.

[0008] In one or more embodiments of the present invention, the second phase-locked loop includes: a frequency discriminator and a digital loop filter, wherein the frequency discriminator is used to count the first clock signal based on the frequency of the second clock signal to obtain a count value and output an adjustment value based on the count value and a target value, and the digital loop filter is used to filter the adjustment value and output an adjustment signal.

[0009] The present invention also discloses a jitter elimination circuit, comprising: a first phase-locked loop and a second phase-locked loop;

[0010] The first phase-locked loop is used to generate a first clock signal based on a reference clock signal or a second clock signal, and the second phase-locked loop is used to generate an adjustment signal for adjusting a frequency division ratio of the first phase-locked loop based on an error between the second clock signal and the first clock signal.

[0011] In one or more embodiments of the present invention, the jitter elimination circuit includes a second selector and a second reference clock detection module, the first input end of the second selector is used to receive a reference clock signal, the second input end of the second selector is used to receive a second clock signal, the output end of the second selector is connected to the input end of the first phase-locked loop, the input end of the second reference clock detection module is used to receive the reference clock signal, the second reference clock detection module is used to output a second control signal based on the reference clock signal, and the selection control end of the second selector is used to receive the second control signal.

[0012] In one or more embodiments of the present invention, the second phase-locked loop includes: a frequency discriminator and a digital loop filter, wherein the frequency discriminator is used to count the first clock signal based on the frequency of the second clock signal to obtain a count value and output an adjustment value based on the count value and a target value, and the digital loop filter is used to filter the adjustment value and output an adjustment signal.

[0013] The present invention also discloses a communication unit, comprising: the jitter elimination circuit and a clock data recovery circuit, wherein the clock data recovery circuit is used to perform clock recovery on data to generate a second clock signal.

[0014] In one or more embodiments of the present invention, the communication unit also includes a third phase-locked loop, a trigger and a memory, the third phase-locked loop outputs a third clock signal based on a reference clock generated by an oscillator, the clock data recovery circuit performs clock recovery on data based on the third clock signal to generate a second clock signal, the input end of the trigger is used to receive data, the trigger processes data based on the second clock signal, the input end of the memory is connected to the output end of the trigger, and the memory stores and transmits the signal output by the trigger based on the signal output by the first selector.

[0015] In one or more embodiments of the present invention, the communication unit also includes a digital data processing unit and a timestamp frequency calibration module, the digital data processing unit is connected in series between the output end of the trigger and the input end of the memory, the digital data processing unit is used to process the data and extract the timestamp in the data, and the timestamp frequency calibration module is used to perform frequency calibration on the timestamp and output a calibration signal for calibrating the division ratio of the third phase-locked loop.

[0016] The present invention also discloses a communication unit, characterized in that it comprises: the jitter elimination circuit described above, and the communication unit further comprises a decoding module, wherein the decoding module is used to decode data to generate a second clock signal.

[0017] In one or more embodiments of the present invention, the communication unit further includes a trigger, and the trigger performs data transmission based on the first clock signal.

[0018] The present invention also discloses a communication system, characterized in that it comprises: a plurality of connected communication units, wherein at least one communication unit is the communication unit for performing jitter elimination on a second clock signal output by a communication unit of an upper node.

[0019] The present invention also discloses a chip, comprising the jitter elimination circuit, or the communication unit, or the communication system, wherein the chip has a GPIO port connected to a crystal oscillator or a crystal generating a reference clock signal for multiplexing.

[0020] Compared with the prior art, the jitter elimination circuit, communication unit and communication system of the present invention can calibrate the clock signal outputted upstream through the jitter elimination circuit to prevent the jitter deterioration of the clock signal outputted upstream from affecting the operation of the downstream circuit; in a multi-node communication system, by setting the jitter elimination circuit in the communication unit, the clock signal of any node can be jitter eliminated, so that the communication of any number of nodes is no longer restricted by clock jitter. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A system block diagram of an existing communication system;

[0023] Figure 2 A schematic diagram of jitter in an existing communication system;

[0024] Figure 3 A system block diagram of single node de-jittering in a communication system in one embodiment of the present invention;

[0025] Figure 4 A system block diagram of multiple node de-jittering in a communication system according to an embodiment of the present invention;

[0026] Figure 5 is a circuit schematic diagram of a communication unit in Embodiment 1 of the present invention;

[0027] Figure 6 1 is a circuit schematic diagram of the first phase-locked loop in Embodiment 1 and Embodiment 2 of the present invention;

[0028] Figure 7 A circuit schematic diagram of the second phase-locked loop in Embodiment 1, Embodiment 2 and Embodiment 3 of the present invention;

[0029] Figure 8 for Figure 7 Counting principle diagram of the second phase-locked loop in FIG.

[0030] Fig. 9 This is a circuit schematic diagram of a communication unit according to Embodiment 2 of the present invention;

[0031] Fig.10 This is a circuit schematic diagram of a communication unit according to Embodiment 3 of the present invention;

[0032] Fig.11 A first structural schematic diagram of a chip according to an embodiment of the present invention;

[0033] Fig.12 FIG. 2 is a second structural diagram of a chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0035] Unless explicitly stated otherwise, throughout the specification and claims, the term “comprise” or variations such as “include” or “comprising”, etc., will be understood to include the stated elements or components but not to exclude other elements or components.

[0036] "Coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits. In addition, in the present invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0037] Example 1

[0038] like Figure 3 As shown, a communication system in one embodiment of the present invention includes: multiple connected communication units, wherein the first communication unit is a master communication unit, and the second and subsequent communication units are slave communication units, the master communication unit receives a clock signal sent by a host, and the slave communication unit recovers the clock signal according to the data output by the upstream communication unit to achieve clock signal synchronization.

[0039] In one embodiment, at least one communication unit performs jitter elimination on a second clock signal obtained based on data output by a communication unit of a previous node, that is, any one or more communication units can be selected from all communication units to perform jitter elimination on a second clock signal output by a communication unit of a previous node.

[0040] like Figure 3As shown in the figure, with the increase of communication units in a multi-node communication system, the clock jitter when it reaches node P can no longer meet the system requirements. Using the crystal oscillator XO as the reference clock of the communication unit of the node greatly improves the jitter performance. At the same time, in order to achieve clock synchronization, the clock signal obtained from the communication unit of the previous node is used to calibrate the frequency of the clock signal of the communication unit of node P, which not only meets the low jitter requirement, but also achieves the purpose of synchronization. Figure 4 As shown, the above method is beneficial. When the jitter performance cannot meet the system requirements after every few levels of nodes, a communication unit that has undergone the above processing can be set, thereby solving the problem of poor jitter performance of multi-node cascade.

[0041] like Figure 5 As shown, the communication unit capable of eliminating the jitter of the clock signal includes: a jitter elimination circuit 10, a third phase-locked loop 20, a clock data recovery circuit CDR, a trigger DFF and a memory FIFO. The jitter elimination circuit 10 includes: a first phase-locked loop APLL, a second phase-locked loop DPLL, a first selector MUX1 and a first reference clock detection module XD1.

[0042] The first phase-locked loop APLL is used to generate a first clock signal CLK1 based on a reference clock signal RECLK, and the second phase-locked loop DPLL is used to generate an adjustment signal for adjusting a frequency division ratio of the first phase-locked loop APLL based on an error between a second clock signal CLK2 and the first clock signal CLK1.

[0043] The clock data recovery circuit CDR is used to perform clock recovery on the data data of the communication unit of the previous node to generate a second clock signal CLK2. The input end of the first reference clock detection module XD1 is used to receive the reference clock signal RECLK. The reference clock signal RECLK is generated by the local crystal oscillator XO. The first reference clock detection module XD1 is used to output a first control signal based on the reference clock signal RECLK. The first reference clock detection module XD1 is used to detect whether there is a reference clock signal RECLK generated by the crystal oscillator XO. When the first reference clock detection module XD1 does not detect the reference clock signal RECLK, it outputs a first control signal of a first state (for example, a logic low level 0). When the first reference clock detection module XD1 detects the reference clock signal RECLK, it outputs a first control signal of a second state (for example, a logic high level 1). In one embodiment, if the reference clock signal RECLK is always at a DC level for a period of time, it is considered that the first reference clock detection module XD1 will not detect the reference clock signal RECLK; ​​if the reference clock signal RECLK is a clock waveform for a period of time, it is considered that the first reference clock detection module XD1 will detect the reference clock signal RECLK.

[0044] The first input end of the first selector MUX1 is used to receive the second clock signal CLK2, the second input end of the first selector MUX1 is used to receive the first clock signal CLK1, and the selection control end of the first selector MUX1 is used to receive the first control signal and select the first clock signal CLK1 or the second clock signal CLK2 as the output of the first selector MUX1 based on the first control signal. For example, when the first control signal is in the first state (for example, a logic low level 0), the first selector MUX1 outputs the second clock signal CLK2; when the first control signal is in the second state (for example, a logic high level 1), the first selector MUX1 outputs the first clock signal CLK1.

[0045] In one embodiment, the third phase-locked loop 20 outputs a third clock signal CLK3 based on a reference clock generated by an on-chip oscillator On-Chip OSC, and the clock data recovery circuit CDR performs clock recovery on the data data based on the third clock signal CLK3 to generate the second clock signal CLK2.

[0046] like Figure 5 As shown, the input end of the trigger DFF is used to receive data data, the trigger DFF processes the data data based on the second clock signal CLK2, the input end of the memory FIFO is connected to the output end of the trigger DFF, and the memory FIFO stores and transmits the signal output by the trigger DFF based on the signal output by the first selector MUX1.

[0047] Figure 6 An exemplary circuit implementation structure of the first phase-locked loop APLL is given, including a phase frequency detector PFD, a charge pump CP, a loop filter LPF, a voltage-controlled oscillator VCO and a frequency divider DIV, and the frequency divider DIV can be a fractional frequency divider. The phase frequency detector PFD, the charge pump CP, the loop filter LPF and the voltage-controlled oscillator VCO are connected in sequence, and the frequency divider DIV constitutes a frequency calibration loop to calibrate the clock signal output by the voltage-controlled oscillator VCO based on its own frequency division ratio and transmit it to the input end of the phase frequency detector PFD. In other embodiments, the first phase-locked loop APLL can be other circuit structure schematics. In one embodiment, the third phase-locked loop 20 can have the same structure as the first phase-locked loop APLL or a different structure.

[0048] The reference clock source of the phase frequency detector PFD of the third phase-locked loop 20 is the local oscillator On-Chip OSC, and the reference clock source of the first phase-locked loop APLL is the crystal oscillator XO; the voltage-controlled oscillator VCO of the third phase-locked loop 20 outputs the third clock signal CLK3, and the voltage-controlled oscillator VCO of the first phase-locked loop APLL outputs the first clock signal CLK1. The crystal oscillator XO serves as the reference clock source of the first phase-locked loop APLL, so that the jitter performance of the first clock signal CLK1 output by the first phase-locked loop APLL is relatively good, and the second clock signal CLK2 that needs to be de-jittered serves as the input of the second phase-locked loop DPLL, and the output of the second phase-locked loop DPLL is used to correct the division ratio of the frequency divider DIV of the first phase-locked loop APLL to correct the frequency of the first clock signal CLK1. In one embodiment, the loop bandwidth of the second phase-locked loop DPLL is designed to be much smaller than the loop bandwidth of the first phase-locked loop APLL.

[0049] like Figure 7 and Figure 6 As shown, the second phase-locked loop DPLL includes a discriminator FD and a digital loop filter DLF. The discriminator FD is used to count the first clock signal CLK1 based on the frequency of the second clock signal CLK2 to obtain a count value and output an adjustment value based on the difference between the count value and the target value. The digital loop filter DLF is used to filter the adjustment value and output an adjustment signal, and the division ratio of the divider DIV of the first phase-locked loop APLL is adjusted by the adjustment signal.

[0050] In one embodiment, a counter is used as the frequency discriminator FD, the output of the frequency discriminator FD is given to the digital loop filter DLF, and the output of the digital loop filter DLF is given to the fractional divider of the first phase-locked loop APLL to adjust the frequency of the first clock signal CLK1 output by the first phase-locked loop APLL. Figure 8 As shown, the frequency of the second clock signal CLK2 obtained from the communication unit of the upstream node can represent the clock frequency of the communication unit of the upstream node, and the frequency of the first clock signal CLK1 represents the frequency of the communication unit of the current node. In other embodiments, the second phase-locked loop DPLL can also be other structures, such as a phase-locked loop with a frequency divider, the frequency divider is connected to the frequency detector FD and the digital loop filter DLF; the frequency detector FD can be replaced by a frequency phase detector.

[0051] Assuming that the target frequency output by the first phase-locked loop APLL is N times the frequency of the second clock signal CLK2, by counting the first clock signal CLK1 output by the first phase-locked loop APLL within a cycle of the second clock signal CLK2, when the output frequency of the first phase-locked loop APLL is the same as the target frequency, the count value of the clock output by the first phase-locked loop APLL within a cycle of the second clock signal CLK2 is N, and N is the target value. If the count value of the first clock signal CLK1 output by the first phase-locked loop APLL within a cycle of the second clock signal CLK2 is greater than N, it means that the frequency of the first clock signal CLK1 is too high. If the count value is less than N, it means that the frequency of the first clock signal CLK1 is too low. Based on this, an adjustment value can be obtained to adjust the output frequency of the first phase-locked loop APLL. When the loop of the second phase-locked loop DPLL is locked, the output clock frequency of the first phase-locked loop APLL is the same as the target frequency. After the loop of the second phase-locked loop DPLL is locked, the second phase-locked loop DPLL can be turned off to save power consumption, while the output signal of the digital loop filter DLF is maintained; or after turning off the second phase-locked loop DPLL, the second phase-locked loop DPLL can be turned on after a preset time to perform intermittent frequency calibration. The noise introduced by the above-mentioned frequency discriminator FD can be improved by reducing the loop bandwidth of the second phase-locked loop DPLL.

[0052] In one embodiment, the communication unit of the downstream node uses the clock data recovery circuit CDR to recover the second clock signal CLK2 from the data data of the communication unit of the upstream node. The clock required by the clock data recovery circuit CDR is provided by the third phase-locked loop 20, and the reference clock source of the third phase-locked loop 20 is a local oscillator On-Chip OSC. There is a first reference clock detection module XD1 inside the chip, and the first reference clock detection module XD1 is used to detect whether there is a reference clock signal RECLK generated by the crystal oscillator XO. When the first reference clock detection module XD1 does not detect the reference clock signal RECLK, the second clock signal CLK2 recovered by the clock data recovery circuit CDR is used to send data data to the communication unit of the downstream node. This is the behavior state of a normal node. When the first reference clock detection module XD1 detects the reference clock signal RECLK, the first clock signal CLK1 after de-jittering is used to send data data to the communication unit of the downstream node. This is the behavior state of a de-jittering node.

[0053] In a multi-node communication system, each communication unit can be of the above structure, and whether debouncing can be performed depends on whether the first reference clock detection module XD1 detects the reference clock signal RECLK, that is, whether the crystal oscillator XO is working. Of course, according to the actual application scenario, the communication unit of one or more nodes (for example, a certain number of ordinary nodes per interval) can be set to the above structure in a targeted manner, and debouncing is performed when the crystal oscillator XO is working, and no debouncing is required when it is not working.

[0054] Example 2

[0055] In Embodiment 1, since there may be a large frequency offset between the reference clock generated by the on-chip oscillator On-Chip OSC and the second clock signal CLK2 obtained based on the data output by the upstream node communication unit, based on Embodiment 1, as Fig. 9 As shown, a digital data processing unit DDP and a time stamp frequency calibration module TSFC are also provided in the communication unit. Specifically, the digital data processing unit DDP is connected between the output end of the trigger DFF and the input end of the memory FIFO, the digital data processing unit DDP is used to extract the time stamp in the data data, and the digital data processing unit DDP also extracts the local time stamp in the reference clock generated by the oscillator On-Chip OSC, the time stamp frequency calibration module TSBFC is connected to the digital data processing unit DDP to obtain the time stamp in the data data from the upstream node communication unit and the local time stamp of the reference clock generated by the oscillator On-Chip OSC, the time stamp frequency calibration module TSBFC compares the time stamp in the data data with the local time stamp, and outputs a calibration signal for adjusting the frequency division ratio of the frequency divider DIV of the third phase-locked loop 20 according to the difference between the two so that the frequency of the third clock signal CLK3 output by the third phase-locked loop 20 is the same as the clock frequency used by the upstream node to transmit data (in one embodiment, the clock frequency used by the upstream node to transmit data is the same as the frequency of the second clock signal CLK2).

[0056] Based on the above scheme, the time stamp (time stamp) embedded in the data data of the communication unit of the upstream node can be compared with the local time stamp through the time stamp frequency calibration module TSBFC, and then the divider DIV in the third phase-locked loop 20 can be adjusted to reduce the deviation between the frequency of the third clock signal CLK3 output by the third phase-locked loop 20 and the clock frequency used by the upstream node to transmit data.

[0057] Example 3

[0058] like Figure 3As shown, a communication system in one embodiment of the present invention includes: multiple connected communication units, wherein the first communication unit is a master communication unit, and the second and subsequent communication units are slave communication units, the master communication unit receives a clock signal sent by a host, and the slave communication unit recovers the clock signal according to the data output by the upstream communication unit to achieve clock signal synchronization.

[0059] In one embodiment, at least one communication unit performs jitter elimination on the second clock signal CLK2 output by the communication unit of the previous node, that is, any one or more communication units can be selected from all the communication units to perform jitter elimination on the second clock signal CLK2 output by the communication unit of the previous node.

[0060] like Figure 3 As shown in the figure, with the increase of communication units in a multi-node communication system, the clock jitter when it reaches node P can no longer meet the system requirements. Using the crystal oscillator XO as the reference clock of the communication unit of the node greatly improves the jitter performance. At the same time, in order to achieve clock synchronization, the clock signal obtained from the communication unit of the previous node is used to calibrate the frequency of the clock signal of the communication unit of node P, which not only meets the low jitter requirement, but also achieves the purpose of synchronization. Figure 4 As shown, the above method is beneficial. When the jitter performance cannot meet the system requirements after every few levels of nodes, a communication unit that has undergone the above processing can be set, thereby solving the problem of poor jitter performance of multi-node cascade.

[0061] like Fig.10 As shown, the communication unit capable of eliminating the jitter of the clock signal includes: a jitter elimination circuit, a decoding module Pattern Detection and a trigger DFF.

[0062] The jitter elimination circuit includes: a second selector MUX2, a second reference clock detection module XD2, a first phase-locked loop APLL and a second phase-locked loop DPLL.

[0063] The first input terminal of the second selector MUX2 is used to receive the reference clock signal RECLK, the second input terminal of the second selector MUX2 is used to receive the second clock signal CLK2, and the output terminal of the second selector MUX2 is connected to the input terminal of the first phase-locked loop APLL. In one embodiment, the reference clock signal RECLK is generated by a crystal oscillator XO.

[0064] The input end of the second reference clock detection module XD2 is used to receive the reference clock signal RECLK. The second reference clock detection module XD2 is used to output a second control signal based on the reference clock signal RECLK. The selection control end of the second selector MUX2 is used to receive the second control signal.

[0065] The first phase-locked loop APLL is used to generate a first clock signal CLK1 based on a reference clock signal RECLK or a second clock signal CLK2, and the second phase-locked loop DPLL is used to generate an adjustment signal for adjusting the frequency division ratio of the first phase-locked loop APLL based on an error between the second clock signal CLK2 and the first clock signal CLK1. The trigger DFF transmits data data based on the first clock signal CLK1.

[0066] In one embodiment, the communication unit of the downstream node decodes the data data of the communication unit of the upstream node through the decoding module Pattern Detection to generate a second clock signal CLK2, and the obtained second clock signal CLK2 is used as the clock reference of the communication unit of the current node. For ordinary nodes, the second clock signal CLK2 is used as the input clock of the first phase-locked loop APLL. For the node P that needs to eliminate jitter, the reference clock signal RECLK generated by the crystal oscillator XO is used as the input clock of the first phase-locked loop APLL, so that the output clock of the first phase-locked loop APLL has very good jitter performance.

[0067] The second reference clock detection module XD2 is used to detect whether the reference clock signal RECLK exists. When the second reference clock detection module XD2 does not detect the reference clock signal RECLK, the second clock signal CLK2 is used as the input clock of the first phase-locked loop APLL. In one embodiment, this is the state of most nodes in a multi-node system; when the second reference clock detection module XD2 detects the reference clock signal RECLK, the reference clock signal RECLK is used as the input clock of the first phase-locked loop APLL.

[0068] As can be seen from the above, in a multi-node communication system, each communication unit can be of the above structure, and whether debouncing can be performed depends on whether the second reference clock detection module XD2 detects the reference clock signal RECLK, that is, whether the crystal oscillator XO is working. Of course, according to the actual application scenario, the communication units of a certain or multiple nodes at intervals can be set to the above structure in a targeted manner, and debouncing is performed when the crystal oscillator XO is working, and no debouncing is required when it is not working.

[0069] The first phase-locked loop APLL is a fractional phase-locked loop, specifically including a phase frequency detector PFD, a charge pump CP, a loop filter LPF, a voltage-controlled oscillator VCO and a frequency divider DIV, wherein the frequency divider DIV is a fractional frequency divider. The phase frequency detector PFD, the charge pump CP, the loop filter LPF and the voltage-controlled oscillator VCO are connected in sequence, and the frequency divider DIV forms a frequency calibration loop to calibrate the first clock signal CLK1 output by the voltage-controlled oscillator VCO based on its own frequency division ratio and transmit it to the input end of the phase frequency detector PFD.

[0070] For the node P that needs to eliminate jitter, since the first clock signal CLK1 output by the first phase-locked loop APLL is locked on the reference clock signal RECLK generated by the local crystal oscillator XO, it cannot be synchronized with the second clock signal CLK2 of the communication unit of the upstream node. In order to solve this problem, the second phase-locked loop DPLL is used as the frequency calibration loop of the first phase-locked loop APLL. The second phase-locked loop DPLL generates an adjustment signal according to the error between the frequency of the first clock signal CLK1 output by the first phase-locked loop APLL and the target frequency, and gives it to the divider DIV of the first phase-locked loop APLL. When the first phase-locked loop APLL and the second phase-locked loop DPLL are both locked, the frequency of the first clock signal CLK1 output by the first phase-locked loop APLL will stabilize at the target frequency.

[0071] Usually, the loop bandwidth of the second phase-locked loop DPLL is designed to be much smaller than the loop bandwidth of the first phase-locked loop APLL, so as to ensure the stability of the output of the first phase-locked loop APLL and achieve good jitter performance of the output clock of the first phase-locked loop APLL.

[0072] like Figure 7 As shown, the second phase-locked loop DPLL includes a frequency discriminator FD and a digital loop filter DLF. The frequency discriminator FD is used to count the first clock signal CLK1 based on the frequency of the second clock signal CLK2 to obtain a count value and output an adjustment value based on the count value and the target value. The digital loop filter DLF is used to filter the adjustment value and output an adjustment signal. In other embodiments, the second phase-locked loop DPLL can also have other structures.

[0073] In one embodiment, a counter is used as the frequency discriminator FD, the output of the frequency discriminator FD is given to the digital loop filter DLF, and the output of the digital loop filter DLF is given to the fractional divider of the first phase-locked loop APLL to adjust the frequency of the first clock signal CLK1 output by the first phase-locked loop APLL. Figure 8 As shown, the frequency of the second clock signal CLK2 obtained from the communication unit of the upstream node can represent the clock frequency of the communication unit of the upstream node, and the frequency of the first clock signal CLK1 represents the frequency of the communication unit of the current node.

[0074] Assuming that the target frequency output by the first phase-locked loop APLL is N times the frequency of the second clock signal CLK2, by counting the first clock signal CLK1 output by the first phase-locked loop APLL within a cycle of the second clock signal CLK2, when the output frequency of the first phase-locked loop APLL is the same as the target frequency, the count value of the clock output by the first phase-locked loop APLL within a cycle of the second clock signal CLK2 is N, and N is the target value. If the count value of the first clock signal CLK1 output by the first phase-locked loop APLL within a cycle of the second clock signal CLK2 is greater than N, it means that the frequency of the first clock signal CLK1 is too high. If the count value is less than N, it means that the frequency of the first clock signal CLK1 is too low. Based on this, an adjustment value can be obtained to adjust the output frequency of the first phase-locked loop APLL. When the loop of the second phase-locked loop DPLL is locked, the output clock frequency of the first phase-locked loop APLL is the same as the target frequency. The noise introduced by the above-mentioned frequency detector FD can be improved by reducing the loop bandwidth of the second phase-locked loop DPLL.

[0075] like Fig.11 and Fig.12 As shown, the present invention also discloses a chip, which includes the communication unit or communication system including the jitter elimination circuit in the above embodiment. The chip has a GPIO1 port and a GPIO2 port. In one embodiment, the GPIO1 port can be connected to a crystal oscillator XO, and the crystal oscillator XO generates a reference clock signal; in another embodiment, the GPIO1 port and the GPIO2 port of the chip can be connected to a crystal Crystal, and the crystal Crystal is connected to the oscillator circuit in the chip to generate a reference clock signal. In one embodiment, the crystal oscillator XO or the crystal Crystal can be located outside the chip.

[0076] In one embodiment, GPIO1 and GPIO2 can be used to define I 2 C address, the power-on reset signal will latch the address signal into the address latch in the chip. After the address is latched, the GPIO1 port and GPIO2 port can be used to connect the crystal oscillator XO or the crystal Crystal. The reference clock detection module in the chip detects whether there is a reference clock signal. In one embodiment, it detects whether the chip is connected to the crystal oscillator XO or the crystal Crystal to distinguish between ordinary nodes and debouncing nodes.

[0077] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive, and the scope of the present invention is limited by the appended claims rather than the above description. According to the above teachings, many changes and variations can be made, and the present invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials and parts, so it is intended to include all changes that fall within the meaning and scope of the equivalent elements of the claims in the present invention, so that those skilled in the art can implement and utilize various different exemplary embodiments of the present invention and various different options and changes without departing from the scope and spirit of the present invention. Any figure mark in the claims should not be regarded as limiting the claims involved.

[0078] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A jitter elimination circuit, characterized in that: include: a first phase-locked loop and a second phase-locked loop; The first phase-locked loop is used to generate a first clock signal based on a reference clock signal, and the second phase-locked loop is used to generate an adjustment signal for adjusting a frequency division ratio of the first phase-locked loop based on an error between the second clock signal and the first clock signal.

2. The jitter elimination circuit according to claim 1, characterized in that: The jitter elimination circuit includes a first selector and a first reference clock detection module, wherein the first input end of the first selector is used to receive the second clock signal, the second input end of the first selector is used to receive the first clock signal, the input end of the first reference clock detection module is used to receive the reference clock signal, the first reference clock detection module is used to output a first control signal based on the reference clock signal, the selection control end of the first selector is used to receive the first control signal, and the first selector selects the first clock signal or the second clock signal to output based on the first control signal.

3. The jitter elimination circuit according to claim 2, characterized in that: When the first reference clock detection module does not detect the reference clock signal, the first control signal is in a first state, and the first selector selects the second clock signal to output according to the first control signal in the first state; when the first reference clock detection module detects the reference clock signal, the first control signal is in a second state, and the first selector selects the first clock signal to output according to the first control signal in the second state.

4. The jitter elimination circuit according to claim 1, characterized in that: The jitter elimination circuit is located in the current node communication unit, the current node communication unit is connected to the previous node communication unit, the jitter elimination circuit obtains the second clock signal based on the data output by the previous node communication unit, and the current node communication unit is connected to the local crystal oscillator or local crystal, and the jitter elimination circuit obtains the reference clock signal based on the local crystal oscillator or local crystal.

5. The jitter elimination circuit according to claim 1, characterized in that: The second phase-locked loop includes: a frequency discriminator and a digital loop filter, wherein the frequency discriminator is used to count the first clock signal based on the frequency of the second clock signal to obtain a count value and output an adjustment value based on the difference between the count value and the target value, and the digital loop filter is used to filter the adjustment value and output an adjustment signal.

6. A jitter elimination circuit, characterized in that: include: a first phase-locked loop and a second phase-locked loop; The first phase-locked loop is used to generate a first clock signal based on a reference clock signal or a second clock signal, and the second phase-locked loop is used to generate an adjustment signal for adjusting a frequency division ratio of the first phase-locked loop based on an error between the second clock signal and the first clock signal.

7. The jitter elimination circuit according to claim 6, characterized in that: The jitter elimination circuit includes a second selector and a second reference clock detection module, the first input end of the second selector is used to receive a reference clock signal, the second input end of the second selector is used to receive a second clock signal, the output end of the second selector is connected to the input end of the first phase-locked loop, the input end of the second reference clock detection module is used to receive the reference clock signal, the second reference clock detection module is used to output a second control signal based on the reference clock signal, the selection control end of the second selector is used to receive a second control signal, and the second selector selects the reference clock signal or the second clock signal for output based on the second control signal.

8. The jitter elimination circuit according to claim 6, characterized in that: The second phase-locked loop includes: a frequency discriminator and a digital loop filter, wherein the frequency discriminator is used to count the first clock signal based on the frequency of the second clock signal to obtain a count value and output an adjustment value based on the difference between the count value and the target value, and the digital loop filter is used to filter the adjustment value and output an adjustment signal.

9. A communication unit, characterized in that: include: According to the jitter elimination circuit and clock data recovery circuit as described in any one of claims 1 to 5, the communication unit is connected to the communication unit of the previous node to receive data from the communication unit of the previous node, and the clock data recovery circuit is used to perform clock recovery on the data to generate a second clock signal.

10. The communication unit according to claim 9, characterized in that The communication unit also includes a third phase-locked loop, a trigger and a memory. The third phase-locked loop outputs a third clock signal based on a reference clock generated by an oscillator. The clock data recovery circuit performs clock recovery on data based on the third clock signal to generate a second clock signal. The input end of the trigger is used to receive data. The trigger processes data based on the second clock signal. The input end of the memory is connected to the output end of the trigger. The memory stores and transmits the signal output by the trigger based on the signal output by the first selector.

11. The communication unit according to claim 10, characterized in that The communication unit also includes a digital data processing unit and a timestamp frequency calibration module. The digital data processing unit is connected between the output end of the trigger and the input end of the memory. The digital data processing unit is used to extract the timestamp in the data and the local timestamp in the reference clock generated by the oscillator. The timestamp frequency calibration module compares the timestamp in the data with the local timestamp, and outputs a calibration signal for calibrating the frequency division ratio of the third phase-locked loop based on the difference between the timestamp in the data and the local timestamp.

12. A communication unit, characterized in that: include: According to the jitter elimination circuit as claimed in claim 9, 10 or 11, the communication unit further comprises a decoding module, the communication unit is connected to the previous node communication unit to receive data from the previous node communication unit, and the decoding module is used to decode the data to generate a second clock signal.

13. The communication unit according to claim 12, characterized in that The communication unit further includes a flip-flop that performs data transmission based on a first clock signal.

14. A communication system, characterized in that: include: A plurality of connected communication units, wherein at least one communication unit is a communication unit as claimed in any one of claims 9 to 13, for performing jitter elimination on a second clock signal output by a communication unit of an upper node.

15. A chip, characterized in that: The chip comprises the jitter elimination circuit as described in any one of claims 1 to 8, or comprises the communication unit as described in any one of claims 9 to 13, or comprises the communication system as described in claim 14, wherein the chip has a GPIO port connected to a crystal oscillator or a crystal that generates a reference clock signal.

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