Level conversion circuit

Abstract

The invention discloses a level conversion circuit, which comprises a first latch module used for obtaining a first logic signal and a second logic signal with a level range from a second power supply voltage to a first reference ground according to an input signal with a level range from the first power supply voltage to the first reference ground, and the first logic signal and the second logic signal are complementary signals; the second latch module is used for obtaining a third logic signal of which the level range is from the second power supply voltage to the second reference ground according to the first logic signal and the second logic signal; the output shaping module is used for obtaining an output signal according to the third logic signal, and the level range of the output signal is from the second power supply voltage to the second reference ground; and the enabling control module is used for pulling down one of the first logic signal and the second logic signal to the first reference ground under the condition that the first power supply voltage is smaller than the set reference voltage, so that the level conversion circuit is prevented from outputting an unstable signal, and the reliability of the circuit is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more specifically, to a level conversion circuit. Background Art

[0002] In a complex power system-on-chip, modules with different functions such as analog circuits, digital circuits, and passive components are integrated into a single chip. Different functional modules have different performance and constraints, and need to run at different voltages to achieve the best performance-to-power ratio. Multi-voltage technology is often used to achieve a compromise between low power consumption and high performance. The multi-voltage design method reduces power consumption while ensuring performance. However, the different logic signal levels between different voltage domains will cause problems with timing accuracy and driving capability. Therefore, a level shift circuit is needed to convert control signals between different power supply voltage domains.

[0003] Voltage domain conversion can be divided into two structures: low to high and high to low. The conversion from high level to low level can be realized by simple buffer drive. However, when the voltage domain is converted from low level to high level, because the low level signal drives the high level signal, the rise and fall time will be longer, and the time near the threshold will be increased, so a level conversion circuit is needed to realize the conversion of different voltage domains.

[0004] Figure 1 A schematic circuit diagram of a conventional level conversion circuit is shown, Figure 1 As shown, the conventional level conversion circuit 100 includes PMOS transistors MP1 to MP4, NMOS transistors MN1 to MN4, and inverters INV1 to INV3. Among them, NMOS transistors MN1 and MN2 are used to convert the high level of the input signal Vin located in the low voltage domain (VDD~GNDA) from the power supply voltage VDD to the power supply voltage VCC, the upper PMOS transistors MP1 and MP2 are cross-coupled to latch the signal, and finally obtain the logic signals AL and AR, the logic signals AL and AR are low-level converted through the upper PMOS transistors MP3 and MP4, and then the low level of the logic signals AL and AR is converted from the reference ground GNDA to the reference ground GNDB, the lower NMOS transistors MN3 and MN4 are cross-coupled to latch the signal, and obtain the logic signal AQ, the inverters INV2 and INV3 perform shaping and filtering on the logic signal AQ, and finally obtain the output signal Vout located in the high voltage domain (VCC~GNDB).

[0005] In actual applications, the traditional level conversion circuit 100 may have a problem that the power-on time of the low-voltage domain is different from the power-on time of the high-voltage domain. When the power-on time of the low-voltage domain is slower than the power-on time of the high-voltage domain, it will cause the voltages of nodes AL and AR to float in an unstable state, which will in turn cause the output logic of the level conversion circuit to be uncertain, and even produce erroneous output in severe cases. Summary of the invention

[0006] In view of the above problems, the purpose of the present invention is to provide a level conversion circuit, which improves the problem that when the power supply voltage in the low voltage domain has not been successfully powered on, the internal nodes of the circuit are in an uncertain state, which then leads to output errors.

[0007] According to one aspect of the present invention, there is provided a level conversion circuit, comprising: a first latch module, for obtaining a first logic signal and a second logic signal with a level range from a second power supply voltage to the first reference ground according to an input signal with a level range from a first power supply voltage to a first reference ground, wherein the first logic signal and the second logic signal are complementary signals; a second latch module, for obtaining a third logic signal with a level range from the second power supply voltage to the second reference ground according to the first logic signal and the second logic signal; an output shaping module, for obtaining an output signal according to the third logic signal, wherein the level range of the output signal is from the second power supply voltage to the second reference ground; and an enable control module, for pulling down one of the first logic signal and the second logic signal to the first reference ground when the first power supply voltage is less than a set reference voltage.

[0008] Optionally, the first latch module includes: a first pull-up unit and a first pull-down unit connected between a first voltage terminal and a second voltage terminal, a first reference node for providing the first logic signal and a second reference node for providing the second logic signal are provided between the first pull-up unit and the first pull-down unit, and the first pull-down unit is used to pull down the potential of one of the first reference node and the second reference node according to the input signal, wherein the first voltage terminal is used to be connected to the second power supply voltage, and the second voltage terminal is used to be connected to the first reference ground via the enable control module, and the enable control module is also used to disconnect the discharge path between the second voltage terminal and the first reference ground when the first power supply voltage is less than the reference voltage.

[0009] Optionally, the enable control module includes: a discharge path control unit connected between the second voltage terminal and the first reference ground, the discharge path control unit being used to disconnect the discharge path of the second voltage terminal to the first reference ground according to a valid enable control signal; and a reference node pull-down unit connected to one of the first reference node and the second reference node, the reference node pull-down unit being used to pull down one of the first reference node and the second reference node according to the valid enable control signal, wherein the enable control signal is effective when the first power supply voltage is less than the reference voltage, and is invalid when the first power supply voltage is greater than / equal to the reference voltage.

[0010] Optionally, the discharge path control unit includes: a first transistor with a first conductivity type, a first end of the first transistor is connected to the second voltage end, a control end of the first transistor is connected to the enable control signal, and a second end of the first transistor is connected to the first reference ground.

[0011] Optionally, the reference node pull-down unit includes: a resistor, a first end of the resistor is connected to the second power supply voltage; a second transistor with a first conductivity type, a first end of the second transistor is connected to the second end of the resistor, a control end of the second transistor is connected to the enable control signal, and a second end of the second transistor is connected to the first reference ground; and a third transistor with a first conductivity type, a first end of the third transistor is connected to one of the first reference node and the second reference node, a control end of the third transistor is connected to the first end of the second transistor, and a second end of the third transistor is connected to the first reference ground.

[0012] Optionally, the reference node pull-down unit also includes: a fourth transistor having a second conductivity type, the second conductivity type is different from the first conductivity type, the first end of the fourth transistor is connected to the second end of the resistor, the control end of the fourth transistor is connected to the enable control signal, and the second end of the fourth transistor is connected to the first end of the third transistor.

[0013] Optionally, the first pull-up unit includes: a fifth transistor and a sixth transistor of the second conductivity type, the first ends of the fifth transistor and the sixth transistor are connected to the first voltage end, the control end of the fifth transistor and the second end of the sixth transistor are connected to the second reference node, the second end of the fifth transistor and the control end of the sixth transistor are connected to the first reference node, and the first pull-down unit includes: a seventh transistor and an eighth transistor of the first conductivity type, the first end of the seventh transistor is connected to the first reference node, the first end of the eighth transistor is connected to the second reference node, the control end of the seventh transistor is used to receive the input signal, the control end of the eighth transistor is used to receive the inverted signal of the input signal, and the second ends of the seventh transistor and the eighth transistor are connected to the second voltage end.

[0014] Optionally, the second latch module includes: a second pull-up unit and a second pull-down unit connected between the first voltage terminal and the third voltage terminal, a third reference node for providing the third logic signal is provided between the second pull-up unit and the second pull-down unit, an input of the second pull-up unit is connected to the first reference node and the second reference node, wherein the first voltage terminal is used to connect to the second power supply voltage, and the third voltage terminal is used to connect to the second reference ground, wherein the second pull-up unit includes: a ninth transistor and a tenth transistor having a second conductivity type, a first terminal of the ninth transistor and the tenth transistor is connected to the first voltage terminal, and a control terminal of the ninth transistor is connected to the first voltage terminal. The first reference node is connected, the second end of the ninth transistor is connected to the third reference node and the second pull-down unit, the control end of the tenth transistor is connected to the second reference node, and the second end of the tenth transistor is connected to the second pull-down unit, wherein the second pull-down unit includes: an eleventh transistor and a twelfth transistor having a first conductivity type, the first end of the eleventh transistor and the control end of the twelfth transistor are connected to the third reference node and the second end of the ninth transistor, the first end of the twelfth transistor and the control end of the eleventh transistor are connected to the second end of the tenth transistor, and the second ends of the eleventh transistor and the twelfth transistor are connected to the third voltage terminal.

[0015] Optionally, the enable control module further includes: a power-on detection unit, wherein the power-on detection unit is used to compare the first power supply voltage with the reference voltage to generate the enable control signal.

[0016] Optionally, the first conductivity type is N type, and the second conductivity type is P type.

[0017] To summarize, the level conversion circuit in the embodiment of the present invention enables the control module to pull down one of the two logic signals output by the first latch module when the power supply voltage in the low voltage domain has not yet been powered up to a preset value, thereby enabling the output node of the first latch module to be in a certain state before the circuit is powered on, thereby avoiding the level conversion circuit from outputting unstable signals, which is beneficial to improving the reliability of the circuit.

[0018] Furthermore, in many subsequent circuits, there may be strict requirements on the level of the input signal. If the output of the level conversion circuit is in an uncertain state when the power supply voltage in the low voltage domain has not yet been powered on, it may cause erroneous operation or damage to the subsequent circuit. Therefore, the level conversion circuit of this embodiment can protect the subsequent circuit and avoid erroneous operation of the subsequent circuit before power-on.

[0019] Furthermore, the enabling control module of this embodiment can also reduce the static current power consumption of the common source resistance load branch when the level conversion circuit works normally, which can save chip area and reduce the static power consumption of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0021] Figure 1 A schematic circuit diagram of a conventional level conversion circuit is shown.

[0022] Figure 2 FIG. 4 shows a schematic structural diagram of a level conversion circuit according to an embodiment of the present invention.

[0023] Figure 3 FIG. 4 shows a schematic circuit diagram of an enabling control module according to a first embodiment of the present invention.

[0024] Figure 4 FIG. 4 shows a schematic circuit diagram of an enabling control module according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0025] Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings.Where possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0026] In the specification, it should be noted that similar reference numerals that have been used to represent similar parts in other drawings are used for these elements as much as possible. In the following description, when functions and configurations known to those skilled in the art are not related to the basic configuration of the present disclosure, their detailed description will be omitted. The terms described in the specification should be understood as follows.

[0027] The advantages and features of the present disclosure and their implementation methods will be described through the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments described herein. Rather, these embodiments are provided to make the present disclosure comprehensive and complete, so as to fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0028] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings used to describe the embodiments of the present disclosure are merely examples, and the present disclosure is therefore not limited to the illustrated details. Similar reference numerals always represent similar elements. In the following description, when it is determined that a detailed description of a related known function or construction will inevitably obscure the focus of the present disclosure, the detailed description will be omitted.

[0029] In the case where the terms “including,” “having,” and “comprising” described in the present specification are used, another part may be added unless “only to” is used. Unless otherwise specified to the contrary, terms in the singular form may include plural forms.

[0030] It should be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component. For example, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component without departing from the scope of the present disclosure.

[0031] The term "at least one" should be understood to include any and all combinations of one or more of the corresponding listed items. For example, the meaning of "at least one of the first item, the second item, and the third item" means the combination of all items proposed from two or more of the first item, the second item, and the third item, as well as the first item, the second item, or the third item.

[0032] As those skilled in the art can fully understand, the features of the various embodiments of the present disclosure can be partially or completely combined or combined with each other, and can interoperate and technically drive each other in various ways. The embodiments of the present disclosure can be performed independently of each other, or can be performed together in a mutually dependent relationship.

[0033] In all embodiments of the present invention, since the source and drain of a metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present invention, the controlled middle electrode of the MOS transistor is referred to as the control terminal, and the remaining two ends of the MOS transistor are referred to as the first terminal and the second terminal, respectively. For the convenience of unified expression, in the context, the source, drain, and gate of a PMOS transistor are referred to as the first terminal, the second terminal, and the control terminal, respectively, and the drain, source, and gate of an NMOS transistor are referred to as the first terminal, the second terminal, and the control terminal, respectively. In addition, terms such as "first" and "second" are only used to distinguish one component (or a portion of a component) from another component (or another portion of a component).

[0034] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] Figure 2 FIG. 2 shows a schematic structural diagram of a level conversion circuit according to an embodiment of the present invention. Figure 2 As shown, the level stretching circuit 200 includes an input inverter 210 , a first latch module 220 , a second latch module 230 , an output shaping module 240 and an enable control module 250 .

[0036] The input inverter 210 is disposed between the voltage domains VDD and GNDA, and is used to obtain an inverted signal of an input signal Vin having a level range between the power supply voltage VDD and the reference ground GNDA.

[0037] The first latch module 220 is arranged between the voltage domains VCC and GNDA. The first latch module 220 is used to convert the high level of the input signal Vin, and then obtain the first logic signal AL and the second logic signal AR with a level range between the power supply voltage VCC and the reference ground GNDA according to the input signal Vin. The first logic signal AL and the second logic signal AR are complementary signals. For example, the power supply voltage VCC is higher than the power supply voltage VDD.

[0038] The second latch module 230 is arranged between the voltage domains VCC and GNDB. The second latch module 230 is used to convert the low level of the input signal Vin, and then obtain a third logic signal AQ with a level range between the power supply voltage VCC and the reference ground GNDB according to the first logic signal AL and the second logic signal AR.

[0039] The output shaping module 240 is used to perform shaping and filtering on the third logic signal AQ, and then obtain an output signal Vout. Therefore, the level range of the output signal Vout is from the power supply voltage VCC to the reference ground GNDB.

[0040] The enable control module 250 is used to compare the power supply voltage VDD with a set reference voltage Vref, and to enable the first logic signal AL if the power supply voltage VDD is less than the reference voltage Vref.

[0041] One of the first logic signal AL and the second logic signal AR is pulled down to the reference ground GNDA, so that the first logic signal AL and the second logic signal AR can have a certain logic state when the power supply voltage VDD has not been successfully powered on, avoiding the output logic error of the level conversion circuit 200.

[0042] Specifically, the first latch module 220 includes a first pull-up unit composed of a pair of PMOS transistors (P-Metal-Oxide-Semiconductor, P-type metal oxide semiconductor field effect transistor) MP1 and MP2 and a first pull-down unit composed of a pair of NMOS transistors (N-Metal-Oxide-Semiconductor, N-type metal oxide semiconductor field effect transistor). The first pull-up unit and the first pull-down unit are connected between a first voltage terminal 201 and a second voltage terminal 202, wherein the first voltage terminal 201 is used to connect to a power supply voltage VCC, and the second voltage terminal 202 is used to connect to a reference ground GNDA via the enable control module 250. The enable control module 250 is also used to control the on-off of a discharge path between the second voltage terminal 202 and the reference ground GNDA according to a comparison result between the power supply voltage VDD and the reference voltage Vref.

[0043] A reference node A1 for providing the first logic signal AL and a reference node A2 for providing the second logic signal AR are provided between the first pull-up unit and the first pull-down unit. The first pull-down unit is further configured to receive the input signal Vin and pull down the potential of one of the reference nodes A1 and A2 according to the input signal Vin.

[0044] Further, in the first latch module 220, the first terminals of the PMOS transistors MP1 and MP2 are connected to the first voltage terminal 201, the control terminal of the PMOS transistor MP1 and the second terminal of the PMOS transistor MP2 are connected to the reference node A2, and the second terminal of the PMOS transistor MP1 and the control terminal of the PMOS transistor MP2 are connected to the reference node A1. The second terminals of the NMOS transistors MN1 and MN2 are connected to the second voltage terminal 202, the first terminal of the NMOS transistor MN1 is connected to the reference node A1, the first terminal of the NMOS transistor MN2 is connected to the reference node A2, the control terminal of the NMOS transistor MN1 is connected to the input signal Vin, and the control terminal of the NMOS transistor MN2 is connected to the inverted signal of the input signal Vin.

[0045] For example, when the power supply voltage VDD is greater than the reference voltage Vref, the enable control module 250 turns on the discharge path from the second voltage terminal 202 to the reference ground GNDA. When the input signal Vin is at a low level, the NMOS transistor MN1 is turned off, the NMOS transistor MN2 is turned on, the reference node A2 is pulled down to the reference ground GNDA through the NMOS transistor MN2, and the PMOS transistor MP1 is turned on, the reference node A1 is pulled high through the PMOS transistor MP1, so the PMOS transistor MP2 is in the off state, and finally the level of the first logic signal AL is equal to the power supply voltage VCC, and the level of the second logic signal AR is equal to the reference ground GNDA. When the input signal Vin is at a high level, the NMOS transistor MN1 is turned on and the NMOS transistor MN2 is turned off, and the reference node A1 is pulled down to the reference ground GNDA through the NMOS transistor MN1, and the PMOS transistor MP2 is turned on, and the reference node A2 is pulled high through the PMOS transistor MP2, so the PMOS transistor MP1 is turned off, and finally the level of the first logic signal AL is equal to the reference ground GNDA, and the level of the second logic signal AR is equal to the power supply voltage VCC.

[0046] Further, the second latch module 230 includes a second pull-up unit composed of PMOS transistors MP3 and MP4 and a second pull-down unit composed of NMOS transistors MN3 and MN4. The second pull-up unit and the second pull-down unit are connected between the first voltage terminal 201 and the third voltage terminal 203, and the third voltage terminal 203 is used to connect to the reference ground GNDB. There is a reference node A3 for providing a third logic signal AQ between the second pull-up unit and the second pull-down unit, and the input of the second pull-up unit is connected to the reference nodes A1 and A2, and the high and low level states of the reference node A3 are controlled according to the first logic signal AL and the second logic signal AR.

[0047] Specifically, in the second latch module 230, the first terminals of the PMOS transistors MP3 and MP4 are connected to the first voltage terminal 201, the control terminal of the PMOS transistor MP3 is connected to the reference node A1, the control terminal of the PMOS transistor MP4 is connected to the reference node A2, and the second terminal of the PMOS transistor MP3 is connected to the reference node A3. The second terminals of the NMOS transistors MN3 and MN4 are connected to the third voltage terminal 203, the first terminal of the NMOS transistor MN3 and the control terminal of the NMOS transistor MN4 are connected to the reference node A3 and the second terminal of the PMOS transistor MP3, and the first terminal of the NMOS transistor MN4 and the control terminal of the NMOS transistor MN3 are connected to the second terminal of the PMOS transistor MP4.

[0048] When the first logic signal AL is at a high level and the second logic signal AR is at a low level, the PMOS transistor MP3 and the NMOS transistor MN4 are turned off, and the PMOS transistor MP4 and the NMOS transistor MN3 are turned on, so the potential of the reference node A3 is pulled down to the reference ground GNDB, so the level of the third logic signal AQ is equal to the reference ground GNDB; when the first logic signal AL is at a low level and the second logic signal AR is at a high level, the PMOS transistor MP3 and the NMOS transistor MN4 are turned on, and the PMOS transistor MP4 and the NMOS transistor MN3 are turned off, so the potential of the reference node A3 is pulled up to the power supply voltage VCC, so the level of the third logic signal AQ is equal to the reference voltage VCC.

[0049] Furthermore, the output shaping module 240 includes inverters INV1 and INV2, which are arranged between the power supply voltage VCC and the reference ground GNDB, and the input of the inverter INV1 is connected to the reference node A3, the output of the inverter INV1 is connected to the input of the inverter INV2, and the output of the inverter INV2 is used to provide the output signal Vout.

[0050] Further, the enable control module 250 includes a power-on detection unit 251, a discharge path control unit 252, and a reference node pull-down unit 253. The power-on detection unit 251 is used to compare the power supply voltage VDD with the reference voltage Vref, and generate an enable control signal EN according to the comparison result. For example, when the power supply voltage VDD is less than the reference voltage Vref, the enable control signal EN is valid (for example, a low level); when the power supply voltage VDD is greater than the reference voltage Vref, the enable control signal EN is invalid (for example, a high level). In an exemplary embodiment, the power-on detection unit 251 can be implemented by a comparator. Of course, the present invention is not limited to this. The power-on detection unit 251 can also be implemented by any circuit that can realize voltage comparison or voltage detection.

[0051] The discharge path control unit 252 is connected between the second voltage terminal 202 and the reference ground GNDA, and is used for disconnecting the discharge path from the second voltage terminal 202 to the reference ground GNDA according to a valid enable control signal EN.

[0052] The reference node pull-down unit 253 is connected to the reference node A2, and is used to pull the potential of the reference node A2 down to the reference ground GNDA according to the effective enable control signal EN. Of course, in other embodiments, the reference node pull-down unit 253 can also be connected to the reference node A1, and the present invention is not limited to this.

[0053] Figure 3FIG. 4 is a schematic circuit diagram of an enabling control module according to a first embodiment of the present invention. Figure 3 The power-on detection unit 251 is not shown in the enabling control module 250. Figure 3 As shown, the discharge path control unit 252 includes an NMOS transistor MN5, a first terminal of the NMOS transistor MN5 is connected to the second voltage terminal 202, a control terminal of the NMOS transistor MN5 is connected to the enable control signal EN, and a second terminal of the NMOS transistor MN5 is connected to the reference ground GNDA.

[0054] The reference node pull-down unit 253 includes a resistor R1 and NMOS transistors MN6 and MN7. A first end of the resistor R1 is connected to a power supply voltage VCC, a second end of the resistor R1 is connected to a first end of the NMOS transistor MN6 and a control end of the NMOS transistor MN7, the control end of the NMOS transistor MN6 is connected to an enable control signal EN, a second end of the NMOS transistor MN6 is connected to a reference ground GNDA, a first end of the NMOS transistor MN7 is connected to a reference node A2, and a second end of the NMOS transistor MN7 is connected to the reference ground GNDA.

[0055] For example, when the power supply voltage VDD is less than the reference voltage Vref, the enable control signal EN is at a low level, and the NMOS transistors MN5 and MN6 are disconnected, so the discharge path between the second terminals of the NMOS transistors MN1 and MN2 and the reference ground GNDA is disconnected, and no matter whether the input signal Vin is at a high level or a low level, the NMOS transistors MN1 and MN2 cannot have a pull-down effect on the reference nodes A1 and A2. At the same time, since the NMOS transistor MN6 is disconnected, the gate voltage of the NMOS transistor MN7 is pulled up by the resistor R1, so the NMOS transistor MN7 is turned on, and the reference node A2 is pulled down to the reference ground GNDA. At the same time, due to the latching effect of the cross-coupled PMOS transistors MP1 and MP2, the reference node A1 is correspondingly pulled up to the power supply voltage VC, and finally the output logic of the level conversion circuit 200 can also be determined. When the power supply voltage VDD is greater than the reference voltage Vref, the enable control signal EN is at a high level, so the NMOS transistors MN5 and MN6 are turned on, and the NMOS transistor MN7 is turned off, and the enable control module 250 does not affect the normal conversion process of the level conversion circuit 200 .

[0056] It can be seen that the enabling control module 250 of this embodiment can pull down one of the reference nodes A1 and A2 when the power supply voltage VDD has not yet been powered up to the preset value, so that the reference nodes A1 and A2 can have a certain logic potential, so that the output of the level conversion circuit can be determined, but the common source resistor load branch composed of NMOS transistors MN6, MN7 and resistor R1 will have static current power consumption when the level conversion circuit is in a normal working state. To reduce the static current power consumption, the resistance value of resistor R1 is required to be relatively large, which will lead to an increase in the chip area. Taking the power supply voltage VDD equal to 3.3V and the power supply voltage VCC equal to 5V as an example, if it is hoped that the static current power consumption of the circuit is reduced to less than 1uA, the resistance value of resistor R1 needs to be no less than 5MOhm, which will greatly increase the chip area.

[0057] Figure 4 The schematic circuit diagram of the enable control module according to the second embodiment of the present invention is shown. The difference between the enable control module 350 of this embodiment and the enable control module 250 of the first embodiment is that the reference node pull-down unit 353 also includes a PMOS transistor MP5 connected between the second end of the resistor R1 and the first end of the NMOS transistor MN6. The first end of the PMOS transistor MP5 is connected to the resistor R1, the second end of the PMOS transistor MP5 is connected to the first end of the NMOS transistor MN6 and the control end of the NMOS transistor MN7, and the control end of the PMOS transistor MP5 is connected to the enable control signal EN.

[0058] Among them, the PMOS transistor MP5 is used to reduce the static current power consumption of the common source resistor load branch when the level conversion circuit is in normal operation, especially in the low-voltage circuit, the static current power consumption of the enabling control module 350 can be basically eliminated, which can save the chip area and reduce the static power consumption of the circuit. Taking the power supply voltage VDD equal to 3.3V as an example, the power supply voltage VCC equal to 5V as an example, the static current power consumption of the circuit is also reduced to less than 1uA, and the resistor R1 only needs to be no less than 1Mohm. Compared with the 5MOhm resistor before the improvement, the resistance value is reduced by 80%, that is, the circuit area is saved by 80%.

[0059] To summarize, the level conversion circuit in the embodiment of the present invention enables the control module to pull down one of the two logic signals output by the first latch module when the power supply voltage in the low voltage domain has not yet been powered up to a preset value, thereby enabling the output node of the first latch module to be in a certain state before the circuit is powered on, thereby avoiding the level conversion circuit from outputting unstable signals, which is beneficial to improving the reliability of the circuit.

[0060] Furthermore, in many subsequent circuits, there may be strict requirements on the level of the input signal. If the output of the level conversion circuit is in an uncertain state when the power supply voltage in the low voltage domain has not yet been powered on, it may cause erroneous operation or damage to the subsequent circuit. Therefore, the level conversion circuit of this embodiment can protect the subsequent circuit and avoid erroneous operation of the subsequent circuit before power-on.

[0061] Furthermore, the enabling control module of this embodiment can also reduce the static current power consumption of the common source resistance load branch when the level conversion circuit works normally, which can save chip area and reduce the static power consumption of the circuit.

[0062] In the above description, the well-known structural elements and steps are not described in detail. However, it should be understood by those skilled in the art that the corresponding structural elements and steps can be realized by various technical means. In addition, in order to form the same structural elements, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although each embodiment is described above respectively, this does not mean that the measures in each embodiment cannot be advantageously used in combination.

[0063] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A level conversion circuit, include: A first latch module, configured to obtain a first logic signal and a second logic signal whose level ranges from a second power supply voltage to the first reference ground according to an input signal whose level ranges from a first power supply voltage to a first reference ground, wherein the first logic signal and the second logic signal are complementary signals; A second latch module, used for obtaining a third logic signal having a level range from a second power supply voltage to a second reference ground according to the first logic signal and the second logic signal; an output shaping module, configured to obtain an output signal according to the third logic signal, wherein a level range of the output signal is from the second power supply voltage to the second reference ground; as well as The enabling control module is used to pull down one of the first logic signal and the second logic signal to the first reference ground when the first power supply voltage is lower than a set reference voltage.

2. The level conversion circuit according to claim 1, in, The first latch module comprises: a first pull-up unit and a first pull-down unit connected between a first voltage terminal and a second voltage terminal, wherein a first reference node for providing the first logic signal and a second reference node for providing the second logic signal are provided between the first pull-up unit and the first pull-down unit, and the first pull-down unit is used to pull down a potential of one of the first reference node and the second reference node according to the input signal, Among them, the first voltage terminal is used to be connected to the second power supply voltage, the second voltage terminal is used to be connected to the first reference ground via the enable control module, and the enable control module is also used to disconnect the discharge path between the second voltage terminal and the first reference ground when the first power supply voltage is less than the reference voltage.

3. The level conversion circuit according to claim 2, in, The enabling control module comprises: a discharge path control unit, connected between the second voltage terminal and the first reference ground, the discharge path control unit being configured to disconnect a discharge path from the second voltage terminal to the first reference ground according to a valid enable control signal; and a reference node pull-down unit connected to one of the first reference node and the second reference node, the reference node pull-down unit being used to pull down one of the first reference node and the second reference node according to the valid enable control signal, The enable control signal is used to be effective when the first power supply voltage is less than the reference voltage, and is used to be ineffective when the first power supply voltage is greater than / equal to the reference voltage.

4. The level conversion circuit according to claim 3, in, The discharge path control unit comprises: A first transistor of a first conductivity type is provided, wherein a first terminal of the first transistor is connected to the second voltage terminal, a control terminal of the first transistor is connected to the enable control signal, and a second terminal of the first transistor is connected to the first reference ground.

5. The level conversion circuit according to claim 3, in, The reference node pull-down unit comprises: a resistor, a first end of the resistor being connected to the second power supply voltage; a second transistor of a first conductivity type, a first terminal of the second transistor being connected to the second terminal of the resistor, a control terminal of the second transistor being connected to the enable control signal, and a second terminal of the second transistor being connected to the first reference ground; and A third transistor having a first conductivity type, wherein a first terminal of the third transistor is connected to one of the first reference node and the second reference node, a control terminal of the third transistor is connected to a first terminal of the second transistor, and a second terminal of the third transistor is connected to the first reference ground.

6. The level conversion circuit according to claim 5, in, The reference node pull-down unit further includes: A fourth transistor having a second conductivity type, wherein the second conductivity type is different from the first conductivity type, a first end of the fourth transistor is connected to the second end of the resistor, a control end of the fourth transistor is connected to the enable control signal, and a second end of the fourth transistor is connected to the first end of the third transistor.

7. The level conversion circuit according to claim 2, in, The first pull-up unit comprises: a fifth transistor and a sixth transistor having a second conductivity type, wherein the first terminals of the fifth transistor and the sixth transistor are connected to the first voltage terminal, the control terminal of the fifth transistor and the second terminal of the sixth transistor are connected to the second reference node, and the second terminal of the fifth transistor and the control terminal of the sixth transistor are connected to the first reference node, The first pull-down unit comprises: A seventh transistor and an eighth transistor of a first conductivity type, wherein the first end of the seventh transistor is connected to the first reference node, the first end of the eighth transistor is connected to the second reference node, the control end of the seventh transistor is used to receive the input signal, the control end of the eighth transistor is used to receive an inverted signal of the input signal, and the second ends of the seventh transistor and the eighth transistor are connected to the second voltage end.

8. The level conversion circuit according to claim 2, in, The second latch module comprises: a second pull-up unit and a second pull-down unit connected between the first voltage terminal and the third voltage terminal, a third reference node for providing the third logic signal is provided between the second pull-up unit and the second pull-down unit, an input of the second pull-up unit is connected to the first reference node and the second reference node, The first voltage terminal is used to connect to the second power supply voltage, and the third voltage terminal is used to connect to the second reference ground. Wherein, the second pull-up unit comprises: a ninth transistor and a tenth transistor having a second conductivity type, wherein the first terminals of the ninth transistor and the tenth transistor are connected to the first voltage terminal, the control terminal of the ninth transistor is connected to the first reference node, the second terminal of the ninth transistor is connected to the third reference node and the second pull-down unit, the control terminal of the tenth transistor is connected to the second reference node, and the second terminal of the tenth transistor is connected to the second pull-down unit, Wherein, the second pull-down unit comprises: An eleventh transistor and a twelfth transistor of the first conductivity type are provided, wherein the first end of the eleventh transistor and the control end of the twelfth transistor are connected to the third reference node and the second end of the ninth transistor, the first end of the twelfth transistor and the control end of the eleventh transistor are connected to the second end of the tenth transistor, and the second ends of the eleventh transistor and the twelfth transistor are connected to the third voltage end.

9. The level conversion circuit according to any one of claims 3 to 6, in, The enabling control module also includes: A power-on detection unit, wherein the power-on detection unit is used to compare the first power supply voltage with the reference voltage to generate the enable control signal.

10. The level conversion circuit according to any one of claims 4 to 8, in, The first conductivity type is N type, and the second conductivity type is P type.

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