Semiconductor structure
By setting a large area of island-shaped conductive layer on the top surface of the magnetoresistive random access memory cell and setting a through hole on the substrate, the problem of difficulty in connecting the bit line and the magnetoresistive random access memory cell is solved. Achieved stable electrical connection and memory efficiency improvement.
Patent Information
- Application Number
- CN202310722664.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-16
- Publication Date
- 2024-12-17
AI Technical Summary
As the memory component size decreases, it is difficult to connect the bit line and the top electrode of the magnetoresistive random access memory cell, resulting in poor electrical connection and affecting memory performance.
A larger area of island-shaped conductive layer is provided on the top surface of the magnetoresistive random access memory cell to ensure the effective electrical connection between the bit line and the magnetoresistive random access memory cell, and through the island-shaped conductive layer and the line layer Electrically connect, and through holes are provided on the substrate to achieve stable connection.
It effectively reduces the difficulty of connecting the bit line and the magnetoresistive random access memory unit, ensures the reliability and effectiveness of the electrical connection, and avoids connection problems caused by too small bit line width.
Smart Images
Figure CN119156017A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure including a magnetoresistive random access memory cell (MRAM cell) and a bit line. Background Art
[0002] Non-volatile memory has the advantage that the stored data will not disappear after power failure, so it has become a widely used memory in personal computers and other electronic devices. Magnetoresistive random access memory is a non-volatile memory that stores information based on the direction of the magnetic moment in the magnetic film layer.
[0003] Generally speaking, a magnetoresistive random access memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top electrode and the bottom electrode. The magnetoresistive random access memory cell can be operated through a bit line connected to the top electrode. However, as the size of the memory component continues to shrink, the area of the top electrode of the magnetoresistive random access memory cell and the width of the bit line are also reduced. As a result, the connection difficulty between the bit line and the top electrode of the magnetoresistive random access memory cell increases (for example, there is a gap between the bit line and the top electrode of the magnetoresistive random access memory cell), which in turn causes the bit line to be unable to be effectively electrically connected to the magnetoresistive random access memory cell, affecting the performance of the memory component. Summary of the invention
[0004] The present invention is directed to a semiconductor structure, wherein an island-shaped conductive layer with a relatively large area is arranged on the top surface of a magnetoresistive random access memory unit to facilitate the electrical connection between a bit line and the magnetoresistive random access memory unit.
[0005] The semiconductor structure of the present invention comprises a circuit layer, an island-shaped conductive layer, a magnetoresistive random access memory unit, a bit line and a via. The circuit layer is arranged on a substrate. The island-shaped conductive layer is arranged on the circuit layer. The magnetoresistive random access memory unit is arranged between the island-shaped conductive layer and the circuit layer, and is electrically connected to the island-shaped conductive layer and the circuit layer. The bit line is arranged on the island-shaped conductive layer. The via is arranged between the bit line and the island-shaped conductive layer. The island-shaped conductive layer is in contact with the top surface of the magnetoresistive random access memory unit.
[0006] In an embodiment of the semiconductor structure of the present invention, a projected area of the island-shaped conductive layer on the substrate is larger than a projected area of the magnetoresistive random access memory unit on the substrate.
[0007] In one embodiment of the semiconductor structure of the present invention, one of the island-shaped conductive layers is connected to a top surface of one of the magnetoresistive random access memory cells.
[0008] In an embodiment of the semiconductor structure of the present invention, the island-shaped conductive layer includes a metal layer.
[0009] In an embodiment of the semiconductor structure of the present invention, a semiconductor component is disposed on the surface of the substrate, and the circuit layer is electrically connected to the semiconductor component.
[0010] In an embodiment of the semiconductor structure of the present invention, the semiconductor device includes a transistor.
[0011] In an embodiment of the semiconductor structure of the present invention, the magnetoresistive random access memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction structure disposed between the top electrode and the bottom electrode.
[0012] The semiconductor structure of the present invention comprises a substrate, a circuit layer, a first conductive layer, a magnetoresistive random access memory cell, a first conductive hole, a second conductive layer, a second conductive hole and a third conductive hole. The substrate has a memory area and a peripheral area. The circuit layer is arranged on the substrate and comprises a memory circuit part located in the memory area and a peripheral circuit part located in the peripheral area, which are separated from each other. The first conductive layer is arranged on the circuit layer and comprises an island part located in the memory area and a first circuit part located in the peripheral area, which are separated from each other. The magnetoresistive random access memory cell is arranged between the island part and the memory circuit part and is electrically connected to the island part and the memory circuit part. The first conductive hole is arranged between the first circuit part and the peripheral circuit part. The second conductive layer is arranged on the first conductive layer and comprises a bit line part located in the memory area and a second circuit part located in the peripheral area, which are separated from each other. The second conductive hole is arranged between the bit line part and the island part. The third conductive hole is arranged between the first circuit part and the second circuit part. The island portion contacts a top surface of the magnetoresistive random access memory cell.
[0013] In an embodiment of the semiconductor structure of the present invention, a projected area of the island portion on the substrate is larger than a projected area of the magnetoresistive random access memory unit on the substrate.
[0014] In an embodiment of the semiconductor structure of the present invention, one of the island portions is connected to a top surface of one of the magnetoresistive random access memory cells.
[0015] In an embodiment of the semiconductor structure of the present invention, the island portion and the first circuit portion are located at the same level.
[0016] In an embodiment of the semiconductor structure of the present invention, a top surface of the island portion is coplanar with a top surface of the first circuit portion.
[0017] In an embodiment of the semiconductor structure of the present invention, the bit line portion and the second line portion are located at the same level.
[0018] In an embodiment of the semiconductor structure of the present invention, a top surface of the bit line portion is coplanar with a top surface of the second line portion.
[0019] In an embodiment of the semiconductor structure of the present invention, a height of the second conductive via is the same as a height of the third conductive via.
[0020] In an embodiment of the semiconductor structure of the present invention, a semiconductor component is disposed on the surface of the substrate, and the circuit layer is electrically connected to the semiconductor component.
[0021] In an embodiment of the semiconductor structure of the present invention, the semiconductor device includes a transistor.
[0022] In an embodiment of the semiconductor structure of the present invention, the magnetoresistive random access memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction structure disposed between the top electrode and the bottom electrode.
[0023] Based on the above, in the semiconductor structure of the present invention, the island-shaped conductive layer (the island-shaped portion of the conductive layer) is disposed on the top surface of the magnetoresistive random access memory cell, and the projection area of the island-shaped conductive layer (the island-shaped portion of the conductive layer) on the substrate is larger than the projection area of the connected magnetoresistive random access memory cell on the substrate, so that the island-shaped conductive layer (the island-shaped portion of the conductive layer) has a larger area than the top surface of the magnetoresistive random access memory cell. Therefore, the conductive via located between the bit line and the magnetoresistive random access memory cell can be easily and reliably disposed on the island-shaped conductive layer (the island-shaped portion of the conductive layer). In this way, the problem that the bit line cannot be effectively electrically connected to the magnetoresistive random access memory cell due to its too small width can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1A is a cross-sectional schematic diagram of a semiconductor structure according to a first embodiment of the present invention;
[0025] Figure 1B is a top view schematically showing a semiconductor structure according to a first embodiment of the present invention;
[0026] Figure 2FIG. 4 is a schematic cross-sectional view of a semiconductor structure according to a second embodiment of the present invention. DETAILED DESCRIPTION
[0027] The following examples are listed and described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn to their original size. For ease of understanding, the same components are indicated by the same symbols in the following description.
[0028] The terms "include", "including", "have", etc. used in this document are open terms, which means "including but not limited to".
[0029] When the terms "first", "second", etc. are used to describe components, they are only used to distinguish these components from each other, and do not limit the order or importance of these components. Therefore, in some cases, the first component may also be referred to as the second component, and the second component may also be referred to as the first component, and this does not deviate from the scope of the present invention.
[0030] In addition, directional terms such as "upper", "lower", etc. mentioned herein are only used to refer to the directions of the drawings and are not used to limit the present invention. Therefore, it should be understood that "upper" can be used interchangeably with "lower", and when a component such as a layer or film is placed "on" another component, the component can be placed directly on the other component, or there can be an intermediate component. On the other hand, when a component is said to be placed "directly" on another component, there is no intermediate component between the two.
[0031] Figure 1A is a schematic cross-sectional view of a semiconductor structure according to a first embodiment of the present invention, Figure 1B is a top view schematically showing a semiconductor structure according to a first embodiment of the present invention, and Figure 1A is based on Figure 1B In addition, Figure 1B In order to make the drawings clear, the Figure 1A The invention relates to a semiconductor device and an interconnect structure disposed on a substrate.
[0032] Please also refer to Figure 1A and Figure 1B The semiconductor structure of the present embodiment includes a substrate 100, a circuit layer 104, a via 106, an island-shaped conductive layer 108, a magnetoresistive random access memory unit 110, a bit line 112, and a via 114. The semiconductor structure of the present embodiment includes a plurality of magnetoresistive random access memory units 110, but the present invention is not limited thereto. In addition, the magnetoresistive random access memory units 110 can be operated through the bit line 112. Therefore, the semiconductor structure of the present embodiment can be applied to a magnetoresistive random access memory device.
[0033] In the present embodiment, the substrate 100 may be a silicon substrate, and a semiconductor component 102 is disposed thereon. The semiconductor component 102 is, for example, a transistor. The circuit layer 104 is disposed on the substrate 100. In the present embodiment, the circuit layer 104 is electrically connected to the semiconductor component 102 disposed on the substrate 100 through the via 106. Therefore, the circuit layer 104 can be regarded as the first metal layer (metal 1, M1) well known in the art, but the present invention is not limited thereto. In other embodiments, depending on actual needs, more than one circuit layer and vias connecting adjacent circuit layers may be disposed between the circuit layer 104 and the semiconductor component 102. The circuit layer 104, the via 106, and other circuit layers and vias disposed according to actual conditions constitute a well-known interconnection structure.
[0034] The island-shaped conductive layer 108 is disposed on the circuit layer 104. In addition, the magnetoresistive random access memory unit 110 is disposed between the island-shaped conductive layer 108 and the circuit layer 104, and is electrically connected to the island-shaped conductive layer 108 and the circuit layer 104. The island-shaped conductive layer 108 may be a metal layer. Therefore, in the case where the circuit layer 104 is the first metal layer (M1), the island-shaped conductive layer 108 may be regarded as the second metal layer (M2). In the present embodiment, the magnetoresistive random access memory unit 110 includes a top electrode 110a, a bottom electrode 110b, and a magnetic tunnel junction structure 110c disposed between the top electrode 110a and the bottom electrode 110b. The top electrode 110a of the magnetoresistive random access memory unit 110 is connected to the island-shaped conductive layer 108. That is, in the present embodiment, the island-shaped conductive layer 108 is in contact with the top surface of the magnetoresistive random access memory unit 110.
[0035] In the present embodiment, one island-shaped conductive layer 108 is connected to the top surface of only one magnetoresistive random access memory unit 110. The projected area of the island-shaped conductive layer 108 on the substrate 100 is larger than the projected area of the connected magnetoresistive random access memory unit 110 on the substrate 100. That is, in the present embodiment, the island-shaped conductive layer 108 serves as a connecting member between the magnetoresistive random access memory unit 110 and other components (e.g., vias). In addition, since the island-shaped conductive layer 108 has a larger area than the top surface of the magnetoresistive random access memory unit 110, the difficulty of connecting the magnetoresistive random access memory unit 110 with the other components can be effectively reduced to ensure an effective electrical connection between the two.
[0036] In addition, in this embodiment, the bottom electrode 110b of the magnetoresistive random access memory cell 110 is in contact with the circuit layer 104, but the present invention is not limited thereto. In other embodiments, the bottom electrode 110b may be electrically connected to the circuit layer 104 through a via.
[0037] The bit line 112 is disposed on the island-shaped conductive layer 108, and the via 114 is disposed between the bit line 112 and each island-shaped conductive layer 108, so that the bit line 112 can be electrically connected to each magnetoresistive random access memory cell 110 through the via 114 to operate the magnetoresistive random access memory cell 110. In the case where the circuit layer 104 is the first metal layer (M1) and the island-shaped conductive layer 108 is the second metal layer (M2), the bit line 112 can be regarded as the third metal layer (M3). In other embodiments, depending on actual needs, more than one circuit layer and vias connecting adjacent circuit layers can be disposed between the bit line 112 and the island-shaped conductive layer 108.
[0038] In the present embodiment, since the projection area of the island-shaped conductive layer 108 on the substrate 100 is larger than the projection area of the connected magnetoresistive random access memory unit 110 on the substrate 100, the island-shaped conductive layer 108 has a larger area than the top surface of the magnetoresistive random access memory unit 110, so each via 114 can be easily and reliably disposed on the corresponding island-shaped conductive layer 108. In this way, the bit line 112 can be electrically connected to each magnetoresistive random access memory unit 110 through these vias 114, and the problem that the bit line cannot be effectively electrically connected to the magnetoresistive random access memory unit 110 due to its too small width can be avoided.
[0039] In addition, the semiconductor structure of this embodiment can be integrated with other structures in the peripheral region, which will be described below.
[0040] Figure 2 FIG. 2 is a cross-sectional view of a semiconductor structure according to a second embodiment of the present invention. In this embodiment, the same components as those in the first embodiment are denoted by the same reference symbols and will not be described again.
[0041] Please refer to Figure 2 , the semiconductor structure of the present embodiment includes a substrate 100, a circuit layer 104, a via 106a, a via 106b, a first conductive layer 200, a magnetoresistive random access memory unit 110, a via 202, a second conductive layer 204, a via 206a, and a via 206b. In the present embodiment, the substrate 100 has a memory area 100a and a peripheral area 100b. The peripheral area 100b is, for example, a logic component area, but the present invention is not limited thereto. The semiconductor component 102 is disposed on the substrate 100 in the memory area 100a and the peripheral area 100b. Figure 2 In the figures, the numbers of various components are only used as examples and are not intended to limit the present invention.
[0042] The circuit layer 104 is disposed on the substrate 100. In the present embodiment, the circuit layer 104 includes a memory circuit portion 104a located in the memory area 100a and a peripheral circuit portion 104b located in the peripheral area 100b, which are separated from each other. The memory circuit portion 104a is electrically connected to the semiconductor device 102 in the memory area 100a through the via 106a, and the peripheral circuit portion 104b is electrically connected to the semiconductor device 102 in the peripheral area 100b through the via 106b.
[0043] The first conductive layer 200 is disposed on the circuit layer 104. In the present embodiment, the first conductive layer 200 includes an island portion 200a located in the memory area 100a and a first circuit portion 200b located in the peripheral area 100b, which are separated from each other. The magnetoresistive random access memory cell 110 is disposed between the island portion 200a and the memory circuit portion 104a, and is electrically connected to the island portion 200a and the memory circuit portion 104a. In addition, the via 202 is disposed between the first circuit portion 200b and the peripheral circuit portion 104b of the circuit layer 104, so that the first circuit portion 200b can be electrically connected to the semiconductor device 102 in the peripheral area 100b through the via 202, the peripheral circuit portion 104b and the via 106b.
[0044] The island-shaped portion 200a of the first conductive layer 200 may correspond to the island-shaped conductive layer 108 in the first embodiment. Like the island-shaped conductive layer 108, the island-shaped portion 200a contacts the top surface of the magnetoresistive random access memory unit 110. In addition, one island-shaped portion 200a is connected to the top surface of only one magnetoresistive random access memory unit 110. The projected area of the island-shaped portion 200a on the substrate 100 is larger than the projected area of the connected magnetoresistive random access memory unit 110 on the substrate 100. Since the island-shaped portion 200a has a larger area than the top surface of the magnetoresistive random access memory unit 110, the difficulty of connecting the magnetoresistive random access memory unit 110 to other components (such as vias) can be effectively reduced to ensure effective electrical connection between the two.
[0045] In this embodiment, the first conductive layer 200 includes an island portion 200a and a first line portion 200b separated from each other, and the island portion 200a and the first line portion 200b are located at the same level. In addition, the top surface of the island portion 200a can be coplanar with the top surface of the first line portion 200b.
[0046] In addition, in this embodiment, the bottom electrode 110b of the magnetoresistive random access memory cell 110 contacts the memory circuit portion 104a of the circuit layer 104, but the present invention is not limited thereto. In other embodiments, the bottom electrode 110b may be electrically connected to the memory circuit portion 104a of the circuit layer 104 through a via.
[0047] The second conductive layer 204 is disposed on the first conductive layer 200 and includes a bit line portion 204a located in the memory area 100a and a second line portion 204b located in the peripheral area 100b, which are separated from each other. In the case where the line layer 104 is the first metal layer (M1) and the first conductive layer 200 is the second metal layer (M2), the second conductive layer 204 can be regarded as the third metal layer (M3). In other embodiments, depending on actual needs, more than one line layer and a via connecting adjacent line layers can be disposed between the second conductive layer 204 and the first conductive layer 200.
[0048] The bit line portion 204a is disposed on the island portion 200a, and the via hole 206a is disposed between the bit line portion 204a and each island portion 200a, so that the bit line portion 204a can be electrically connected to each magnetoresistive random access memory cell 110 through the via hole 206a to operate the magnetoresistive random access memory cell 110.
[0049] The second circuit portion 204b is disposed on the first circuit portion 200b, and the via 206b is disposed between the first circuit portion 200b and the second circuit portion 204b, so that the second circuit portion 204b can be electrically connected to the semiconductor component 102 in the peripheral area 100b through the via 206b, the first circuit portion 200b, the via 202, the peripheral circuit portion 104b and the via 106b.
[0050] In the present embodiment, the second conductive layer 204 includes a bit line portion 204a and a second line portion 204b separated from each other, and the bit line portion 204a and the second line portion 204b are located at the same horizontal height. In addition, the top surface of the bit line portion 204a can be coplanar with the top surface of the second line portion 204b. In addition, in the present embodiment, since the top surface of the island portion 200a is coplanar with the top surface of the first line portion 200b, the via 206a and the via 206b can have the same height.
[0051] In this embodiment, since the projection area of the island portion 200a on the substrate 100 is larger than the projection area of the connected magnetoresistive random access memory cell 110 on the substrate 100, the island portion 200a has a larger area than the top surface of the magnetoresistive random access memory cell 110, so each via 206a can be easily and reliably disposed on the corresponding island portion 200a. In this way, the bit line portion 204a serving as a bit line can be electrically connected to each magnetoresistive random access memory cell 110 through these vias 206a, and the problem that the bit line cannot be effectively electrically connected to the magnetoresistive random access memory cell 110 due to its too small width can be avoided.
[0052] The semiconductor structures of the first and second embodiments described above can be applied to various types of magnetoresistive random access memory devices. For example, the semiconductor structure of the embodiment of the present invention can be applied to a magnetoresistive random access memory device including three transistors and two magnetoresistive random access memory cells (3T2M), but the present invention is not limited thereto.
[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A semiconductor structure, characterized in that: include: A circuit layer is arranged on the substrate; An island-shaped conductive layer is disposed on the circuit layer; A magnetoresistive random access memory unit is disposed between the island-shaped conductive layer and the circuit layer, and is electrically connected to the island-shaped conductive layer and the circuit layer; A bit line is disposed on the island-shaped conductive layer; as well as A via hole is provided between the bit line and the island-shaped conductive layer, The island-shaped conductive layer is in contact with the top surface of the magnetoresistive random access memory unit.
2. The semiconductor structure according to claim 1, characterized in that The projected area of the island-shaped conductive layer on the substrate is larger than the projected area of the magnetoresistive random access memory unit on the substrate.
3. The semiconductor structure according to claim 1, characterized in that One of the island-shaped conductive layers is connected to the top surface of one of the magnetoresistive random access memory cells.
4. The semiconductor structure according to claim 1, characterized in that: The island-shaped conductive layer includes a metal layer.
5. The semiconductor structure according to claim 1, characterized in that: A semiconductor component is arranged on the surface of the substrate, and the circuit layer is electrically connected to the semiconductor component.
6. The semiconductor structure according to claim 5, characterized in that: The semiconductor component includes a transistor.
7. The semiconductor structure according to claim 1, characterized in that: The magnetoresistive random access memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction structure disposed between the top electrode and the bottom electrode.
8. A semiconductor structure, characterized in that: include: A substrate having a memory region and a peripheral region; A circuit layer is disposed on the substrate and includes a memory circuit portion located in the memory area and a peripheral circuit portion located in the peripheral area which are separated from each other; A first conductive layer is disposed on the circuit layer and includes an island portion located in the memory area and a first circuit portion located in the peripheral area, which are separated from each other; A magnetoresistive random access memory unit is disposed between the island portion and the memory line portion and is electrically connected to the island portion and the memory line portion; A first conductive via is provided between the first circuit portion and the peripheral circuit portion; A second conductive layer is disposed on the first conductive layer and includes a bit line portion located in the memory area and a second line portion located in the peripheral area which are separated from each other; A second conductive hole is provided between the bit line portion and the island portion; as well as A third conductive via is provided between the first circuit portion and the second circuit portion, The island portion is in contact with a top surface of the magnetoresistive random access memory unit.
9. The semiconductor structure according to claim 8, characterized in that: A projected area of the island portion on the substrate is larger than a projected area of the magnetoresistive random access memory unit on the substrate.
10. The semiconductor structure according to claim 8, characterized in that One of the island portions is connected to a top surface of one of the magnetoresistive random access memory cells.
11. The semiconductor structure according to claim 8, characterized in that: The island portion is located at the same level as the first line portion.
12. The semiconductor structure according to claim 11, characterized in that: A top surface of the island portion is coplanar with a top surface of the first line portion.
13. The semiconductor structure according to claim 8, characterized in that The bit line portion is located at the same level as the second line portion.
14. The semiconductor structure according to claim 13, characterized in that: A top surface of the bit line portion is coplanar with a top surface of the second line portion.
15. The semiconductor structure according to claim 8, characterized in that The height of the second conductive via is the same as that of the third conductive via.
16. The semiconductor structure according to claim 8, characterized in that A semiconductor component is arranged on the surface of the substrate, and the circuit layer is electrically connected to the semiconductor component.
17. The semiconductor structure according to claim 16, characterized in that: The semiconductor component includes a transistor.