Display device and vehicle including the same

Abstract

The invention discloses a display device and a vehicle including the same. The display device includes: a first substrate; the pixel electrode is arranged on the first substrate; a pixel defining layer disposed on the first substrate and covering at least a portion of the pixel electrode; a second substrate disposed on the pixel defining layer and spaced apart from the first substrate and the pixel defining layer to define a space between the second substrate and the pixel defining layer; and a light blocking pattern disposed on a surface of the second substrate facing the first substrate and overlapping the pixel defining layer in a plan view.

Description

Technical Field

[0001] Embodiments relate to a display device, and more particularly, to a display device providing visual information and a vehicle including the display device. Background Art

[0002] If impurities such as moisture, oxygen, or the like enter the display device from the outside, the life of a transistor included in the display device may be shortened, and the light emitting efficiency of a light emitting element included in the display device may be reduced.

[0003] Accordingly, the display device can be encapsulated by isolating the inside of the display device from the outside to prevent impurities from penetrating. For example, the display device may include a substrate and an encapsulation substrate on which a cover or lid is formed. The substrate and the encapsulation substrate may be integrally connected by a sealing member. Summary of the invention

[0004] The embodiment provides a display device with improved display quality.

[0005] An embodiment provides a vehicle including a display device.

[0006] A display device according to an embodiment of the present disclosure includes: a first substrate; a pixel electrode disposed on the first substrate; a pixel defining layer disposed on the first substrate and covering at least a portion of the pixel electrode; a second substrate disposed on the pixel defining layer and spaced apart from the first substrate and the pixel defining layer to define a space between the second substrate and the pixel defining layer; and a light blocking pattern disposed on a surface of the second substrate facing the first substrate and overlapping with the pixel defining layer in a plan view.

[0007] In one embodiment, a distance between an edge of a surface of the pixel defining layer facing the second substrate and an edge of a surface of the light blocking pattern facing the second substrate may satisfy the following equation 1: In Equation 1, X may be the distance between the edge of the surface of the pixel defining layer and the edge of the surface of the light blocking pattern, D may be the distance between the surface of the pixel defining layer and the surface of the second substrate, n1 may be the refractive index of the space, n2 may be the refractive index of the second substrate, n3 may be the refractive index of external air, and θ may be a viewing angle.

[0008] In one embodiment, the width of the surface of the light blocking pattern may satisfy the following Equation 2: W=G-2X. In Equation 2, W may be the width of the surface of the light blocking pattern, and G may be the width of the surface of the pixel defining layer.

[0009] In one embodiment, the display device may further include a spacer disposed between the pixel defining layer and the light blocking pattern.

[0010] In one embodiment, a sum of a thickness of the light blocking pattern and a thickness of the spacer may be greater than about 3 micrometers (μm) and less than or equal to about 20 μm.

[0011] In an embodiment, the light blocking pattern may be provided in plural, and the spacer may overlap at least one of the plurality of light blocking patterns in the plan view.

[0012] In one embodiment, a maximum width of the light blocking pattern may be greater than a width of the spacer.

[0013] In one embodiment, the display device may further include: a light-emitting layer disposed on the pixel electrode; a common electrode disposed on the light-emitting layer, the pixel defining layer and the spacer; and a capping layer disposed on the common electrode.

[0014] In one embodiment, the light blocking pattern may include a black matrix.

[0015] In an embodiment, the display device may further include a sealing member disposed between the first substrate and the second substrate along an edge of each of the first substrate and the second substrate and coupling the first substrate and the second substrate.

[0016] In one embodiment, the second substrate may include a glass substrate.

[0017] In one embodiment, the space may be an empty space.

[0018] In one embodiment, the space may be filled with a filler.

[0019] A vehicle according to an embodiment of the present disclosure includes: a vehicle body defining an interior space; and a display device disposed in the interior space. The display device includes: a first substrate; a pixel electrode disposed on the first substrate; a pixel defining layer disposed on the first substrate and covering at least a portion of the pixel electrode; a spacer disposed on the pixel defining layer; a second substrate disposed on the spacer and spaced apart from the first substrate and the spacer to define a space between the second substrate and the pixel defining layer; a transmission pattern disposed on a surface of the second substrate facing the first substrate and overlapping the pixel defining layer in a plan view; and a light blocking pattern disposed on the transmission pattern and defining an opening that accommodates at least a portion of the spacer.

[0020] In an embodiment, the light blocking pattern may cover at least a portion of a side surface of the spacer.

[0021] In an embodiment, the light blocking pattern may be provided in plural, and the spacer may be received in the opening of at least one of the plurality of light blocking patterns.

[0022] In an embodiment, the transmissive pattern may include a transparent organic material.

[0023] In one embodiment, the light blocking pattern may include a black matrix.

[0024] In an embodiment, the display device may further include a sealing member disposed between the first substrate and the second substrate along an edge of each of the first substrate and the second substrate and coupling the first substrate and the second substrate.

[0025] In one embodiment, the second substrate may include a glass substrate.

[0026] In one embodiment, the space between the second substrate and the pixel defining layer may be an empty space.

[0027] In one embodiment, the space between the second substrate and the pixel defining layer may be filled with a filler.

[0028] In one embodiment, the vehicle may further include an instrument cluster, a center instrument panel adjacent to the instrument cluster, and a passenger seat instrument panel adjacent to the center instrument panel. The display device may be disposed on at least one of the instrument cluster, the center instrument panel, and the passenger seat instrument panel.

[0029] In a display device according to an embodiment of the present disclosure, a light blocking pattern overlapping with a pixel defining layer in a plan view may be disposed between a first substrate and a second substrate. The light blocking pattern may block incident light incident from the outside and reflected light in which the incident light is reflected by the pixel defining layer. In addition, the thickness of the space between the first substrate and the second substrate may be increased. Accordingly, the coherence may be reduced, and the rainbow color shift phenomenon visually recognized at a side viewing angle may be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0031] Figure 2 It is along Figure 1 A cross-sectional view taken along line II'.

[0032] Figure 3yes Figure 2 An enlarged cross-sectional view of area A.

[0033] Figure 4 yes Figure 3 An enlarged cross-sectional view of area B.

[0034] Figure 5 is an example Figure 3 A cross-sectional view of another example of .

[0035] Figure 6 is a plan view illustrating a display device according to another embodiment of the present disclosure.

[0036] Figure 7 It is along Figure 6 A cross-sectional view taken along line II-II'.

[0037] Figure 8 is an example Figure 7 A cross-sectional view of another example of .

[0038] Fig. 9 is a cross-sectional view illustrating a display device according to still another embodiment of the present disclosure.

[0039] Fig.10 is an example Fig. 9 A cross-sectional view of another example of .

[0040] Fig.11 is a view schematically illustrating the exterior of a vehicle according to an embodiment of the present disclosure.

[0041] Fig.12 is a schematic illustration Fig.11 View of the interior of the vehicle. DETAILED DESCRIPTION

[0042] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the teachings herein, the first element, component, region, layer or section discussed below may be referred to as a second element, component, region, layer or section.

[0043] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to be restrictive. As used herein, "one", "the" and "at least one" do not represent the limitation of quantity, and are intended to include both the singular and the plural, unless the context clearly states otherwise. For example, "an element" has the same meaning as "at least one element", unless the context clearly states otherwise. "At least one" should not be interpreted as limiting "one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the term "including" or "comprising" when used in this specification clearly indicates that there are stated features, regions, integers, steps, operations, elements and / or parts, but does not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, parts and / or its groups.

[0044] It will be understood that when an element is referred to as being "on" or "connected to" another element, it may be directly on or directly connected to the other element, or intervening elements may exist therebetween. Conversely, when an element is referred to as being "directly on" another element, no intervening elements are present. Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and redundant descriptions of the same components will be omitted.

[0045] Figure 1 is a plan view illustrating a display device according to an embodiment of the present disclosure. As used herein, a "plan view" is a view in which a first substrate (see Figure 2 A view in the thickness direction (i.e., the third direction DR3) of SUB1).

[0046] refer to Figure 1 , the display device 10 may include a display area DA and a non-display area NDA. The display area DA may be an area that displays an image by generating light or adjusting the transmittance of light provided from an external light source. The non-display area NDA may be an area that does not display an image. The non-display area NDA may be located around the display area DA. In one embodiment, for example, the non-display area NDA may surround the entire display area DA.

[0047] A plurality of pixels PX may be disposed in the display area DA. The plurality of pixels PX may be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. In one embodiment, for example, the first direction DR1 may be perpendicular to the second direction DR2. Each of the plurality of pixels PX may emit light. When each of the plurality of pixels PX emits light, the display area DA may display an image.

[0048] Lines connected to the plurality of pixels PX may be further disposed in the display area DA. In one embodiment, for example, the lines may include data signal lines, gate signal lines, power lines, and the like.

[0049] A driver for driving the plurality of pixels PX may be disposed in the non-display area NDA. In one embodiment, for example, the driver may include a data driver, a gate driver, a power supply voltage generator, a timing controller, etc. The plurality of pixels PX may emit light based on a signal received from the driver.

[0050] Figure 2 It is along Figure 1 A cross-sectional view taken along line II'.

[0051] refer to Figure 1 and Figure 2 , the display device 10 may include a first substrate SUB1, a second substrate SUB2, and a sealing member SM.

[0052] The first substrate SUB1 may include a transparent material or an opaque material. In one embodiment, for example, the first substrate SUB1 may include a rigid glass substrate, a polymer substrate, a flexible film, a metal substrate, etc. These may be used alone or in combination with each other. In one embodiment, the first substrate SUB1 may include a rigid glass substrate.

[0053] The second substrate SUB2 may be disposed on the first substrate SUB1. The second substrate SUB2 may face the first substrate SUB1. The second substrate SUB2 may be spaced apart from the first substrate SUB1 in a third direction DR3 intersecting each of the first direction DR1 and the second direction DR2. In one embodiment, for example, the third direction DR3 may be perpendicular to each of the first direction DR1 and the second direction DR2. Accordingly, a space SP may be defined between the first substrate SUB1 and the second substrate SUB2. In one embodiment, the space SP may be an empty space (for example, in a vacuum state). In another embodiment, the space SP may be filled with a filler.

[0054] The second substrate SUB2 may include a transparent material or an opaque material. In one embodiment, for example, the second substrate SUB2 may include a rigid glass substrate, a polymer substrate, a flexible film, a metal substrate, etc. These may be used alone or in combination with each other. In one embodiment, the second substrate SUB2 may include a glass substrate, such as a rigid glass substrate.

[0055] The sealing member SM may be disposed along an edge of each of the first substrate SUB1 and the second substrate SUB2 and between the first substrate SUB1 and the second substrate SUB2. That is, the sealing member SM may be disposed between the first substrate SUB1 and the second substrate SUB2 along the non-display area NDA. The first substrate SUB1 and the second substrate SUB2 may be coupled to each other by the sealing member SM. Since the space SP between the first substrate SUB1 and the second substrate SUB2 is sealed by the sealing member SM, external moisture, air, impurities, etc. may be prevented from penetrating into the space SP. In one embodiment, for example, the sealing member SM may include an organic material such as an epoxy resin.

[0056] Figure 3 yes Figure 2 An enlarged cross-sectional view of area A. Figure 4 yes Figure 3 An enlarged cross-sectional view of area B.

[0057] refer to Figure 3 and Figure 4 The display device 10 may include a first substrate SUB1, a buffer layer BUF, a transistor TR, a gate insulating layer GI, an interlayer insulating layer ILD, a via insulating layer VIA, a pixel defining layer PDL, a light emitting element LD, a spacer SPC, a capping layer CPL, a light blocking pattern BP and a second substrate SUB2.

[0058] The transistor TR may include an active pattern ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The light emitting element LD may include a pixel electrode PE, a light emitting layer EL, and a common electrode CE.

[0059] The buffer layer BUF may be disposed on the first substrate SUB1. The buffer layer BUF may prevent metal atoms or impurities from diffusing from the first substrate SUB1 to the transistor TR. In addition, when the surface of the first substrate SUB1 is uneven, the buffer layer BUF may improve the flatness of the surface of the first substrate SUB1. The buffer layer BUF may include an inorganic material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other.

[0060] The active pattern ACT may be disposed on the buffer layer BUF. The active pattern ACT may include a source region, a drain region, and a channel region between the source region and the drain region. The active pattern ACT may include a silicon semiconductor material or an oxide semiconductor material. Examples of silicon semiconductor materials may include amorphous silicon, polycrystalline silicon, and the like. Examples of oxide semiconductor materials may include indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), and the like. These may be used alone or in combination with each other.

[0061] The gate insulating layer GI may be disposed on the buffer layer BUF. The gate insulating layer GI may fully cover the active pattern ACT and may have a substantially flat upper surface without generating steps around the active pattern ACT. Alternatively, the gate insulating layer GI may cover the active pattern ACT and may be disposed with a uniform thickness along the contour of the active pattern ACT. The gate insulating layer GI may include an inorganic material such as silicon oxide (SiO x ), silicon nitride (SiN x ), Silicon Carbide (SiC x ), silicon oxynitride (SiO x N y ), Silicon Oxycarbide (SiO x C y ) etc. These may be used alone or in combination with each other.

[0062] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap with the channel region of the active pattern ACT in a plan view. The gate electrode GE may include a metal, an alloy, a conductive metal oxide, a metal nitride, or the like. Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), or the like. Examples of conductive metal oxides may include indium tin oxide, indium zinc oxide, or the like. Examples of metal nitrides may include aluminum nitride (AlN x ), tungsten nitride (WN x ), chromium nitride (CrN x ) etc. These may be used alone or in combination with each other.

[0063] The interlayer insulating layer ILD may be disposed on the gate insulating layer GI. The interlayer insulating layer ILD may fully cover the gate electrode GE and may have a substantially flat upper surface without generating steps around the gate electrode GE. Alternatively, the interlayer insulating layer ILD may cover the gate electrode GE and may be disposed with a uniform thickness along the contour of the gate electrode GE. The interlayer insulating layer ILD may include an inorganic material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, etc. These may be used alone or in combination with each other.

[0064] The source electrode SE and the drain electrode DE may be disposed on the interlayer insulating layer ILD. The source electrode SE may be connected to the source region of the active pattern ACT through a first contact hole penetrating the gate insulating layer GI and the first portion of the interlayer insulating layer ILD. In addition, the drain electrode DE may be connected to the drain region of the active pattern ACT through a second contact hole penetrating the gate insulating layer GI and the second portion of the interlayer insulating layer ILD. In an embodiment, for example, each of the source electrode SE and the drain electrode DE may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0065] Accordingly, a transistor TR including an active pattern ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE may be disposed on the first substrate SUB1.

[0066] The via insulating layer VIA may be disposed on the interlayer insulating layer ILD. The via insulating layer VIA may fully cover the source electrode SE and the drain electrode DE. The via insulating layer VIA may include an organic material such as phenolic resin, acrylic resin, polyimide resin, polyamide resin, siloxane resin, epoxy resin, etc. These may be used alone or in combination with each other.

[0067] The pixel electrode PE may be disposed on the through-hole insulating layer VIA. The pixel electrode PE may be connected to the drain electrode DE through a contact hole penetrating the through-hole insulating layer VIA. The pixel electrode PE may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. For example, the pixel electrode PE may operate as an anode.

[0068] The pixel defining layer PDL may be disposed on the through-hole insulating layer VIA. The pixel defining layer PDL may cover at least a portion of the pixel electrode PE. In one embodiment, for example, the pixel defining layer PDL may cover the edge of the pixel electrode PE. That is, an opening exposing at least a portion of the upper surface of the pixel electrode PE may be defined in the pixel defining layer PDL. The pixel defining layer PDL may include an inorganic material or an organic material. In one embodiment, for example, the pixel defining layer PDL may include an organic material such as an epoxy resin, a silicone resin, or the like. These may be used alone or in combination with each other. For another example, the pixel defining layer PDL may include an inorganic material or an organic material including a black light blocking material.

[0069] The spacer SPC may be disposed on the pixel defining layer PDL. Specifically, the spacer SPC may protrude from the upper surface of the pixel defining layer PDL in the thickness direction (e.g., the third direction DR3). The spacer SPC may prevent the display characteristics from being deteriorated due to external impact. The spacer SPC may be used to maintain the space SP between the first substrate SUB1 and the second substrate SUB2. In addition, the spacer SPC may be used to support a fine metal mask (FMM) for depositing an organic light emitting material. The spacer SPC may include an inorganic material or an organic material.

[0070] In one embodiment, for example, the spacer SPC may be formed simultaneously with the pixel defining layer PDL by the same process. In this case, the spacer SPC may include the same material as the pixel defining layer PDL. For another example, the spacer SPC may be formed by a process separate from the pixel defining layer PDL. In this case, the spacer SPC may include a material different from that of the pixel defining layer PDL, or may include the same material as that of the pixel defining layer PDL.

[0071] The light emitting layer EL may be disposed on the pixel electrode PE. Specifically, the light emitting layer EL may be disposed in an opening in the pixel defining layer PDL. The light emitting layer EL may include an organic light emitting material that emits light of a preset color. In one embodiment, for example, the light emitting layer EL may include an organic light emitting material that emits red light, green light, or blue light.

[0072] The common electrode CE may be disposed on the light emitting layer EL, the pixel defining layer PDL and the spacer SPC. The common electrode CE may be a plate-shaped electrode. The common electrode CE may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In one embodiment, for example, the common electrode CE may operate as a cathode.

[0073] Accordingly, a light emitting element LD including a pixel electrode PE, a light emitting layer EL, and a common electrode CE may be disposed on the first substrate SUB1. The light emitting element LD may be electrically connected to the transistor TR.

[0074] The capping layer CPL may be disposed on the common electrode CE. The capping layer CPL may protect the common electrode CE. The capping layer CPL may include an organic insulating material or an inorganic insulating material.

[0075] In one embodiment, the light blocking pattern BP may be disposed between the capping layer CPL and the second substrate SUB2. Specifically, the light blocking pattern BP may be disposed on a surface S1 of the second substrate SUB2 facing the first substrate SUB1. The light blocking pattern BP may contact each of the surface S1 of the second substrate SUB2 and the capping layer CPL. In addition, the light blocking pattern BP may overlap with each of the pixel defining layer PDL and the spacer SPC in a plan view. For example, the spacer SPC may be disposed between the pixel defining layer PDL and the light blocking pattern BP. The light blocking pattern BP may be used to maintain a space SP between the first substrate SUB1 and the second substrate SUB2 together with the spacer SPC. For example, the second substrate SUB2 may be disposed on the pixel defining layer PDL and the spacer SPC and spaced apart from the first substrate SUB1, the pixel defining layer PDL and the spacer SPC to define a space SP between the second substrate SUB2 and the pixel defining layer PDL.

[0076] The light blocking pattern BP may include a light blocking material. In one embodiment, for example, the light blocking pattern BP may include a black matrix. The light blocking pattern BP may absorb or block incident light L1 incident from the outside through the second substrate SUB2. In addition, the light blocking pattern BP may absorb or block reflected light L2 in which the incident light L1 is reflected by the pixel defining layer PDL.

[0077] When the light blocking pattern BP is not disposed between the pixel defining layer PDL and the second substrate SUB2, interference may occur between the reflected light L2 reflected and emitted by the pixel defining layer PDL and the re-reflected light in which the reflected light L2 is re-reflected and emitted by the second substrate SUB2. In this case, due to the interference, a color shift of the rainbow color can be visually recognized at a viewing angle θ (e.g., a side viewing angle). The viewing angle θ at which the user visually recognizes the color shift may be approximately 60° or less. Here, the "viewing angle" θ is defined as the maximum angle between the user's gaze direction and the normal vector of the upper surface of the second substrate SUB2 parallel to the third direction DR3, wherein the user's gaze direction is the direction in which the user can view an image having a predetermined acceptable quality level output from the display device 10. That is, when the display device 10 is observed from a vertical direction, the viewing angle θ may be approximately 0°.

[0078] On the other hand, when the light blocking pattern BP is disposed between the pixel defining layer PDL and the second substrate SUB2, the light blocking pattern BP can absorb or block the incident light L1 and the reflected light L2 and reduce the coherence. That is, the color shift under the viewing angle θ caused by interference can be effectively reduced.

[0079] In this case, the light blocking pattern BP may be disposed so that color shift does not occur at a viewing angle θ of about 60°. In other words, the light blocking pattern BP may be disposed so that color shift does not occur when a viewing angle of light L3 in which reflected light L2 is refracted by the second substrate SUB2 and emitted to the outside is about 60°.

[0080] However, the present disclosure is not limited thereto, and the viewing angle θ considered in the arrangement of the light blocking pattern BP may be variously changed. Alternatively, when the display device 10 is used in a vehicle, the light blocking pattern BP may be arranged so that color shift does not occur at a viewing angle θ of about 0° to about 10°.

[0081] In one embodiment, a distance X between an edge of the light blocking pattern BP facing the surface S2 of the second substrate SUB2 and an edge of the pixel defining layer PDL facing the surface S3 of the second substrate SUB2 may have a constant range. The distance X may satisfy the following equation 1:

[0082] [Equation 1]

[0083]

[0084] In Equation 1, D may be the distance between the surface S3 of the pixel defining layer PDL and the surface S1 of the second substrate SUB2, and θ may be the viewing angle. In addition, n1 may be the refractive index of the space SP, n2 may be the refractive index of the second substrate SUB2, and n3 may be the refractive index of the outside.

[0085] In one embodiment, when the space SP is in a vacuum state, the refractive index n1 of the space SP may be the refractive index of a vacuum (eg, 1). In another embodiment, when the space SP is filled with a filler, the refractive index n1 of the space SP may be the refractive index of the filler.

[0086] In one embodiment, the refractive index n3 of the outside may be the refractive index of the outside air. That is, the refractive index n3 of the outside may be about 1.

[0087] In one embodiment, for example, the space SP may be in a vacuum state, and the refractive index n1 of the space SP may be about 1. The refractive index n2 of the second substrate SUB2 may be about 1.5, and the refractive index n3 of the outside may be about 1. The viewing angle θ may be about 60°, and the distance X may be about 4 micrometers (μm) to about 6 μm. However, the present disclosure is not limited thereto.

[0088] In addition, the width W of the surface S2 of the light blocking pattern BP may satisfy the following Equation 2. In this case, the width W of the surface S2 of the light blocking pattern BP may be the length of the surface S2 of the light blocking pattern BP in the second direction DR2.

[0089] [Equation 2]

[0090] W = G-2X.

[0091] In Equation 2, G may be a width of a surface S3 of the pixel defining layer PDL, and X may be a distance between an edge of the light blocking pattern BP facing the surface S2 of the second substrate SUB2 and an edge of the pixel defining layer PDL facing the surface S3 of the second substrate SUB2.

[0092] In this case, the width G of the surface S3 of the pixel defining layer PDL may be the length of the surface S3 of the pixel defining layer PDL in the second direction DR2 , and the width W of the surface S2 of the light blocking pattern BP may be a positive number.

[0093] In one embodiment, the maximum width of the light blocking pattern BP in the second direction DR2 (e.g., the width W of the surface S2) may be greater than the width of the spacer SPC. In this case, the width of the spacer SPC may be the length of the spacer SPC in the second direction DR2. However, the present disclosure is not limited thereto. Alternatively, in another embodiment, the width W of the surface S2 of the light blocking pattern BP may be less than or equal to the width of the spacer SPC.

[0094] In addition, the sum of the thickness L of the light blocking pattern BP and the thickness H of the spacer SPC may be greater than about 3 μm and less than or equal to about 20 μm. In this case, the thickness L of the light blocking pattern BP and the thickness H of the spacer SPC may be the length of the light blocking pattern BP in the third direction DR3 and the length of the spacer SPC in the third direction DR3, respectively. In one embodiment, for example, the thickness L of the light blocking pattern BP may be about 1.2 μm to about 1.8 μm, but the present disclosure is not limited thereto.

[0095] Since the light blocking pattern BP is disposed between the spacer SPC and the second substrate SUB2, the length of the space SP in the third direction DR3 may be relatively thick, and interference causing color shift may be effectively reduced.

[0096] Figure 5 is an example Figure 3 A cross-sectional view of another example of .

[0097] refer to Figure 3 and Figure 5 The display device 10 may include a first substrate SUB1, a buffer layer BUF, a transistor TR, a gate insulating layer GI, an interlayer insulating layer ILD, a via insulating layer VIA, a pixel defining layer PDL, a light emitting element LD, a spacer SPC, a capping layer CPL, a light blocking pattern BP and a second substrate SUB2.

[0098] However, in addition to the spacer SPC, reference Figure 5 The display device 10 described can be used with reference Figure 3 The display device 10 described is substantially the same or similar. Hereinafter, redundant descriptions will be omitted or simplified.

[0099] A buffer layer BUF, an active pattern ACT, a gate insulating layer GI, a gate electrode GE, an interlayer insulating layer ILD, a source electrode SE, a drain electrode DE, a via insulating layer VIA, a pixel electrode PE, a pixel defining layer PDL and a light emitting layer EL may be sequentially disposed on the first substrate SUB1.

[0100] The spacer SPC may be disposed on the pixel defining layer PDL. In one embodiment, the spacer SPC may be disposed on some of the pixel defining layers PDL. That is, in a plan view, the spacer SPC may overlap with some of the pixel defining layers PDL, and may not overlap with other of the pixel defining layers PDL.

[0101] The common electrode CE may be disposed on the light emitting layer EL, the pixel defining layer PDL, and the spacer SPC, and the capping layer CPL may be disposed on the common electrode CE.

[0102] The light blocking pattern BP may be disposed between the capping layer CPL and the second substrate SUB2. Specifically, the light blocking pattern BP may be disposed on a surface S1 of the second substrate SUB2 facing the first substrate SUB1.

[0103] In one embodiment, the light blocking pattern BP may be provided in plurality. In one embodiment, some of the light blocking patterns BP may overlap with each of the pixel defining layer PDL and the spacer SPC in a plan view. Other light blocking patterns BP of the light blocking patterns BP may overlap with the pixel defining layer PDL and may not overlap with the spacer SPC. That is, the spacer SPC may overlap with at least one of the light blocking patterns BP in a plan view.

[0104] In other words, some of the light blocking patterns BP may contact each of the surface S1 of the second substrate SUB2 and the capping layer CPL. Other of the light blocking patterns BP may contact the surface S1 of the second substrate SUB2 and may not contact the capping layer CPL.

[0105] In the display device 10 according to an embodiment of the present disclosure, a light blocking pattern BP overlapping with the pixel defining layer PDL in a plan view may be provided on the second substrate SUB2. The light blocking pattern BP may block incident light L1 incident from the outside and reflected light L2 in which the incident light L1 is reflected by the pixel defining layer PDL. In addition, the thickness of the space SP between the first substrate SUB1 and the second substrate SUB2 may be increased. Accordingly, the coherence may be reduced, and the rainbow color shift phenomenon visually recognized at a side viewing angle may be effectively improved.

[0106] Figure 6 is a plan view illustrating a display device according to another embodiment of the present disclosure. Figure 7 It is along Figure 6 A cross-sectional view taken along line II-II'.

[0107] In the following, the references will be omitted or simplified. Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 The description of the display device 10 overlaps the description.

[0108] refer to Figure 6 , the display device 20 may include a display area DA and a non-display area NDA. The display area DA may be an area where an image is displayed, and the non-display area NDA may be an area where an image is not displayed. A plurality of pixels PX may be disposed in the display area DA, and a driver for driving the plurality of pixels PX may be disposed in the non-display area NDA.

[0109] refer to Figure 6 and Figure 7 The display device 20 may include a first substrate SUB1, a buffer layer BUF, a transistor TR, a gate insulating layer GI, an interlayer insulating layer ILD, a via insulating layer VIA, a pixel defining layer PDL, a light emitting element LD, a spacer SPC, a capping layer CPL, a transmissive pattern TP, a light blocking pattern BP and a second substrate SUB2.

[0110] The transistor TR may include an active pattern ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The light emitting element LD may include a pixel electrode PE, a light emitting layer EL, and a common electrode CE.

[0111] A buffer layer BUF, an active pattern ACT, a gate insulating layer GI, a gate electrode GE, an interlayer insulating layer ILD, a source electrode SE, a drain electrode DE, a via insulating layer VIA, a pixel electrode PE, a pixel defining layer PDL, a spacer SPC, a light emitting layer EL, a common electrode CE and a capping layer CPL may be sequentially disposed on the first substrate SUB1.

[0112] In one embodiment, the transmission pattern TP may be disposed between the capping layer CPL and the second substrate SUB2. Specifically, the transmission pattern TP may be disposed on a surface S1 of the second substrate SUB2 facing the first substrate SUB1. In one embodiment, for example, the transmission pattern TP may contact each of the surface S1 of the second substrate SUB2 and the capping layer CPL. In addition, the transmission pattern TP may overlap each of the pixel defining layer PDL and the spacer SPC in a plan view. The transmission pattern TP may be used to maintain a space SP between the first substrate SUB1 and the second substrate SUB2 together with the spacer SPC.

[0113] The transmission pattern TP may transmit light. The transmission pattern TP may transmit incident light L1 incident from the outside through the second substrate SUB2. In addition, the transmission pattern TP may transmit light L4 emitted from the light emitting element LD to the outside. In an embodiment, the transmission pattern TP may include a transparent organic material.

[0114] The light blocking pattern BP may be disposed on the transmission pattern TP. In one embodiment, the light blocking pattern BP may define an opening OP that accommodates at least a portion of the spacer SPC. The light blocking pattern BP may cover at least a portion of the side surface of the spacer SPC accommodated in the opening OP. That is, at least a portion of each of the spacer SPC, the common electrode CE disposed on the spacer SPC, and the capping layer CPL disposed on the spacer SPC may fill the opening OP. In addition, the opening OP may expose at least a portion of the transmission pattern TP. The transmission pattern TP and the capping layer CPL may contact each other in the opening OP.

[0115] The light blocking pattern BP may include a light blocking material. In one embodiment, for example, the light blocking pattern BP may include a black matrix. The light blocking pattern BP may absorb or block incident light L1 incident from the outside through the second substrate SUB2 and reflected light L2 where the incident light L1 is reflected by the pixel defining layer PDL.

[0116] Figure 8 is an example Figure 7 A cross-sectional view of another example of .

[0117] refer to Figure 6 and Figure 8 The display device 20 may include a first substrate SUB1, a buffer layer BUF, a transistor TR, a gate insulating layer GI, an interlayer insulating layer ILD, a via insulating layer VIA, a pixel defining layer PDL, a light emitting element LD, a spacer SPC, a capping layer CPL, a transmissive pattern TP, a light blocking pattern BP and a second substrate SUB2.

[0118] However, in addition to the spacer SPC, reference Figure 8The display device 20 described can be used with reference Figure 7 The display device 20 described is substantially the same or similar. Hereinafter, redundant descriptions will be omitted or simplified.

[0119] A buffer layer BUF, an active pattern ACT, a gate insulating layer GI, a gate electrode GE, an interlayer insulating layer ILD, a source electrode SE, a drain electrode DE, a via insulating layer VIA, a pixel electrode PE, a pixel defining layer PDL and a light emitting layer EL may be sequentially disposed on the first substrate SUB1.

[0120] The spacer SPC may be disposed on the pixel defining layer PDL. In one embodiment, the spacer SPC may be disposed on some of the pixel defining layers PDL. That is, in a plan view, the spacer SPC may overlap with some of the pixel defining layers PDL, and may not overlap with other of the pixel defining layers PDL.

[0121] The common electrode CE may be disposed on the light emitting layer EL, the pixel defining layer PDL, and the spacer SPC, and the capping layer CPL may be disposed on the common electrode CE.

[0122] The transmissive pattern TP may be disposed between the capping layer CPL and the second substrate SUB2. Specifically, the transmissive pattern TP may be disposed on a surface S1 of the second substrate SUB2 facing the first substrate SUB1.

[0123] In an embodiment, some of the transmission patterns TP may overlap each of the pixel defining layer PDL and the spacer SPC in a plan view. Other of the transmission patterns TP may overlap the pixel defining layer PDL and may not overlap the spacer SPC in a plan view. That is, the spacer SPC may overlap at least one of the transmission patterns TP.

[0124] In other words, some of the transmissive patterns TP may contact each of the surface S1 of the second substrate SUB2 and the capping layer CPL. Other of the transmissive patterns TP may contact the surface S1 of the second substrate SUB2 and may not contact the capping layer CPL.

[0125] The light blocking pattern BP may be disposed on the transmissive pattern TP. The light blocking pattern BP may define an opening OP that accommodates at least a portion of the spacer SPC. That is, the opening OP of the light blocking pattern BP may accommodate at least a portion of the spacer SPC that overlaps with the transmissive pattern TP in a plan view. In other words, the spacer SPC may be accommodated in the opening OP of at least one of the light blocking patterns BP. The light blocking pattern BP may cover at least a portion of the side surface of the spacer SPC accommodated in the opening OP.

[0126] In addition, the opening OP of the light blocking pattern BP may expose at least a portion of the transmissive pattern TP. When the transmissive pattern TP and the spacer SPC overlap each other in a plan view, the transmissive pattern TP and the capping layer CPL may contact each other in the opening OP.

[0127] In the display device 20 according to an embodiment of the present disclosure, a transmissive pattern TP and a light blocking pattern BP overlapping the pixel defining layer PDL in a plan view may be provided on the second substrate SUB2. Since the transmissive pattern TP transmits the light L4 emitted from the light emitting element LD, the viewing angle may be ensured when the light emitting element LD emits light. In addition, since the light blocking pattern BP blocks the incident light L1 and the reflected light L2, the rainbow color shift phenomenon visually recognized at a side viewing angle may be effectively improved.

[0128] Fig. 9 is a cross-sectional view illustrating a display device according to another embodiment of the present disclosure. For example, Fig. 9 Can correspond to Figure 7 Cross-sectional view of .

[0129] In the following, the references will be omitted or simplified. Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 The description of the display device 10 overlaps the description.

[0130] refer to Fig. 9 The display device 30 may include a first substrate SUB1, a buffer layer BUF, a transistor TR, a gate insulating layer GI, an interlayer insulating layer ILD, a via insulating layer VIA, a pixel defining layer PDL, a spacer SPC, a light emitting element LD, a capping layer CPL, a transmissive pattern TP, a light blocking pattern BP and a second substrate SUB2.

[0131] The transistor TR may include an active pattern ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The light emitting element LD may include a pixel electrode PE, a light emitting layer EL, and a common electrode CE.

[0132] The transmissive pattern TP may be disposed between the capping layer CPL and a surface S1 of the second substrate SUB2 facing the first substrate SUB1. In an embodiment, the transmissive pattern TP may overlap each of the pixel defining layer PDL and the spacer SPC in a plan view.

[0133] The light blocking pattern BP may be disposed on the capping layer CPL. The light blocking pattern BP may overlap the pixel defining layer PDL in a plan view. The light blocking pattern BP may include a first light blocking pattern BP1 and a second light blocking pattern BP2.

[0134] In a plan view, the first light blocking pattern BP1 may overlap the pixel defining layer PDL, and may not overlap the spacer SPC.

[0135] The second light blocking pattern BP2 may be disposed on the transmissive pattern TP. The second light blocking pattern BP2 may overlap each of the pixel defining layer PDL and the spacer SPC in a plan view. The second light blocking pattern BP2 may define an opening OP that accommodates at least a portion of the spacer SPC and exposes at least a portion of the transmissive pattern TP. The second light blocking pattern BP2 may cover at least a portion of a side surface of the spacer SPC accommodated in the opening OP.

[0136] The light blocking pattern BP may include an organic light blocking material or an inorganic light blocking material. The light blocking pattern BP may absorb or block incident light L1 incident from the outside through the second substrate SUB2. In addition, the light blocking pattern BP may absorb or block reflected light L2 where the incident light L1 is reflected by the pixel defining layer PDL.

[0137] Fig.10 is an example Fig. 9 A cross-sectional view of another example of .

[0138] refer to Fig.10 The display device 30 may include a first substrate SUB1, a buffer layer BUF, a transistor TR, a gate insulating layer GI, an interlayer insulating layer ILD, a via insulating layer VIA, a pixel defining layer PDL, a light emitting element LD, a capping layer CPL, a low reflective layer LRL and a second substrate SUB2.

[0139] However, in addition to the low reflection layer LRL, reference Fig.10 The display device 30 described can be used with reference Fig. 9 The display device 30 described is substantially the same or similar. Hereinafter, redundant descriptions will be omitted or simplified.

[0140] In one embodiment, the low reflection layer LRL may be disposed between the capping layer CPL and the second substrate SUB2. Specifically, the low reflection layer LRL may be disposed on a surface S1 of the second substrate SUB2 facing the first substrate SUB1. In one embodiment, for example, the low reflection layer LRL may have a multilayer structure in which a plurality of layers are stacked. The low reflection layer LRL may reduce the reflectivity of the incident light L1 incident from the outside.

[0141] In the display device 30 according to an embodiment of the present disclosure, at least one of the light blocking pattern BP and the low reflection layer LRL may be disposed between the first substrate SUB1 and the second substrate SUB2. Accordingly, the rainbow color shift phenomenon visually recognized at a side viewing angle may be effectively improved.

[0142] Fig.11 is a view schematically illustrating the exterior of a vehicle according to an embodiment of the present disclosure. Fig.12 is a schematic illustration Fig.11 View of the interior of the vehicle.

[0143] refer to Fig.11 and Fig.12 The vehicle 1000 may be a device that moves a transport object such as a person, an object, an animal, etc. from a starting point to a destination. In one embodiment, for example, the vehicle 1000 may include a three-wheeled or four-wheeled vehicle, a construction machine, a two-wheeled vehicle, a motor device, a bicycle, a train running on a track, a ship running on the sea or a river, etc.

[0144] The vehicle 1000 may include a body 100 and a chassis.

[0145] The body 100 may form the exterior of the vehicle 1000 and may define an interior space where the driver and passengers are located. In one embodiment, for example, the body 100 may include a front window glass 200, a hood, a roof, a rear panel, a trunk, etc. The chassis may include a mechanical device for driving. In one embodiment, for example, the chassis may include a generator, a power transmission device, a drive device, a steering device, a brake device, a suspension device, a transmission device, a fuel device, etc.

[0146] The vehicle 1000 may include an instrument cluster 310 , a center instrument panel 320 , a passenger seat instrument panel 330 , and a display device 40 .

[0147] The instrument cluster 310 may be located in front of the steering wheel. A tachometer, a speedometer, a coolant temperature gauge, a fuel gauge, a direction change indicator light, a high beam indicator light, warning lights (e.g., a seat belt warning light, a door open warning light, an engine oil warning light, a fuel shortage warning light), an odometer, an automatic shift selector lever indicator light, etc. may be provided on the instrument cluster 310.

[0148] The center instrument panel 320 may be adjacent to one side of the instrument cluster 310 . An audio device, an air conditioner, a control panel having a plurality of buttons for adjusting a heater of a seat, and the like may be provided on the center instrument panel 320 .

[0149] The passenger seat instrument panel 330 may be adjacent to one side of the center instrument panel 320. That is, the passenger seat instrument panel 330 may be spaced apart from the instrument cluster 310 with the center instrument panel 320 interposed therebetween. In one embodiment, the instrument cluster 310 may correspond to a driver's seat setting, and the passenger seat instrument panel 330 may correspond to a passenger's seat setting.

[0150] The display device 40 may be disposed in the internal space. The display device 40 may correspond to the reference Figures 1 to 10 That is, the display device 40 may have the same Figures 1 to 10 The display devices 10 , 20 , and 30 described herein have substantially the same or similar structures.

[0151] The display device 40 may be provided on at least one of the instrument cluster 310, the center instrument panel 320, and the passenger seat instrument panel 330. In other words, the display device 40 may include at least one of a first display device 41 provided on the instrument cluster 310, a second display device 42 provided on the center instrument panel 320, and a third display device 43 provided on the passenger seat instrument panel 330. However, the present disclosure is not limited thereto, and the arrangement of the display device 40 may be variously changed. Alternatively, the display device 40 may be provided on other configurations of the vehicle 1000, such as the front window glass 200, an interior mirror, and the like.

[0152] In one embodiment, for example, the first display device 41 may be provided on the instrument cluster 310 to provide the driver with vehicle information, speed information, etc. The second display device 42 may be provided on the center instrument panel 320 to provide map information, vehicle setting information, etc. The third display device 43 may be provided on the passenger seat instrument panel 330 to provide entertainment information, etc. to the passenger. However, the present disclosure is not limited thereto, and the information provided by the first display device 41, the second display device 42, and the third display device 43 may be changed variously.

[0153] In one embodiment, the first display device 41, the second display device 42, and the third display device 43 can minimize the light traveling toward the front window glass 200 so as not to interfere with the driver's front driving field of view. In addition, at least one of the first display device 41, the second display device 42, and the third display device 43 can be switched between a wide viewing angle mode and a narrow viewing angle mode.

[0154] exist Fig.12In the embodiment, the first display device 41, the second display device 42 and the third display device 43 are illustrated as being spaced apart from each other, but the present disclosure is not limited thereto. Alternatively, in another embodiment, the first display device 41, the second display device 42 and the third display device 43 may be connected to each other.

[0155] The present disclosure can be applied to various display devices. For example, the present disclosure is applicable to various display devices, such as display devices for vehicles, ships and aircraft, portable communication devices, display devices for display or information transmission, medical display devices, etc.

[0156] The foregoing is an illustration of the embodiments and should not be construed as limiting them. Although some embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications may be made in the embodiments without substantially departing from the novel teachings and advantages of the present invention. Accordingly, all such modifications are intended to be included within the scope of the present invention as defined in the claims. Therefore, it should be understood that the foregoing is an illustration of various embodiments and should not be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A display device, include: a first substrate; A pixel electrode, disposed on the first substrate; a pixel defining layer, disposed on the first substrate and covering at least a portion of the pixel electrode; a second substrate disposed on the pixel defining layer and spaced apart from the first substrate and the pixel defining layer to define a space between the second substrate and the pixel defining layer; as well as A light blocking pattern is disposed on a surface of the second substrate facing the first substrate and overlaps the pixel defining layer in a plan view.

2. The display device according to claim 1, wherein a distance between an edge of a surface of the pixel defining layer facing the second substrate and an edge of a surface of the light blocking pattern facing the second substrate satisfies the following equation 1: Wherein X is the distance between the edge of the surface of the pixel defining layer and the edge of the surface of the light blocking pattern, D is the distance between the surface of the pixel defining layer and the surface of the second substrate, n1 is the refractive index of the space, n2 is the refractive index of the second substrate, n3 is the refractive index of the external air, and θ is the viewing angle.

3. The display device according to claim 2, wherein a width of the surface of the light blocking pattern satisfies the following equation 2: W = G-2X, Wherein W is the width of the surface of the light blocking pattern, and G is the width of the surface of the pixel defining layer.

4. The display device according to claim 1, further comprising: include: A spacer is disposed between the pixel defining layer and the light blocking pattern. 5 . The display device of claim 4 , wherein a sum of a thickness of the light blocking pattern and a thickness of the spacer is greater than 3 μm and less than or equal to 20 μm. 6 . The display device of claim 4 , wherein the light blocking pattern is provided in plural, and the spacer overlaps at least one of the plurality of light blocking patterns in the plan view. 7 . The display device of claim 4 , wherein a maximum width of the light blocking pattern is greater than a width of the spacer.

8. The display device according to claim 4, further comprising: include: A light-emitting layer is arranged on the pixel electrode; A common electrode, disposed on the light emitting layer, the pixel defining layer and the spacer; as well as The capping layer is arranged on the common electrode. 9 . The display device of claim 1 , wherein the light blocking pattern comprises a black matrix.

10. The display device according to claim 1, further comprising: include: A sealing member is disposed between the first substrate and the second substrate along an edge of each of the first substrate and the second substrate and couples the first substrate and the second substrate. The display device according to claim 1 , wherein the second substrate comprises a glass substrate. The display device according to claim 1 , wherein the space is an empty space. The display device according to claim 1 , wherein the space is filled with a filler.

14. A vehicle, include: The body of the vehicle defines the interior space; as well as A display device is arranged in the internal space. The display device comprises: a first substrate; A pixel electrode, disposed on the first substrate; a pixel defining layer, disposed on the first substrate and covering at least a portion of the pixel electrode; A spacer, disposed on the pixel defining layer; a second substrate disposed on the spacer and spaced apart from the first substrate and the spacer to define a space between the second substrate and the pixel defining layer; a transmissive pattern disposed on a surface of the second substrate facing the first substrate and overlapping the pixel defining layer in a plan view; and A light blocking pattern is disposed on the transmissive pattern and defines an opening that receives at least a portion of the spacer. 15 . The vehicle of claim 14 , wherein the light blocking pattern covers at least a portion of a side surface of the spacer. 16 . The vehicle according to claim 14 , wherein the light blocking pattern is provided in plural, and the spacer is received in the opening of at least one of the plurality of the light blocking patterns.

17. The vehicle of claim 14, wherein the transmissive pattern comprises a transparent organic material.

18. The vehicle of claim 14, wherein the light blocking pattern comprises a black matrix.

19. The vehicle of claim 14, wherein the display device further include: A sealing member is disposed between the first substrate and the second substrate along an edge of each of the first substrate and the second substrate and couples the first substrate and the second substrate.

20. The vehicle of claim 14, wherein the second substrate comprises a glass substrate.

21. The vehicle of claim 14, wherein the space between the second substrate and the pixel defining layer is an empty space.

22. The vehicle of claim 14, wherein the space between the second substrate and the pixel defining layer is filled with a filler.

23. The vehicle of claim 14, further comprising: include: Instrument cluster; a center instrument panel adjacent to said instrument cluster; as well as A passenger seat instrument panel, adjacent to said center instrument panel, The display device is disposed on at least one of the instrument cluster, the center instrument panel, and the passenger seat instrument panel.

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