A SPDK architecture multi-control storage expansion method and device based on memory sharing

Abstract

The embodiments of this specification disclose a method and device for multi-controller storage expansion based on memory sharing in an SPDK architecture. The method includes building an interconnection link with other controllers; creating an original circular queue in the SPDK process, and mapping a mapped circular queue corresponding to the original circular queue in the SPDK process of the other controllers based on the interconnection link; and traversing and processing the queue data in the original circular queue. The embodiments of this specification do not require the support of upper-layer communication protocols such as FC, ISCSI, and NVMe‑oF, nor do they require conversion through block devices. The SPDK process directly operates the opposite end, that is, the circular queue mapped by the other controllers, and the SPDK process of the opposite end is treated as its own thread for processing, thereby realizing the transformation of communication between processes into communication between threads, reducing resource consumption, improving communication speed, and extending the operation of SPDK from single-controller operation to multi-controller operation.

Description

Technical Field

[0001] One or more embodiments of this specification relate to communication technology, and more particularly, to a method and device for multi-controller storage expansion in an SPDK architecture based on memory sharing. Background Art

[0002] The Storage Performance Development Kit (SPDK) provides a series of high-performance, scalable, user-mode tools and libraries. SPDK's current application scenario is primarily for block storage. It is driven by a polling model, using a ring queue to process requests between threads. A requesting thread submits a request to the queue and then continues to perform other tasks. The processing thread can continuously or periodically poll the queue to check for new requests and process them. Current storage systems have evolved from single-controller systems to multi-controller systems. However, SPDK software currently runs only on a single machine. Consequently, communication between controllers in the SPDK architecture is limited to protocols such as FC, iSCSI, and NVMe-oF. These protocols map storage devices from one controller to another, allowing the mapped storage devices to be used as block devices. These methods require processing at the block device layer, increasing complexity, cost, transmission speed, and I / O latency. This also results in poor interoperability between SPDK software running across multiple controllers. Summary of the Invention

[0003] To solve the above problems, one or more embodiments of this specification describe a method and device for multi-controller storage expansion in an SPDK architecture based on memory sharing.

[0004] According to a first aspect, a method for multi-controller storage expansion in an SPDK architecture based on memory sharing is provided, the method comprising:

[0005] Building interconnection links with other controllers based on a high-speed interconnection protocol that supports memory sharing, wherein the interconnection links are used to perform memory mapping sharing for multiple controllers;

[0006] Creating an original circular queue in the SPDK process, mapping the mapped circular queue corresponding to the original circular queue in the SPDK processes of other controllers based on the interconnection link, and sharing queue data of the mutually matched original circular queue and mapped circular queue in real time;

[0007] The queue data in the original circular queue is traversed and processed.

[0008] Preferably, the high-speed interconnection protocol is a non-transparent bridge protocol or a computational fast link protocol.

[0009] Preferably, the original ring queue is only provided with a message dequeueing permission, and the mapped ring queue is only provided with a message enqueueing permission.

[0010] Preferably, after creating the original ring queue in the SPDK process, the method further includes:

[0011] Initialize the original ring queue.

[0012] Preferably, the traversing and processing the queue data in the original ring queue includes:

[0013] The original circular queue is traversed in a continuous polling manner. When queue data exists in the original circular queue, the queue data is taken out from the original circular queue and processed.

[0014] Preferably, the method further comprises:

[0015] When a data write instruction is detected, a target mapping circular queue and a target write row corresponding to the data to be written are determined, and the data to be written is written to the target write row of the target mapping circular queue.

[0016] Preferably, the creating of the original circular queue in the SPDK process and mapping the mapped circular queue corresponding to the original circular queue in the SPDK processes of the remaining controllers based on the interconnection link include:

[0017] When there are more than two remaining controllers that need to share memory, the same number of original circular queues are created in the SPDK process based on the number of remaining controllers that need to share memory, and mapped circular queues corresponding to different original circular queues are mapped in the SPDK process of each remaining controller based on the interconnection link.

[0018] According to a second aspect, a multi-controller storage expansion device based on SPDK architecture and memory sharing is provided, the device comprising:

[0019] A construction module, configured to construct an interconnection link with other controllers based on a high-speed interconnection protocol supporting memory sharing, wherein the interconnection link is used to perform memory mapping sharing for multiple controllers;

[0020] A mapping module is used to create an original circular queue in the SPDK process, and map the mapped circular queue corresponding to the original circular queue in the SPDK processes of other controllers based on the interconnection link, so that the queue data of the original circular queue and the mapped circular queue that match each other are shared in real time;

[0021] The traversal module is used to traverse and process the queue data in the original ring queue.

[0022] According to a third aspect, there is provided an electronic device comprising a processor and a memory;

[0023] The processor is connected to the memory;

[0024] The memory is used to store executable program code;

[0025] The processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the steps of the method provided in the first aspect or any possible implementation manner of the first aspect.

[0026] According to a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, and the computer-readable storage medium stores instructions, which, when the instructions are executed on a computer or a processor, enable the computer or the processor to execute the method provided in the first aspect or any possible implementation of the first aspect.

[0027] The method and apparatus provided in the embodiments of this specification do not require support from upper-layer communication protocols such as FC, iSCSI, and NVMe-oF, nor do they require conversion through block devices. Instead, the peer end is directly operated through the SPDK process, that is, the circular queues mapped by the other controllers are operated, and the SPDK process of the peer end is treated as its own thread for processing. This converts inter-process communication into inter-thread communication, reduces resource consumption, improves communication speed, and expands the operation of SPDK from single-controller operation to multi-controller operation, thereby realizing multi-controller storage expansion under the SPDK architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 This is a flowchart of a multi-controller storage expansion method in an SPDK architecture based on memory sharing in one embodiment of this specification.

[0030] Figure 2 This is a schematic diagram of the architecture of the interconnection link in one embodiment of this specification.

[0031] Figure 3 This is a schematic diagram of the principle of the mapping process of the original ring queue in one embodiment of this specification.

[0032] Figure 4This is a structural diagram of a multi-controller storage expansion device based on SPDK architecture with shared memory in one embodiment of this specification.

[0033] Figure 5 It is a structural diagram of an electronic device in one embodiment of this specification. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application.

[0035] In the following introduction, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The following introduction provides multiple embodiments of the present application. Different embodiments can be replaced or combined, so the present application can also be considered to include all possible combinations of the same and / or different embodiments described. Therefore, if one embodiment includes features A, B, and C, and another embodiment includes features B and D, then the present application should also be considered to include embodiments containing one or more of all other possible combinations of A, B, C, and D, even though the embodiment may not be clearly described in the following text.

[0036] The following description provides examples and does not limit the scope, applicability, or examples set forth in the claims. Changes may be made to the function and arrangement of the elements described without departing from the scope of the present application. Various examples may appropriately omit, replace, or add various processes or components. For example, the described method may be performed in an order different from the order described, and various steps may be added, omitted, or combined. In addition, features described in some examples may be combined in other examples.

[0037] See also Figure 1 , Figure 1 This is a flow chart of a method for multi-controller storage expansion in an SPDK architecture based on memory sharing provided in an embodiment of the present application. In this embodiment of the present application, the method includes:

[0038] S101. Build interconnection links with other controllers based on a high-speed interconnection protocol that supports memory sharing.

[0039] The interconnection link is used to perform memory mapping sharing for multiple controllers.

[0040] The execution entity of this application may be a controller.

[0041] In the embodiments of this specification, there are multiple controllers in a multi-control system. In order to realize multi-control storage expansion under the SPDK architecture, the controller first needs to directly build an interconnection link with the remaining controllers through a high-speed interconnection protocol that supports memory sharing, so as to realize memory mapping sharing between multiple controllers through the interconnection link. High-speed protocols are commonly used in the storage field. Compared with upper-layer communication protocols such as FC, ISCSI, and NVMe-oF, they have the advantages of low overhead and fast speed. The communication connection constructed by the memory mapping sharing method allows the controllers to be directly connected through the interconnection link, without the support of the upper-layer communication protocol or the conversion of block devices, which is more efficient. At the same time, such a memory sharing mapping method can also enable the controller to directly operate the data mapped by the other controllers through the SPDK process, so as to treat the SPDK processes of the other controllers as their own threads, thereby converting the communication between processes into communication between threads, so that the operation of SPDK is expanded from a single controller to multiple controllers. High-speed interconnect protocols that support memory sharing include Non-Transparent Bridge (NTB), Compute Express Link (CXL), and Unified Port Interface (UPI). The remaining controllers refer to controllers other than the controller itself in a multi-controller system.

[0042] In one possible implementation, the high-speed interconnection protocol is a non-transparent bridge protocol or a computational fast link protocol.

[0043] In the embodiments of this specification, NTB (Non-Transparent Bridge) technology is derived from the standard PCIe rules. Two hosts can forward PCIe transactions from one side of NTB to the other side through the address translation mechanism of NTB. This function enables communication between different hosts. With the help of the characteristics of NTB, the memory of other machines can also be mapped to this end to achieve memory sharing. CXL is a high-speed data transmission protocol that allows fast and reliable data transmission between different components within a computer system. It aims to solve bottleneck problems in high-performance computing, including memory capacity, memory bandwidth, and I / O latency. CXL technology not only provides high-speed transmission, but also supports memory sharing and virtualization, making the collaboration between controllers closer and more efficient. The interconnection link architecture built according to the non-transparent bridge protocol or the computing fast link protocol is as follows: Figure 2 As shown in Figure 1, multiple controllers can be interconnected using PCIe NTB links or CXL links. If PCIe NTB links are used, each controller can access the memory of another controller via NTB. If CXL links are used, multiple controllers can simultaneously access the shared memory attached to the CXL link.

[0044] S102: Create an original circular queue in the SPDK process, and map a mapped circular queue corresponding to the original circular queue in the SPDK processes of other controllers based on the interconnection link.

[0045] The queue data of the original ring queue and the mapped ring queue that match each other are shared in real time.

[0046] In the embodiments of this specification, the controller will create an original circular queue in the SPDK process, and then share the original circular queue mapping created by itself to the other controllers through the memory sharing mechanism of the interconnection link, so that the other controllers will also have a mapped circular queue corresponding to the original circular queue of this controller. They match each other, that is, the queue data of the original circular queue and the mapped circular queue, which essentially belong to a circular queue, are shared in real time through the interconnection link, so that the other controllers can perform operations such as reading and writing on the mapped circular queue in their own SPDK processes, thereby realizing the process of operating the original circular queue of this controller with the other controllers. The specific principle diagram of this process is shown in the figure. Figure 3 shown.

[0047] In one possible implementation, the original ring queue is only provided with a message dequeueing permission, and the mapped ring queue is only provided with a message enqueueing permission.

[0048] In the embodiments of this specification, in order to prevent the current controller and another controller mapped with a mapped circular queue from reading and writing the same circular queue at the same time, that is, conflicts caused by reading and writing the same block of memory at the same time, only message dequeue permissions will be set in the original circular queue, and only message enqueue permissions will be set in the mapped circular queue. In this way, any controller can only read data from the original circular queue in its own SPDK, and write data from the mapped circular queue in its own SPDK.

[0049] In one possible implementation, creating an original circular queue in the SPDK process, and mapping a mapped circular queue corresponding to the original circular queue in the SPDK processes of other controllers based on the interconnection link includes:

[0050] When there are more than two remaining controllers that need to share memory, the same number of original circular queues are created in the SPDK process based on the number of remaining controllers that need to share memory, and mapped circular queues corresponding to different original circular queues are mapped in the SPDK process of each remaining controller based on the interconnection link.

[0051] In the embodiments of this specification, under normal circumstances, a primary circular queue will only be matched with one mapped circular queue, that is, a primary circular queue will only form a mapped circular queue in one remaining controller for memory sharing. If a certain type of circular queue of this controller needs to be shared with multiple controllers, the controller will generate multiple primary circular queues of the same type based on the number of remaining controllers to be shared, and map a mapped circular queue in each remaining controller using a different primary circular queue, to ensure the independence of the same type of mapped circular queues in different remaining controllers and prevent them from interfering with each other.

[0052] In one possible implementation, after creating the original ring queue in the SPDK process, the method further includes:

[0053] Initialize the original ring queue.

[0054] In the embodiments of this specification, after creating the original circular queue, it must first be initialized. The specific initialization process may include allocating memory space, setting the queue size, initializing control variables, marking the queue state, setting boundary conditions, and initializing auxiliary variables. Allocating memory space refers to allocating sufficient memory to store the circular queue's data structure, typically including the array of elements in the queue and control variables that manage the queue state (such as the head pointer and tail pointer). Setting the queue size refers to determining the queue's maximum capacity, i.e., the maximum number of elements the queue can store. Typically, the queue size should be a power of 2, thereby simplifying the circular queue management logic through bit operations. Initializing control variables refers to setting the initial values ​​of the queue's head pointer and tail pointer. Marking the queue state refers to initializing the queue's status flags, such as whether it is empty or full. Setting boundary conditions is used to implement wraparound logic for the queue's head and tail pointers after they reach the end of the queue. Initializing auxiliary variables refers to initializing a counter that records the current number of elements in the queue.

[0055] S103: traverse and process the queue data in the original ring queue.

[0056] In the embodiments of this specification, through the above settings, each controller can operate the circular queues of other controllers to achieve mutual communication between controllers. During the communication process, corresponding data will be generated in the circular queue. The controller will traverse the original circular queue to determine the queue data therein and process the queue data in a unified manner. The traversal process can be selected according to actual conditions, either regular traversal or irregular continuous real-time traversal. The former may cause lag in data processing and have a higher latency, so the latter is generally preferred.

[0057] In one embodiment, the traversing and processing queue data in the original ring queue includes:

[0058] The original circular queue is traversed in a continuous polling manner. When queue data exists in the original circular queue, the queue data is taken out from the original circular queue and processed.

[0059] In the embodiments of this specification, the controller continuously traverses the original circular queue in a polling manner. During the traversal of the original circular queue, if queue data is found in the queue, the queue data is first dequeued, that is, the queue data is taken out. Only after the queue data is taken out will the queue data be processed, rather than being processed directly in the queue. This also avoids the residual of processed data in the queue.

[0060] In one embodiment, the method further comprises:

[0061] When a data write instruction is detected, a target mapping circular queue and a target write row corresponding to the data to be written are determined, and the data to be written is written to the target write row of the target mapping circular queue.

[0062] In the embodiments of this specification, if a storage system has more than two controllers, the SPDK process of a controller will contain different mapping ring queues mapped from different controllers. When a user writes data to a controller, the controller will determine the mapping ring queue to which the data to be written should be written based on the data write instruction, that is, determine the target mapping ring queue, and also determine the target write row, that is, the specific location in the target mapping ring queue.

[0063] The following will be combined with the Figure 4 , the SPDK architecture multi-control storage expansion device based on memory sharing provided by the embodiment of the present application is introduced in detail. Figure 4 The SPDK architecture multi-control storage expansion device based on memory sharing shown is used to execute this application Figure 1 For the convenience of explanation, only the part related to the embodiment of the present application is shown. For the specific technical details not disclosed, please refer to the present application. Figure 1 The embodiment shown.

[0064] See Figure 4 , Figure 4 This is a schematic diagram of the structure of a multi-control storage expansion device based on SPDK architecture with memory sharing provided by an embodiment of the present application. Figure 4 As shown, the device includes:

[0065] A construction module 401 is configured to construct an interconnection link with other controllers based on a high-speed interconnection protocol supporting memory sharing, wherein the interconnection link is used to perform memory mapping sharing for multiple controllers;

[0066] A mapping module 402 is configured to create an original circular queue in the SPDK process, and map a mapped circular queue corresponding to the original circular queue in the SPDK processes of other controllers based on the interconnection link, so that queue data of the original circular queue and the mapped circular queue that match each other are shared in real time;

[0067] The traversal module 403 is used to traverse and process the queue data in the original ring queue.

[0068] In one possible implementation, the high-speed interconnection protocol is a non-transparent bridge protocol or a computational fast link protocol.

[0069] In one possible implementation, the original ring queue is only provided with a message dequeueing permission, and the mapped ring queue is only provided with a message enqueueing permission.

[0070] In one embodiment, the mapping module 402 is further configured to:

[0071] Initialize the original ring queue.

[0072] In one embodiment, the traversal module 403 is specifically configured to:

[0073] The original circular queue is traversed in a continuous polling manner. When queue data exists in the original circular queue, the queue data is taken out from the original circular queue and processed.

[0074] In one embodiment, the device further comprises:

[0075] The writing module is configured to determine a target mapping circular queue and a target writing row corresponding to the data to be written when a data writing instruction is detected, and write the data to be written into the target writing row of the target mapping circular queue.

[0076] In one embodiment, the mapping module 402 is specifically configured to:

[0077] When there are more than two remaining controllers that need to share memory, the same number of original circular queues are created in the SPDK process based on the number of remaining controllers that need to share memory, and mapped circular queues corresponding to different original circular queues are mapped in the SPDK process of each remaining controller based on the interconnection link.

[0078] Those skilled in the art will clearly understand that the technical solutions of the embodiments of the present application can be implemented with the help of software and / or hardware. "Unit" and "module" in this specification refer to software and / or hardware that can independently perform or cooperate with other components to perform specific functions, where the hardware can be, for example, a field-programmable gate array (FPGA) or an integrated circuit (IC).

[0079] Each processing unit and / or module in the embodiments of the present application may be implemented by an analog circuit that implements the functions described in the embodiments of the present application, or may be implemented by software that executes the functions described in the embodiments of the present application.

[0080] See also Figure 5 , which shows a schematic diagram of the structure of an electronic device involved in an embodiment of the present application, the electronic device can be used to implement Figure 1 The method in the embodiment shown. Figure 5 As shown, the electronic device 500 may include: at least one processor 501 , at least one network interface 504 , a user interface 503 , a memory 505 , and at least one communication bus 502 .

[0081] The communication bus 502 is used to implement the connection and communication between these components.

[0082] The user interface 503 may include a display screen (Display) and a camera (Camera). Optionally, the user interface 503 may also include a standard wired interface and a wireless interface.

[0083] The network interface 504 may optionally include a standard wired interface or a wireless interface (such as a WI-FI interface).

[0084] The processor 501 may include one or more processing cores. The processor 501 utilizes various interfaces and circuits to connect various components within the electronic device 500. It executes instructions, programs, code sets, or instruction sets stored in the memory 505, and accesses data stored in the memory 505 to perform various functions and process data within the electronic device 500. Optionally, the processor 501 may be implemented in hardware using at least one of a digital signal processing (DSP), a field-programmable gate array (FPGA), and a programmable logic array (PLA). The processor 501 may integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. The CPU primarily processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing content displayed on the display; and the modem handles wireless communications. It is understood that the modem may also be implemented independently of the processor 501 and implemented on a separate chip.

[0085] Among them, the memory 505 may include a random access memory (RAM) or a read-only memory (Read-Only Memory). Optionally, the memory 505 includes a non-transitory computer-readable storage medium. The memory 505 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 505 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area may store data involved in the above-mentioned various method embodiments, etc. The memory 505 may also be optionally at least one storage device located away from the aforementioned processor 501. As Figure 5 As shown, the memory 505 as a computer storage medium may include an operating system, a network communication module, a user interface module, and program instructions.

[0086] exist Figure 5In the electronic device 500 shown, the user interface 503 is mainly used to provide an input interface for the user and obtain user input data; and the processor 501 can be used to call the memory-shared SPDK architecture multi-controller storage extension application stored in the memory 505 and specifically perform the following operations:

[0087] Building interconnection links with other controllers based on a high-speed interconnection protocol that supports memory sharing, wherein the interconnection links are used to perform memory mapping sharing for multiple controllers;

[0088] Creating an original circular queue in the SPDK process, mapping the mapped circular queue corresponding to the original circular queue in the SPDK processes of other controllers based on the interconnection link, and sharing queue data of the mutually matched original circular queue and mapped circular queue in real time;

[0089] The queue data in the original circular queue is traversed and processed.

[0090] The present application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above method. The computer-readable storage medium may include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a DVD, a CD-ROM, a microdrive, a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a DRAM, a VRAM, a flash memory device, a magnetic card or an optical card, a nanosystem (including a molecular memory IC), or any type of medium or device suitable for storing instructions and / or data.

[0091] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0092] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0093] In the several embodiments provided in this application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interface, and the indirect coupling or communication connection of the device or unit can be electrical or other forms.

[0094] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0095] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0096] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a memory and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned memory includes: U disk, read-only memory (ROM), random access memory (RAM), mobile hard disk, magnetic disk, or optical disk, etc., various media that can store program code.

[0097] Those skilled in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be completed by instructing related hardware through a program. The program may be stored in a computer-readable memory, which may include a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0098] The above is only an exemplary embodiment of the present disclosure and cannot be used to limit the scope of the present disclosure. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the specification and practicing the disclosure herein, those skilled in the art will easily think of the implementation scheme of the present disclosure. This application is intended to cover any variation, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the art that are not recorded in the present disclosure. The description and examples are to be regarded as exemplary only, and the scope and spirit of the present disclosure are defined by the claims.

Claims

1. A multi-controller storage expansion method for an SPDK architecture based on memory sharing, characterized in that: The method comprises: Building an interconnection link with other controllers based on a high-speed interconnection protocol supporting memory sharing, wherein the interconnection link is used to perform memory mapping sharing for multiple controllers; An original circular queue is created in the SPDK process, and a mapped circular queue corresponding to the original circular queue is mapped in the SPDK processes of other controllers based on the interconnection link, and queue data of the original circular queue and the mapped circular queue that match each other are shared in real time; Traversing and processing the queue data in the original circular queue; The original ring queue is only provided with a message dequeue permission, and the mapped ring queue is only provided with a message enqueue permission; The traversing and processing the queue data in the original ring queue includes: The original circular queue is traversed in a continuous polling manner, and when queue data exists in the original circular queue, the queue data is taken out from the original circular queue and processed.

2. The method according to claim 1, characterized in that The high-speed interconnection protocol is a non-transparent bridge protocol or a computing fast link protocol.

3. The method according to claim 1, characterized in that After the original ring queue is created in the SPDK process, the following steps are also included: Initialize the original ring queue.

4. The method according to claim 1, characterized in that: The method further comprises: When a data write instruction is detected, a target mapping circular queue and a target write row corresponding to the data to be written are determined, and the data to be written is written to the target write row of the target mapping circular queue.

5. The method according to claim 1, characterized in that The creating of the original ring queue in the SPDK process, and mapping the mapped ring queue corresponding to the original ring queue in the SPDK processes of other controllers based on the interconnection link, includes: When there are more than two remaining controllers that need to share memory, the same number of original circular queues are created in the SPDK process based on the number of remaining controllers that need to share memory, and mapped circular queues corresponding to different original circular queues are respectively mapped in the SPDK process of each remaining controller based on the interconnection link.

6. A multi-control storage expansion device based on SPDK architecture with memory sharing, characterized in that: The device comprises: A construction module, used to construct an interconnection link with other controllers based on a high-speed interconnection protocol supporting memory sharing, wherein the interconnection link is used to perform memory mapping sharing on multiple controllers; A mapping module, used for creating an original circular queue in the SPDK process, mapping a mapped circular queue corresponding to the original circular queue in the SPDK processes of other controllers based on the interconnection link, and sharing queue data of the mutually matching original circular queue and mapped circular queue in real time; A traversal module, used for traversing and processing queue data in the original circular queue; The original ring queue is only provided with a message dequeue permission, and the mapped ring queue is only provided with a message enqueue permission; The traversal module is specifically used for: The original circular queue is traversed in a continuous polling manner, and when queue data exists in the original circular queue, the queue data is taken out from the original circular queue and processed.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

8. A computer-readable storage medium having a computer program stored thereon, wherein the computer-readable storage medium has instructions stored therein, and when the instructions are executed on a computer or a processor, the computer or the processor executes the steps of the method according to any one of claims 1 to 5.

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