LDMOS transistor
By optimizing the body contact region and structural design in the LDMOS transistor, the device failure problem caused by parasitic transistor turning on is solved, the transistor's robustness and reverse recovery ability are improved, and its withstand voltage and breakdown voltage are enhanced.
Patent Information
- Application Number
- CN202411297296.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-14
- Publication Date
- 2024-12-20
AI Technical Summary
The on-off of the parasitic transistor in the LDMOS transistor causes device failure, reducing device reliability, especially when the degree of integration increases and process line width decreases.
By setting the junction depth of the body contact region in the LDMOS transistor is greater than the junction depth of the source region, the base resistance of the surface parasitic transistor is reduced, and the structure of the gate dielectric layer, withstand voltage layer and buffer field plate is optimized to improve the transistor's flexibility Rod and reverse recovery.
It effectively reduces the robustness of the parasitic transistor on the LDMOS transistor, improves the high current capability and reverse recovery capability, and enhances the device's withstand voltage and breakdown voltage.
Smart Images
Figure CN119170646A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and more specifically, to an LDMOS transistor. Background Art
[0002] LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistors are widely used as power devices in power integrated circuits due to their high breakdown voltage and compatibility with CMOS processes. With the increase in integration and the reduction in process line width, the opening of parasitic transistors in LDMOS is an important mechanism for device failure, greatly reducing the reliability of the device. Summary of the invention
[0003] In view of this, an object of the present invention is to provide an LDMOS transistor to solve the problems existing in the prior art.
[0004] According to a first aspect of the present invention, there is provided an LDMOS transistor, comprising: a well region; a body region of a second doping type, extending from the upper surface of the well region to the interior of the well region; a source region of a first doping type and a body contact region of a second doping type, extending from the upper surface of the body region to the interior thereof; a drain region of a first doping type, located in the well region; and a source electrode, in contact with the body contact region and the source region; wherein a junction depth of the body contact region is greater than a junction depth of the source region.
[0005] Preferably, the body contact region at least surrounds a portion of the lower surface of the source region.
[0006] Preferably, the source electrode is located on upper surfaces of the source region and the body contact region.
[0007] Preferably, the source electrode extends from an upper surface of the body contact region to an interior of the body contact region.
[0008] Preferably, the source electrode extends in the body contact region to a depth greater than a junction depth of the source region.
[0009] Preferably, the source electrode contacts a side surface of the source region.
[0010] Preferably, the source includes a trench located in the body contact region and a conductive material located in the trench.
[0011] Preferably, the width of the body contact region along the direction from the source region to the drain region is greater than the width of the source electrode.
[0012] Preferably, it further comprises: a gate dielectric layer adjacent to the source region, located on the upper surface of the well region; and a voltage-resistant layer adjacent to the drain region, located on the well region.
[0013] Preferably, it also includes: a buffer field plate, located between the gate dielectric layer and the voltage-resistant layer, and located on the upper surface of the well region, wherein the thickness of the voltage-resistant layer is greater than the thickness of the buffer field plate, and the thickness of the buffer field plate is greater than the thickness of the gate dielectric layer.
[0014] Preferably, it further comprises a drift region of the first doping type located in the well region, and the drift region is located at least below the voltage-resistant layer.
[0015] Preferably, the voltage-resistant layer protrudes toward the inside of the well region.
[0016] Preferably, the lower surface of the buffer field plate and the lower surface of the gate dielectric layer are located on the same plane parallel to the direction from the source region to the drain region.
[0017] Preferably, a lower surface of the buffer field plate and a lower surface of the gate dielectric layer are higher than a lower surface of the voltage-resistant layer.
[0018] Preferably, the thickness of the gate dielectric layer is set to be 0.95 nm to 9.5 nm.
[0019] Preferably, the method further comprises a gate conductor at least located on the gate dielectric layer.
[0020] Preferably, the device further comprises a field shielding conductor at least located on the voltage-resistant layer.
[0021] Preferably, it further comprises a reduced surface electric field region of the second doping type located in the well region, and the reduced surface electric field region and the drift region are mutually depleted.
[0022] Preferably, a drain electrode is further included, wherein the drain region is located below the voltage-resistant layer, and the drain electrode passes through the voltage-resistant layer and extends to the drain region.
[0023] Preferably, it also includes a shallow trench isolation structure located below the voltage-resistant layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0025] Figure 1 A cross-sectional view showing an LDMOS transistor according to a first embodiment of the present invention;
[0026] Figure 2 A cross-sectional view showing an LDMOS transistor according to a second embodiment of the present invention;
[0027] Figure 3 A cross-sectional view showing an LDMOS transistor according to a third embodiment of the present invention;
[0028] Figure 4 A cross-sectional view showing an LDMOS transistor according to a fourth embodiment of the present invention;
[0029] Figure 5 A cross-sectional view showing an LDMOS transistor according to a fifth embodiment of the present invention;
[0030] Figure 6 A cross-sectional view showing an LDMOS transistor according to a sixth embodiment of the present invention. DETAILED DESCRIPTION
[0031] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.
[0032] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.
[0033] If it is to describe the situation of being directly located on another layer or another region, the expression "A is directly on B" or "A is on B and adjacent to it" will be used in this article. In this application, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.
[0034] Many specific details of the present invention are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.
[0035] Figure 1 A cross-sectional view of an LDMOS transistor according to a first embodiment of the present invention is shown. Figure 1As shown, the LDMOS transistor includes: a well region 102; a body region 104 of a second doping type, extending from the upper surface of the well region 102 to the inside of the well region; a source region 105 of a first doping type and a body contact region 107 of a second doping type, extending from the upper surface of the body region 104 to the inside thereof; a drain region 106 of a first doping type, located in the well region 102; and a source electrode S, in contact with the body contact region 107 and the source region 105, and located on the upper surfaces of the body contact region 107 and the source region 105. The junction depth of the body contact region 107 is greater than the junction depth of the source region 105. In this embodiment, the body contact region 107 is in contact with the side surface of the source region 105. In other embodiments, as Figure 2 As shown, the body contact region 107 at least surrounds a portion of the lower surface of the source region 105 . In an optional embodiment, the body contact region 107 may also surround the entire lower surface of the source region 105 .
[0036] The LDMOS transistor further includes a drift region 103 of the first doping type; a gate dielectric layer 141 adjacent to the source region 105 and located on the upper surface of the well region 102; a voltage-resistant layer 142 adjacent to the drain region 106 and located on the well region 102; and a gate conductor 140 at least located on the gate dielectric layer. In this embodiment, the body region 104 extends to a portion of the gate dielectric layer 141, the drift region 103 extends at least to a portion of the voltage-resistant layer 142, the drain region 106 is located in the drift region 103 and on a side of the voltage-resistant layer 142 away from the gate dielectric layer 141, and the gate conductor 140 further extends to the voltage-resistant layer 142.
[0037] In this embodiment, the LDMOS transistor further includes a substrate 101, the substrate is set to the second doping type, and the well region is set to the first doping type. In other optional embodiments, the well region may also be set to the second doping type, in which case the body region and the drift region need to be set to a contact state. In addition, an epitaxial layer or a buried layer may also be included between the substrate and the well region, which is not limited here.
[0038] The present invention reduces the base resistance of the surface parasitic transistor (source region 105 / body region 104 / well region 102 and drift region 103) by setting the junction depth of the body contact region greater than the junction depth of the source region, thereby reducing the influence of the parasitic transistor on the robustness of the LDMOS transistor.
[0039] Figure 3 2 is a cross-sectional view showing an LDMOS transistor according to a third embodiment of the present invention, Figure 3 The LDMOS transistor shown is Figure 2The difference between the LDMOS transistors shown is that the body contact region and the source electrode are arranged differently, and the other structures are basically the same, which will not be described in detail here.
[0040] like Figure 3 As shown, the body contact region 207 extends from the upper surface of the body region 104 to the inside of the body contact region 104, and the body contact region 207 extends laterally to the bottom of the source region 105 to partially surround the lower surface of the source region 105. The source electrode S1 extends from the upper surface of the body contact region 207 to the inside thereof, and the source electrode S1 contacts the side surface of the source region 105. Furthermore, the lower surface of the source electrode S1 is lower than the lower surface of the source region 105, and the width of the source electrode S1 along the direction from the source region to the drain region is smaller than the width of the body contact region 207. Specifically, the source electrode S1 includes a groove in the body contact region 207, and a conductive material filled in the groove.
[0041] The arrangement of the body contact region and the source electrode in this embodiment makes it easier for the accumulated charge in the base region of the surface parasitic transistor to be drawn away by the source electrode in the body contact region, which is beneficial to improving the high current capability and robustness of the LDMOS transistor and enhancing the reverse recovery capability of the transistor.
[0042] Figure 4 A cross-sectional view showing an LDMOS transistor according to a fourth embodiment of the present invention, Figure 4 The LDMOS transistor shown is Figure 3 The difference between the LDMOS transistor shown in FIG. 1 and FIG. 2 is that it further includes a buffer field plate 112. Figure 4 As shown, the LDMOS transistor includes: a well region 102; a source region 105 of a first doping type and a drain region 106 of a first doping type located in the well region 102; a gate dielectric layer 111 adjacent to the source region 105 and located on the upper surface of the well region 102; a voltage-resistant layer 113 adjacent to the drain region, located on the upper surface of the well region and protruding into the well region 102, and a buffer field plate 112, located between the gate dielectric layer 111 and the voltage-resistant layer 113, and located on the upper surface of the well region 102, wherein the thickness of the voltage-resistant layer 113 is greater than the thickness of the buffer field plate 112, and the thickness of the buffer field plate 112 is greater than the thickness of the gate dielectric layer 111. In a preferred embodiment, the length of the gate dielectric layer 111 is less than the length of the voltage-resistant layer 113; the length of the buffer field plate 112 is less than the length of the voltage-resistant layer 113. It should be noted that the length and thickness of the buffer field plate 112 and the length and thickness of the voltage-resistant layer 113 can be adjusted accordingly according to the requirements of the applied voltage and the ultimate optimization of the specific on-resistance Rsp.
[0043] In this embodiment, the lower surface of the voltage-resistant layer 113 is lower than the lower surface of the buffer field plate 112, the upper surface of the buffer field plate 112 is higher than the upper surface of the gate dielectric layer 111, and the upper surface of the voltage-resistant layer 113 is higher than the upper surface of the buffer field plate 112. The lower surface of the buffer field plate 112 and the lower surface of the gate dielectric layer 111 are approximately located in the same plane. It should be noted that when the gate dielectric layer 111 and the buffer field plate 112 are both formed by depositing a dielectric layer, the lower surface of the buffer field plate 112 and the lower surface of the gate dielectric layer 111 are located in the same plane; when the gate dielectric layer 111 and the buffer field plate 112 are both formed by thermal oxidation growth, the lower surface of the buffer field plate 112 may be slightly lower than the lower surface of the gate dielectric layer 111.
[0044] In this embodiment, the buffer field plate 112 has a uniform thickness. In an optional embodiment, the buffer field plate is arranged along a direction from the source region to the drain region, and the thickness increases successively.
[0045] In this embodiment, the voltage-resistant layer 113 is configured to be bird's beak-shaped and is formed by a local silicon oxidation process. The thickness of the voltage-resistant layer 113 is uniform except for the bird's beak portion. In other embodiments, the voltage-resistant layer 113 can also be formed by a process of depositing a dielectric layer. In this case, the lower surface of the voltage-resistant layer 113 and the lower surface of the buffer field plate 112 are approximately located in the same plane. In an optional embodiment, the thickness of the voltage-resistant layer 113 increases in sequence along the direction from the source region to the drain region.
[0046] In this embodiment, the thickness of the gate dielectric layer is set to 0.95nm-9.5nm, and can be formed synchronously with the gate oxide of the CMOS device. The thickness of the buffer field plate is set to 4nm-40nm, and the thickness of the voltage-resistant layer is set to 25nm-350nm. Both the buffer field plate and the voltage-resistant layer can be formed by a thermal oxygen growth process or a deposition process.
[0047] The LDMOS transistor further includes a gate conductor 120 and a field shield conductor 121 which are separately arranged, wherein the gate conductor 120 is at least located on the gate dielectric layer 111, and the field shield conductor 121 is at least located on the voltage-resistant layer 113. In this embodiment, the gate conductor 120 is located on the gate dielectric layer 111 and a portion of the buffer field plate 112, and the field shield conductor 121 is located on a portion of the voltage-resistant layer 113 and a portion of the buffer field plate 112. In an optional embodiment, the gate conductor 120 is only located on the gate dielectric layer 111, and may also extend from the gate dielectric layer 111 to the buffer field plate 112, or may also extend from the gate dielectric layer 111 to the voltage-resistant layer 113; the field shield conductor 121 may be only located on the voltage-resistant layer 113, or may extend from the voltage-resistant layer 113 to the buffer field plate 112. The gate conductor 120 and the field shield conductor 121 are preferably both made of polysilicon. The field shield conductor can be set to a first doping type or a second doping type. The field shield conductor 121 can be connected to the same potential as the gate conductor 120, or the field shield conductor 121 can be connected to other potentials separately.
[0048] The gate dielectric layer 111 of the LDMOS transistor provided in this embodiment is very thin, and the threshold voltage of the transistor is very low, so that the energy required to drive the low threshold power module of the power integrated circuit is reduced, the switching frequency of the low threshold power module is accelerated, and the reverse surface channel current of the transistor with the low threshold voltage is increased, so that the body reverse recovery current (the current flowing through the well region and the body region) becomes smaller, thereby effectively reducing the power loss of the power stage driver in the high-frequency switch and reducing the reverse recovery loss of the transistor at the same time; the buffer field plate 112 can be defined as an extension of the gate dielectric layer, and its thickness is greater than the thickness of the gate dielectric layer, so as to reduce the electric field on the gate dielectric layer close to the drain region side, so that the length of the gate dielectric layer can be reduced, and the reverse recovery loss of the transistor can be reduced. The charge required to turn on the transistor can slow down the tunneling current that appears at the gate dielectric layer when the transistor works at a high voltage; and the lower surface of the buffer field plate is in the same plane as the lower surface of the gate dielectric layer, the surface current path of the transistor is short, and the specific on-resistance of the transistor can be reduced; the voltage-resistant layer 113 is set to be an oxide layer thicker than the buffer field plate 112, and protrudes into the well area, so that the current path on the surface of the high-voltage area of the transistor is long, so as to improve the voltage resistance of the transistor, and the voltage-resistant layer 113 is combined with the field shielding conductor separated from the gate electrode above it, and the drift region below it, so as to further improve the breakdown voltage of the device, reduce the voltage coupling of the device drain to the gate, reduce the voltage coupling loss of the device, and reduce the specific on-resistance of the device.
[0049] Figure 5 2 is a cross-sectional view showing an LDMOS transistor according to a fifth embodiment of the present invention, Figure 5The LDMOS transistor shown is Figure 3 The difference between the LDMOS transistor shown is that it further includes a reduced surface electric field region of the second doping type. The other structures are basically the same and will not be described in detail here.
[0050] In this embodiment, the reduced surface electric field region 401 of the second doping type is arranged below the drift region 103 of the first doping type to deplete each other with the drift region 103, reduce the surface electric field between the gate and drain of the transistor, and improve the breakdown voltage of the transistor. The reduced surface electric field region 401 can be arranged to contact the body region 104, or can be arranged to be separated from the body region. Among them, the spacing between the drift region 103 and the reduced surface electric field region 401 is greater than or equal to 0. In other embodiments, the drift region 103 and the reduced surface electric field region 401 can also be arranged left and right, or the reduced surface electric field region 401 surrounds the drift region 103, etc., and the positional relationship between the drift region 103 and the reduced surface electric field region 401 is not limited here.
[0051] In this embodiment, the number of layers of the drift region 103 and the reduced surface electric field region 401 is set to one. In other embodiments, the number of layers of the drift region 103 and the reduced surface electric field region 401 can also be set to multiple, which is not limited here.
[0052] In other embodiments, the drift region 103 includes a plurality of first doped regions that are separately arranged, and the reduced surface electric field region 401 includes a plurality of second doped regions that are separately arranged. Specifically, the plurality of first doped regions that are separately arranged are arranged in a lateral direction, the plurality of second doped regions that are separately arranged are arranged in a lateral direction, and the second doped regions are located below the first doped regions. Preferably, a second doped region is arranged below each first doped region. The spacing between adjacent first doped regions and the width of each first doped region can be arbitrarily set according to requirements, and the spacing between adjacent second doped regions and the width of each first doped region can be arbitrarily set according to requirements.
[0053] Figure 6 2 is a cross-sectional view showing an LDMOS transistor according to a sixth embodiment of the present invention, Figure 6 The LDMOS transistor shown is Figure 3 The difference between the LDMOS transistors shown is that the arrangement of the drain region is different, and the other structures are basically the same, which will not be described in detail here.
[0054] In this embodiment, the drain region 506 is located below the voltage-resistant layer 143; the drain electrode D1 passes through the voltage-resistant layer 142 and contacts the drain region 506. Preferably, the drain region 506 is aligned with the side of the voltage-resistant layer 142 away from the gate dielectric layer 141. In an optional embodiment, a shallow isolation trench is further included below the voltage-resistant layer 142, wherein the shallow isolation trench is located between the source region and the drain region.
[0055] In this embodiment, the drain region is disposed below the voltage-resistant layer, and the formation of a metal silicide barrier layer in the drain region can be omitted, so as to reduce the size of the LDMOS transistor.
[0056] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.
Claims
1. An LDMOS transistor, characterized in that: include: Well region; a body region of a second doping type extending from an upper surface of the well region to an interior of the well region; a source region of a first doping type and a body contact region of a second doping type extending from an upper surface of the body region to an interior thereof; a drain region of a first doping type, located in the well region; as well as a source electrode, contacting the body contact region and the source region; Wherein, the junction depth of the body contact region is greater than the junction depth of the source region.
2. The LDMOS transistor according to claim 1, characterized in that The body contact region surrounds at least a portion of a lower surface of the source region.
3. The LDMOS transistor according to claim 1, characterized in that: The source electrode is located on upper surfaces of the source region and the body contact region.
4. The LDMOS transistor according to claim 1, characterized in that: The source electrode extends from the upper surface of the body contact region to the inside of the body contact region.
5. The LDMOS transistor according to claim 4, characterized in that: The source electrode extends in the body contact region to a depth greater than a junction depth of the source region.
6. The LDMOS transistor according to claim 4, characterized in that: The source electrode contacts a side surface of the source region.
7. The LDMOS transistor according to claim 4, characterized in that: The source includes a trench in the body contact region and a conductive material in the trench.
8. The LDMOS transistor according to claim 4, characterized in that: The width of the body contact region along the direction from the source region to the drain region is greater than the width of the source electrode.
9. The LDMOS transistor according to claim 1, characterized in that: Also includes: A gate dielectric layer adjacent to the source region is located on the upper surface of the well region; as well as The voltage-resistant layer adjacent to the drain region is located on the well region.
10. The LDMOS transistor according to claim 9, characterized in that: Also includes: a buffer field plate, located between the gate dielectric layer and the voltage-resistant layer and on the upper surface of the well region, Wherein, the thickness of the voltage-resistant layer is greater than the thickness of the buffer field plate, and the thickness of the buffer field plate is greater than the thickness of the gate dielectric layer.
11. The LDMOS transistor according to claim 9, characterized in that: It also includes a drift region of the first doping type located in the well region, and the drift region is at least located below the voltage-resistant layer.
12. The LDMOS transistor according to claim 9, characterized in that: The voltage-resistant layer protrudes toward the inside of the well region.
13. The LDMOS transistor according to claim 10, characterized in that: The lower surface of the buffer field plate and the lower surface of the gate dielectric layer are located on the same plane parallel to the direction from the source region to the drain region.
14. The LDMOS transistor according to claim 10, characterized in that: The lower surface of the buffer field plate and the lower surface of the gate dielectric layer are higher than the lower surface of the voltage-resistant layer.
15. The LDMOS transistor according to claim 10, characterized in that: The thickness of the gate dielectric layer is set to be 0.95nm to 9.5nm.
16. The LDMOS transistor according to claim 10, characterized in that: It also includes a gate conductor at least located on the gate dielectric layer.
17. The LDMOS transistor according to claim 10, characterized in that: The invention also includes a field shielding conductor at least located on the voltage-sustaining layer.
18. The LDMOS transistor according to claim 11, characterized in that: The invention also includes a reduced surface electric field region of the second doping type located in the well region, wherein the reduced surface electric field region and the drift region are mutually depleted.
19. The LDMOS transistor according to claim 9, characterized in that: It also includes a drain electrode, wherein the drain region is located below the voltage-resistant layer, and the drain electrode passes through the voltage-resistant layer and extends to the drain region.
20. The LDMOS transistor according to claim 9, characterized in that It also includes a shallow trench isolation structure located below the voltage-resistant layer.