Total dose irradiation resistant high-voltage LDMOS device

Abstract

The invention belongs to the technical field of semiconductor power devices, and particularly provides a high-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device capable of resisting total dose irradiation, which is used for solving the problem that holes in electron-hole pairs generated by an oxide layer of a traditional LDMOS device after the total dose irradiation are trapped to form trapped charges, so that the electrical characteristics of the device are changed. An extended field plate (16) is arranged, the extended field plate (16) is spliced to the side, pointing to a drain electrode, of a gate metal field plate (14), the gate metal field plate (14) extends towards the side of the drain electrode, and the extension length is 0.4-0.6 time of the length of the gate metal field plate (14); the extension field plate enables the gate metal field plate to extend towards one side of the drain, thereby effectively optimizing the distribution of trapped charges in an oxide layer after the device is irradiated, reducing the concentration of the trapped charges, and reducing the influence of irradiation on the electrical characteristics of the device. Under the same irradiation condition, the performance parameters of the LDMOS device are more stable, and the LDMOS device has better total dose irradiation effect resistance.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor power devices, and specifically provides a high-voltage LDMOS device resistant to total dose radiation. Background Art

[0002] In recent years, my country has developed rapidly in the fields of aerospace and aviation, and more and more electronic devices have been applied to the space environment, where the working environment is far more harsh than that of the earth. In the space environment, there are a large number of high-energy particles and cosmic rays. When these particles and rays pass through the spacecraft and act on the components, they will have an adverse radiation effect on the devices. According to the statistics of satellite failure causes, equipment failures caused by radiation account for as much as 40%. Therefore, how to reduce the damage of radiation to devices and improve chip reliability has become an urgent problem to be solved.

[0003] LDMOS devices have the advantages of high integration, high reliability and fast switching speed. As the core device of integrated circuits, they are widely used in gate driver integrated circuits, power supply integrated circuits and analog switch integrated circuits. In order to improve the ability of LDMOS to withstand high voltage and high current, technologies such as terminals, field plates, surface electric field reduction and drift region growth are used when developing and designing devices. However, while these technologies optimize the performance of LDMOS devices, they also increase their size. In high-voltage switching circuits, the area of ​​LDMOS power devices can account for more than half of the area of ​​the entire integrated circuit. Therefore, in a space environment, the probability of damage caused by radiation is greater. In recent years, the application of more and more high-voltage integrated products in the aerospace field has further highlighted the importance of studying the radiation effects of LDMOS devices.

[0004] The total dose irradiation effect refers to the device performance degradation caused by the trapped charges induced by radiation in the oxide layer. The total dose irradiation effect affects semiconductor devices in two ways: one is the ionization effect, which means that the energy of the incident high-energy particles is absorbed by the silicon dioxide atoms, ionizing to produce electron-hole pairs, which in turn have a series of effects on the device; the other is the displacement effect of atoms, which means that the silicon atoms deviate from their original lattice positions due to the impact of the incident high-energy particles, causing lattice damage. The impact of ionization damage is more far-reaching and more likely to occur than displacement damage. The generation of electron-hole pairs in the oxide will cause charge accumulation, resulting in a decrease in device performance; therefore, the research on the total dose irradiation effect mainly focuses on the ionization effect.

[0005] The cross-sectional structure of a conventional LDMOS device is as follows: Figure 1As shown, it includes: a substrate (01) located at the bottom; a drift region (02) located above the substrate (01); a P-type well region (03) located at the upper left of the drift region (02); an N-type well region (04) located at the upper right of the drift region (02); an N-type buried layer (05) and a P-type buried layer (06) located in the middle of the drift region (02); a source P+ region (07) and a source N+ region (08) located above the P-type well region (03); a drain N+ region (09) located above the N-type well region (04); a silicon dioxide layer (10) located above the drift region (02); polysilicon (12) located above the silicon dioxide layer (10); a source (13), a gate metal field plate (14) and a drain (15) located in an interlayer dielectric (11); when a voltage of 300V is applied to the drain, the electric field strength in the silicon dioxide layer is as follows: Figure 2 As shown. The number of electron-hole pairs generated by the device under irradiation is closely related to the electric field strength. The greater the electric field strength, the more electron-hole pairs are generated. Due to the high electron mobility, the electrons induced by radiation are quickly moved out of the oxide layer, causing little damage to the device. However, the hole mobility is slow, and the holes induced by radiation are captured by traps in the oxide layer, forming positively charged oxide layer trap charges, which are locally aggregated under the action of the electric field and become the main cause of device damage. The schematic diagram of the trap charge distribution inside the device after irradiation is shown in Figure 3 As shown in the figure, when the device is just in the irradiation environment, electron-hole pairs will be generated in the oxide layer, and the electrons will quickly migrate out of the oxide layer, while the holes will be trapped; but due to the existence of the drain voltage, under the action of the electric field formed by the voltage, the holes will diffuse and drift, and eventually form an uneven distribution of trapped charges in the oxide layer, affecting the device performance. Further, the schematic diagram of the trap charge distribution of the conventional LDMOS under different irradiation doses is shown in Figure 4 As shown in the figure, under the action of external bias, the charge distribution in the oxide layer is high in the middle and low on both sides; in the area near the drain end, firstly, due to the small electric field strength, there are few electron-hole pairs induced by radiation; secondly, the electric field points away from the drain end, and the small amount of holes induced will move in the direction away from the drain end, so the trap charge concentration near the drain end is low; the electric field strength in the middle part is moderate, the number of electron-hole pairs induced by radiation is large, and the holes generated near the drain end move to the middle part, causing the formation of trapped charge accumulation in the middle part; although the electric field strength near the source end is large, due to the existence of the device field plate structure, the electric field direction points upward to the field plate, and the holes are extracted by the electric field, so the trap charge concentration near the source end is also relatively low.

[0006] To this end, the present invention proposes a novel LDMOS device structure, which lengthens the metal field plate to change the direction of the electric field in the oxide layer, so that more holes are extracted by the upward electric field, reconstructs the distribution of trapped charges, and improves the device's radiation resistance. Summary of the invention

[0007] The purpose of the present invention is to provide a high-voltage LDMOS device resistant to total dose radiation in order to solve the problem that holes in electron-hole pairs generated in an oxide layer of a traditional LDMOS device after total dose radiation are captured to form trapped charges, thereby causing changes in the electrical characteristics of the device. An extended field plate is provided to extend the gate metal field plate toward the drain side, thereby optimizing the distribution of trapped charges in the oxide layer of the device after radiation, reducing the concentration of trapped charges, and thus reducing the influence of radiation on the electrical characteristics of the device. Under the same radiation conditions, the performance parameters of the LDMOS device in the present invention are more stable, and the device has better resistance to the total dose radiation effect.

[0008] To achieve the above object, the technical solution adopted by the present invention is:

[0009] A total dose radiation resistant high voltage LDMOS device comprises: a substrate (01), a drift region (02), a P-type well region (03), an N-type well region (04), an N-type buried layer (05), a P-type buried layer (06), a source P+ region (07), a source N+ region (08), a drain N+ region (09), a silicon dioxide layer (10), an interlayer dielectric layer (11), a polysilicon gate (12), a source (13), a gate metal field plate (14), a drain (15) and an extended field plate (16); wherein:

[0010] The drift region (02) is arranged on the substrate (01); the P-type well region (03) and the N-type well region (04) are arranged in the drift region (02) and are located at the upper left and upper right, respectively; the N-type buried layer (05) and the P-type buried layer (06) are embedded in the middle area of ​​the drift region (02), and the N-type buried layer (05) is arranged on the P-type buried layer (06); the source P+ region (07) is adjacent to the source N+ region (08) and is jointly arranged in the P-type well region (03); the source (13) is arranged between the source P+ region (07) and the source The invention relates to a first embodiment of the present invention, wherein the first embodiment comprises a first gate electrode (14) and a second gate electrode (16) arranged on the N+ region (08); the drain N+ region (09) is arranged in the N-type well region (04); the drain (15) is arranged on the drain N+ region (09); the silicon dioxide layer (10) is arranged on the drift region (02); the polysilicon gate (12) is arranged on the silicon dioxide layer (10) and is located on the source side; the gate metal field plate (14) is arranged on the polysilicon gate (12); the extended field plate (16) is spliced ​​to the gate metal field plate (14) and points to the drain side, so that the gate metal field plate (14) extends toward the drain side.

[0011] Furthermore, the extension length is 0.4 to 0.6 times the length of the gate metal field plate (14).

[0012] Based on the above technical solution, the beneficial effects of the present invention are:

[0013] The present invention provides a total dose radiation resistant high-voltage LDMOS device, creatively proposes an extended field plate (16) structure, by splicing the extended field plate (16) to the gate metal field plate (14) pointing to the drain side, so that the gate metal field plate (14) extends toward the drain side, and only by optimizing the extended field plate (16), the distribution of trapped charges in the oxide layer of the device after irradiation can be effectively optimized, the concentration of trapped charges can be reduced, thereby reducing the influence of irradiation on the electrical characteristics of the device, and ultimately improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematic diagram of the cross-sectional structure of a conventional LDMOS device.

[0015] Figure 2 for Figure 1 Schematic diagram of the electric field strength in the silicon dioxide layer when a voltage of 300V is applied to the drain of the LDMOS device shown.

[0016] Figure 3 for Figure 1 Schematic diagram of internal trapped charge distribution of the LDMOS device after irradiation.

[0017] Figure 4 for Figure 1 The trapped charge distribution of the LDMOS device shown is under multiple radiation doses.

[0018] Figure 5 The present invention is a schematic cross-sectional structure diagram of a high-voltage LDMOS device resistant to total dose radiation provided by the present invention.

[0019] Figure 6 1 is a diagram showing the distribution of trapped charges of a high-voltage LDMOS device resistant to total-dose radiation under multiple radiation doses in an embodiment of the present invention.

[0020] Figure 7 It is a comparison diagram of the trapped charge distribution of the LDMOS device at a dose of 70 krad in the embodiment of the present invention and the comparative example.

[0021] Figure 8 The figure is a curve diagram showing the variation of the breakdown voltage of the LDMOS device with the radiation dose in the embodiment of the present invention and the comparative example. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical scheme and technical effect of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0023] This embodiment provides a high-voltage LDMOS device resistant to total dose radiation, which effectively improves the reliability of the device by adjusting the distribution of trapped charges. Figure 5As shown, it specifically includes: a substrate (01), a drift region (02), a P-type well region (03), an N-type well region (04), an N-type buried layer (05), a P-type buried layer (06), a source P+ region (07), a source N+ region (08), a drain N+ region (09), a silicon dioxide layer (10), an interlayer dielectric layer (11), a polysilicon gate (12), a source (13), a gate metal field plate (14), a drain (15) and an extended field plate (16); wherein:

[0024] The drift region (02) is arranged on the substrate (01); the P-type well region (03) and the N-type well region (04) are arranged in the drift region (02) and are respectively located at the upper left and upper right; the N-type buried layer (05) and the P-type buried layer (06) are embedded in the middle area of ​​the drift region (02), and the N-type buried layer (05) is arranged on the P-type buried layer (06); the source P+ region (07) is adjacent to the source N+ region (08) and is jointly arranged in the P-type well region (03); the source (13) is arranged on the source P+ region (07) and the source N+ region (08); the drain N+ region (09) is arranged The device is placed in an N-type well region (04); the drain (15) is arranged on the drain N+ region (09); the silicon dioxide layer (10) is arranged on the drift region (02); the polysilicon gate (12) is arranged on the silicon dioxide layer (10) and is located on the source side; the gate metal field plate (14) is arranged on the polysilicon gate (12); the extended field plate (16) is spliced ​​to the gate metal field plate (14) and points to the drain side, so that the gate metal field plate (14) extends toward the drain side, and the extended length is 0.4 to 0.6 times the length of the gate metal field plate (14), and the extended length is the length of the extended field plate.

[0025] To further illustrate the beneficial effects of the present invention, Figure 1 The conventional LDMOS device shown is used as a comparative example. Without changing other structural parameters, the length of the extended field plate (16) is set to 3 μm, that is, the gate metal field plate (14) extends 3 μm toward the drain side. By extending the gate metal field plate, more holes are extracted by the electric field, which reduces the influence of radiation on device performance and improves the device's ability to resist total dose radiation.

[0026] like Figure 6 The figure shows the trap charge distribution diagram of the high-voltage LDMOS device resistant to total dose radiation in this embodiment under multiple radiation doses. It can be seen from the figure that the overall charge distribution law is similar to Figure 4 As shown in the figure, they all show a trend of being high in the middle and low on both sides, and with the increase of irradiation dose, the concentration of trapped charges generated also increases.

[0027] like Figure 7The figure shows a comparison of the trapped charge distribution of the LDMOS device in this embodiment and the comparative example at a dose of 70 krad. It can be seen from the figure that the low-concentration region on the left side of the LDMOS device in the present invention is significantly longer than the low-concentration region on the left side of the traditional LDMOS device, which indicates that under the effect of extending the field plate, more trapped charges are extracted and the high-concentration region is shortened.

[0028] like Figure 8 The figure shows a curve diagram of the breakdown voltage of the LDMOS device in the present embodiment and the comparative example as a function of the irradiation dose. It can be seen from the figure that the breakdown voltage of the conventional LDMOS device reaches a maximum when the irradiation dose is 100 krad, and then begins to decline, indicating that the trapped charge concentration generated at this time modulates the drift region concentration of the conventional device to reach the optimum; while the breakdown voltage of the LDMOS device in the present invention continues to increase after the irradiation dose exceeds 100 krad, indicating that the trapped charge concentration generated at this time does not make the drift region concentration of the inventive device reach the optimum, and the device can withstand higher doses of irradiation; it can be seen that the LDMOS device provided by the present invention has stronger radiation resistance than the conventional device.

[0029] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A high-voltage LDMOS device resistant to total dose radiation, comprising: A substrate (01), a drift region (02), a P-type well region (03), an N-type well region (04), an N-type buried layer (05), a P-type buried layer (06), a source P+ region (07), a source N+ region (08), a drain N+ region (09), a silicon dioxide layer (10), an interlayer dielectric layer (11), a polysilicon gate (12), a source (13), a gate metal field plate (14), a drain (15), and an extended field plate (16); characterized in that: The drift region (02) is arranged on the substrate (01); the P-type well region (03) and the N-type well region (04) are arranged in the drift region (02) and are located at the upper left and upper right, respectively; the N-type buried layer (05) and the P-type buried layer (06) are embedded in the middle area of ​​the drift region (02), and the N-type buried layer (05) is arranged on the P-type buried layer (06); the source P+ region (07) is adjacent to the source N+ region (08) and is jointly arranged in the P-type well region (03); the source (13) is arranged between the source P+ region (07) and the source The invention relates to a first embodiment of the present invention, wherein the first embodiment comprises a first gate electrode (14) and a second gate electrode (16) arranged on the N+ region (08); the drain N+ region (09) is arranged in the N-type well region (04); the drain (15) is arranged on the drain N+ region (09); the silicon dioxide layer (10) is arranged on the drift region (02); the polysilicon gate (12) is arranged on the silicon dioxide layer (10) and is located on the source side; the gate metal field plate (14) is arranged on the polysilicon gate (12); the extended field plate (16) is spliced ​​to the gate metal field plate (14) and points to the drain side, so that the gate metal field plate (14) extends toward the drain side.

2. The high-voltage LDMOS device resistant to total dose radiation according to claim 1, characterized in that: The extension length is 0.4 to 0.6 times the length of the gate metal field plate (14).

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