Electrostatic resonator and preparation method thereof
By setting a silicon oxide layer on the anchor point, electrode and resonator side wall of the MEMS electrostatic resonator, the problem of large electrode gap in the MEMS process is solved, a larger capacitance and electric field is achieved, and the performance of the electrostatic resonator is improved. .
Patent Information
- Application Number
- CN202411318659.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-20
- Publication Date
- 2024-12-20
AI Technical Summary
In the MEMS process, the deep reactive ion etching process is constrained by the depth aspect ratio and the minimum line width, resulting in the large gap between the prepared electrostatic resonator electrodes and cannot meet the design requirements, limiting the preparation of high-performance electrostatic resonators.
By providing a silicon oxide layer on the side walls of the anchor point, the electrode and the resonator, and extending the silicon oxide layer into the cavity, forming a dielectric layer on the inner wall of the cavity, thereby reducing the electrode spacing and achieving a larger capacitance and electric field.
The electrode spacing is reduced, the performance of the electrostatic resonator is improved, and the driving voltage is reduced at the same time, which is improved.
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Figure CN119171870A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of micro-electromechanical systems, and in particular to an electrostatic resonator and a method for preparing the same. Background Art
[0002] Micro-Electro-Mechanical System (MEMS) is a high-tech field based on microelectronics and micromachining technology. MEMS technology can integrate mechanical components, drive components, electronic control systems, digital processing systems, etc. into an integrated micro unit. MEMS devices have many advantages such as being small, intelligent, executable, integrable, having good process compatibility, and low cost. The development of MEMS technology has opened up a new technological field and industry. Micro sensors, micro actuators, micro components, micromechanical optical devices, vacuum microelectronic devices, power electronic devices, etc. made using MEMS technology have very broad application prospects in the fields of aviation, aerospace, automobiles, biomedicine, environmental monitoring, military, and the Internet of Things.
[0003] MEMS electrostatically driven resonators rely on two plates to form a capacitor, and use the electric field to form an electrostatic force to drive the resonator to resonate. Usually, MEMS electrostatically driven resonators reduce the distance between the plates to obtain a larger capacitor, thereby generating a larger electric field, while strengthening the electrostatic force and reducing the driving voltage.
[0004] However, in the MEMS process, DRIE (deep reactive ion etching process) is constrained by the aspect ratio and the minimum line width, resulting in the prepared electrostatic resonator having a large gap between electrodes. The gap cannot be made small enough, that is, it cannot meet the design requirements, which in turn limits the preparation of high-performance electrostatic resonators. Summary of the invention
[0005] In view of this, the present application provides an electrostatic resonator and a method for preparing the same to reduce the distance between electrodes.
[0006] The present application provides an electrostatic resonator, comprising:
[0007] A first wafer, comprising a first anchor portion, a first electrode connection portion and a groove; wherein the first electrode connection portion is arranged on both sides of the first anchor portion, the groove is arranged on both sides of the first electrode connection portion, and the first anchor portion and the first electrical connection portion are spaced apart by the groove;
[0008] A second wafer is bonded to the first wafer, and the groove and the second wafer are covered to form a cavity; the second wafer has a second anchor portion, a second electrode connecting portion, a resonant body, and a through hole; wherein the second anchor portion is connected to the first anchor portion to form an anchor, the first electrode connecting portion is connected to the second electrode connecting portion to form an electrode, the through hole passes through the second wafer to communicate with the cavity, and the resonant body is located on both sides of the second electrode connecting portion and is spaced apart from the anchor and the electrode through the through hole;
[0009] The silicon oxide layer is arranged on the anchor point, the electrode, the side wall of the resonator and the inner wall of the cavity.
[0010] In some embodiments, the first wafer further includes a through silicon via, wherein the through silicon via is located at the bottom of the cavity and penetrates the first wafer to communicate with the cavity.
[0011] In some embodiments, the electrostatic resonator further includes a capping layer, wherein the capping layer is connected to a side of the second wafer facing away from the first wafer.
[0012] In some embodiments, the electrostatic resonator further includes a bonding layer disposed on the anchor point.
[0013] The present application also provides a method for preparing an electrostatic resonator, which is used to prepare the electrostatic resonator as described above, comprising:
[0014] The first wafer is patterned to form a first anchor portion, a first electrode connection portion and a groove; the first electrode connection portion is arranged on both sides of the first anchor portion, the groove is arranged on both sides of the first electrode connection portion, and the first anchor portion and the first electrical connection portion are spaced apart by the groove;
[0015] Bonding the second wafer to the first wafer, wherein the groove and the second wafer are covered to form a cavity;
[0016] The second wafer is patterned to form a second anchor portion, a second electrode connection portion, a resonant body, and a through hole; wherein the second anchor portion is connected with the first anchor portion to form an anchor point, the first electrode connection portion is connected with the second electrode connection portion to form an electrode, the through hole penetrates the second wafer to communicate with the cavity, and the resonant body is located at both sides of the second electrode connection portion and is spaced apart from the anchor point and the electrode through the through hole;
[0017] A silicon oxide layer is formed on the second wafer, wherein the silicon oxide layer is located on the anchor point, the electrode, the side wall of the resonator, and the inner wall of the cavity.
[0018] In some embodiments, before patterning the first wafer, the method further includes:
[0019] providing a first wafer;
[0020] forming a first hard mask on the first wafer;
[0021] performing patterning on the first hard mask to expose a portion of the first wafer;
[0022] Performing patterning on the exposed first wafer to form silicon grooves;
[0023] The first hard mask is removed.
[0024] In some embodiments, patterning the first wafer includes:
[0025] forming a second hard mask on the first wafer;
[0026] performing patterning on the second hard mask to expose a portion of the first wafer;
[0027] The exposed portion of the first wafer is patterned to form a first anchor portion, a first electrode connection portion, a groove, and a first support portion; the first electrode connection portion is disposed on both sides of the first anchor portion, the first support portion is located on a side of the first electrical connection portion away from the first anchor portion, and the first electrode connection portion is spaced from the first anchor portion and the first support portion by the groove;
[0028] The second hard mask is removed.
[0029] In some embodiments, after bonding the second wafer to the first wafer and before patterning the second wafer, the process further includes:
[0030] forming a bonding film and a third hard mask on a surface of the second wafer facing away from the first wafer;
[0031] performing patterning on the third hard mask film to expose a portion of the bonding film;
[0032] The bonding film is patterned to form a bonding layer that exposes a portion of the second wafer.
[0033] In some embodiments, the patterning process of the second wafer includes:
[0034] forming a fourth hard mask on the bonding layer and the second wafer;
[0035] performing patterning on the fourth hard mask to expose a portion of the second wafer;
[0036] The second wafer is patterned to form a second anchor portion, a second electrode connecting portion, a resonant body, a through hole and a second supporting portion; wherein the second anchor portion is connected to the first anchor portion to form an anchor point, the first electrode connecting portion is connected to the second electrode connecting portion to form an electrode, the second supporting portion and the first supporting portion form a supporting body, the through hole passes through the second wafer to communicate with the cavity, the resonant body is located on both sides of the second electrode connecting portion and is spaced apart from the anchor point, the electrode and the supporting body through the through hole.
[0037] In some embodiments, after patterning the second wafer and before forming a silicon oxide layer on the second wafer, the method further includes:
[0038] A thinning process is performed on a side of the first wafer facing away from the second wafer, and the side of the first wafer is thinned to the bottom of the silicon groove, so that a through silicon via is formed in the silicon groove.
[0039] The present application provides an electrostatic resonator and a preparation method thereof. By arranging a silicon oxide layer on the anchor point, the electrode and the side wall of the resonator, and the silicon oxide layer extending into the cavity to be arranged on the inner wall of the cavity, the dielectric layer between the electrodes is changed from air to a silicon oxide layer, thereby reducing the distance between the two electrodes, that is, the distance between the electrodes can meet the design requirements, and because the distance between the electrodes is reduced, the capacitance between the two electrodes has a larger capacitance under the same area and distance, thereby generating a larger electric field, that is, having a larger electrostatic force while reducing the driving voltage, thereby improving the performance of the electrostatic resonator. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0041] Figure 1 is a schematic diagram of the structure of the electrostatic resonator provided by the present application;
[0042] Figure 2 It is a schematic diagram of the process of preparing the electrostatic resonator provided by the present application;
[0043] Figure 3-Figure 12 It is a schematic diagram of the process structure of the method for preparing an electrostatic resonator provided in this application.
[0044] Reference numerals:
[0045] 10. Electrostatic resonator; 100. First wafer; 110. First anchor portion; 120. First electrode connection portion; 130. Groove; 131. Cavity; 140. First support portion; 150. Through silicon via; 151. Silicon groove; 160. Conductive portion; 170. Positioning groove; 200. Second wafer; 210. Second anchor portion; 220. Second electrode connection portion; 230. Resonator; 240. Through hole; 250. Second support portion; 300. Silicon oxide layer; 400. Bonding layer; 510. First hard mask; 520. Second hard mask; 530. Fifth hard mask. DETAILED DESCRIPTION
[0046] The technical solutions in the embodiments of the present application are clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.
[0047] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the description of the present application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise clearly and specifically defined.
[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by a person skilled in the art to which this application belongs. The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more related listed items. The terms "connection", "electrical connection", and "electrical connection" used herein include any direct and indirect electrical or structural connection means. Therefore, if the text describes a first device coupled / connected / electrically connected to a second device, it means that the first device can be directly electrically / structurally connected to the second device, or indirectly electrically / structurally connected to the second device through other devices or connection means.
[0049] The present application provides an electrostatic resonator, comprising a first wafer, a second wafer and a silicon oxide layer. The first wafer has a first anchor portion, a first electrode connection portion and a groove. The first electrode connection portion is arranged on both sides of the first anchor portion, the groove is arranged on both sides of the first electrode connection portion, and the first anchor portion and the first electrical connection portion are spaced apart by the groove. The second wafer is bonded to the first wafer, and the groove forms a cavity. The second wafer has a second anchor portion, a second electrode connection portion, a resonator and a through hole. The second anchor portion is connected to the first anchor portion to form an anchor point, the first electrode connection portion is connected to the second electrode connection portion to form an electrode, the through hole runs through the second wafer to communicate with the cavity, and the resonator is located on both sides of the second electrode connection portion and is spaced apart from the anchor point and the electrode by the through hole. The silicon oxide layer is arranged on the side walls of the anchor point, the electrode and the resonator and on the inner wall of the cavity.
[0050] In the present application, a silicon oxide layer is provided on the side walls of the anchor point, the electrode and the resonator, and the silicon oxide layer extends into the cavity to be provided on the inner wall of the cavity, so that the dielectric layer between the electrodes is changed from air to a silicon oxide layer, thereby reducing the distance between the two electrodes, that is, the distance between the electrodes can meet the design requirements, and because the distance between the electrodes is reduced, the capacitance between the two electrodes has a larger capacitance at the same area and distance, thereby generating a larger electric field, that is, having a larger electrostatic force while reducing the driving voltage, thereby improving the performance of the electrostatic resonator.
[0051] See also Figure 1 , Figure 1 1 is a schematic diagram of the structure of the electrostatic resonator provided by the present application. The present application provides an electrostatic resonator 10, which includes a first wafer 100, a second wafer 200 and a silicon oxide layer 300. The first wafer 100 has a first anchor portion 110, a first electrode connection portion 120 and a groove 130. The first electrode connection portion 120 is arranged on both sides of the first anchor portion 110, the groove is arranged on both sides of the first electrode connection portion 120, and the first anchor portion 110 and the first electrical connection portion are spaced apart by the groove.
[0052] The second wafer 200 is bonded to the first wafer 100 , and the groove and the second wafer 200 are covered to form a cavity 131 .
[0053] The second wafer 200 has a second anchor portion 210, a second electrode connection portion 220, a resonator 230, and a through hole 240. The second anchor portion 210 is connected to the first anchor portion 110 to form an anchor, the first electrode connection portion 120 is connected to the second electrode connection portion 220 to form an electrode, and the through hole 240 penetrates the second wafer 200 to communicate with the cavity 131. The resonator 230 is located on both sides of the second electrode connection portion 220 and is spaced apart from the anchor and the electrode through the through hole 240, that is, the second wafer 200 constitutes the device layer of the electrostatic resonator 10, and the electrode and the resonator 230 are located on both sides of the anchor.
[0054] The first wafer 100 and the second wafer 200 are made of degenerately doped single crystal silicon. The silicon oxide layer 300 is disposed on the anchor point, the electrode, the sidewall of the resonator 230 and the inner wall of the cavity 131 .
[0055] In one embodiment, the first wafer 100 further includes a first support portion 140, which is located on a side of the first electrode connecting portion 120 away from the first anchor portion 110, and the groove is located between the electrode and the first support portion 140 and the first anchor portion 110. The first support portion 140 is used to form a support body with the second support portion 250, so as to facilitate connecting the cap layer to the support body.
[0056] In one embodiment, the first wafer 100 further includes a through silicon via 150, which is located at the bottom of the cavity 131 and penetrates the first wafer 100 to communicate with the cavity 131. The number of through silicon vias 150 is multiple, such as the number of through silicon vias 150 can be 2, 3, 5, 6 or 7. In this embodiment, the number of through silicon vias 150 is 6 as an example for explanation. Among them, two through silicon vias 150 in each of the four through silicon vias 150 are respectively communicated with the grooves 130 on both sides close to the anchor point, and one through silicon via 150 in the two through silicon vias 150 is respectively communicated with the grooves 130 on both sides away from the anchor point.
[0057] In one embodiment, the first wafer 100 further includes a conductive portion 160. The conductive portion 160 is filled in the through silicon via 150 to be electrically connected to an external element.
[0058] In one embodiment, the first wafer 100 further has a positioning groove 170 with a notch facing the side of the first wafer 100 away from the second wafer 200 and not connected to the cavity 131. The positioning groove 170 is located on both sides of the through silicon via 240150. By providing the positioning groove 170 on the side of the first wafer 100 away from the second wafer 200, it is convenient to perform positioning during the preparation process.
[0059] In one embodiment, the second wafer 200 further includes a second supporting portion 250, which is located on a side of the electrode away from the anchor point. The resonator 230 is located between the second electrode connecting portion 220, the second anchor point portion 210, and the second supporting portion 250. The through hole 240 is located between the resonator 230 and the second anchor point portion 210, between the resonator 230 and the second electrode connecting portion 220, and between the resonator 230 and the second supporting portion 250.
[0060] like Figure 1 As shown, the resonator 230 is spaced apart from the second anchor portion 210 , the second electrode connecting portion 220 and the second supporting portion 250 , wherein the spaced apart portions are through holes 240 .
[0061] In one embodiment, the direction from the anchor point to the electrode is the first direction, and the first direction is the same as the width direction. The width of the second support portion 250 is greater than the width of the first support portion 140, the width of the second electrode connecting portion 220 is greater than the width of the first electrode connecting portion 120, and the width of the second anchor portion 210 is greater than the width of the first anchor portion 110.
[0062] In one embodiment, the electrostatic resonator 10 further includes a bonding layer 400 disposed on the anchor point. Specifically, the bonding layer 400 is disposed on the anchor point and the support body, and the material of the bonding layer 400 is polysilicon, that is, the bonding layer 400 can be a polysilicon bonding layer 400, so that the cap layer can be tightly bonded to the second wafer 200 through the bonding layer 400, thereby improving the mechanical stability and preventing harmful factors such as moisture and oxygen in the external environment from invading the interior of the electrostatic resonator 10, thereby protecting the sensitive components inside the electrostatic resonator 10 from damage, and improving the performance of the electrostatic resonator 10.
[0063] In one embodiment, the electrostatic resonator 10 further includes a capping layer, which is connected to the side of the second wafer 200 facing away from the first wafer 100. Specifically, the capping layer is bonded to the second wafer 200 through a bonding layer 400. The capping layer can be a polysilicon capping layer. By being provided on the capping layer bonded to the second wafer 200, the components in the device are protected, thereby improving the performance of the electrostatic resonator 10.
[0064] In the present application, a silicon oxide layer 300 is provided on the anchor point, the electrode and the side wall of the resonator 230, and the silicon oxide layer 300 extends into the cavity 131 to be provided on the inner wall of the cavity 131, so that the dielectric layer between the electrodes is changed from air to the silicon oxide layer 300, thereby reducing the distance between the two electrodes, that is, the distance between the electrodes can meet the design requirements, and because the distance between the electrodes is reduced, the capacitance between the two electrodes has a larger capacitance at the same area and distance, thereby generating a larger electric field, that is, having a larger electrostatic force while reducing the driving voltage, thereby improving the performance of the electrostatic resonator 10.
[0065] See also Figure 2-Figure 12 , Figure 2 It is a schematic flow chart of the method for preparing an electrostatic resonator provided in this application. Figure 3-Figure 12 1 is a schematic diagram of the process structure of the preparation method of the electrostatic resonator provided by the present application. The present application also provides a preparation method for preparing the electrostatic resonator 10 provided by the present application, and the preparation method comprises the following steps:
[0066] S11, patterning the first wafer to form a first anchor portion, a first electrode connecting portion and a groove; the first electrode connecting portion is arranged on both sides of the first anchor portion, the groove is arranged on both sides of the first electrode connecting portion, and the first anchor portion and the first electrical connecting portion are spaced apart by the groove.
[0067] See also Figure 3-Figure 5 In one embodiment, before step S11, the process further includes: providing a first wafer 100; then, forming a first hard mask 510 on the first wafer 100; then, patterning the first hard mask 510 to expose a portion of the first wafer 100; then, patterning the exposed first wafer 100 to form a silicon groove 151; then, removing the first hard mask 510.
[0068] Specifically, the provided first wafer 100 can be a common wafer or a SOI wafer; then, a first hard mask 510 is formed on the front side of the first wafer 100, and the first hard mask 510 can be a silicon nitride (SiN), silicon oxide or titanium nitride (TiN) hard mask, that is, the material of the first hard mask 510 is composed of at least one of silicon nitride (SiN), silicon oxide and titanium nitride (TiN).
[0069] In this embodiment, the first hard mask 510 is composed of silicon oxide as an example for explanation; then, the first hard mask 510 located on the front side of the first wafer 100 is patterned by a photolithography process to expose a portion of the first wafer 100; then, the exposed first wafer 100 is patterned using the patterned first hard mask 510 located on the front side of the first wafer 100 as a shield or mask, such as patterning the first wafer 100 by a deep reactive ion etching process (DRIE) to form a silicon groove 151, wherein the groove of the silicon groove 151 faces the front side of the first wafer 100; then, the first hard mask 510 on the front side of the first wafer 100 is removed.
[0070] See also Figure 3-Figure 5In one embodiment, while the first hard mask 510 is formed on the front side of the first wafer 100, the first hard mask 510 is also formed on the back side of the first wafer 100, that is, the first hard mask 510 is disposed on both the front side and the back side of the first wafer 100; before the first hard mask 510 on the front side is patterned, the first hard mask 510 on the back side is patterned to expose a portion of the first wafer 100 on the back side, and the patterned first hard mask 510 on the back side is used as a mask or shielding. The back surface of the first wafer 100 is patterned by a photolithography process to form a positioning groove 170 with a notch facing away from the front surface of the first wafer 100; then, the first hard mask 510 located on the front surface is patterned to form a silicon groove 151, and the notch of the silicon groove 151 is opposite to the notch direction of the positioning groove 170, and the positioning groove 170 is located on both sides of the silicon groove 151; in a subsequent step, the first hard mask 510 on the front surface of the first wafer 100 is removed, and the first hard mask 510 located on the back surface of the first wafer 100 is removed at the same time.
[0071] See also Figure 6 In one embodiment, after removing the first hard mask 510 , the method further includes: filling a conducting portion 160 in the silicon trench 151 for electrical connection with external components.
[0072] See also Figure 6 and Figure 7In step S11: specifically, a second hard mask 520 is formed on the first wafer 100; then, the second hard mask 520 is patterned to expose a portion of the first wafer 100; then, the exposed portion of the first wafer 100 is patterned to form a first anchor portion 110, a first electrode connection portion 120, a groove 130 and a first support portion 140, the first electrode connection portion 120 is arranged on both sides of the first anchor portion 110, the first support portion 140 is located on a side of the first electrical connection portion away from the first anchor portion 110, and the first electrode connection portion 120 is spaced from the first anchor portion 110 and the first support portion 140 by the groove 130; then, the second hard mask 520 is removed. Further, a second hard mask 520 is formed on the front side of the first wafer 100; then, the second hard mask 520 located on the front side is patterned by a photolithography process to form a patterned second hard mask 520 located on the front side to expose a portion of the first wafer 100; then, the exposed portion of the first wafer 100 is patterned by a DRIE process using the patterned second hard mask 520 located on the front side as a shield to form the first anchor portion 110 and the first electrode connection portion 110. The first electrode connecting portion 120, the groove 130 and the first supporting portion 140, the first electrode connecting portion 120 is arranged on both sides of the first anchor portion 110, the first supporting portion 140 is located on the side of the first electrical connecting portion away from the first anchor portion 110, the first electrode connecting portion 120 and the first anchor portion 110 and the first supporting portion 140 are spaced apart by the groove 130, the groove 130 is connected to the silicon groove 151, and the silicon groove 151 is located at the bottom of the groove 130; then, the second hard mask 520 located on the front side is removed.
[0073] See also Figure 6 In one embodiment, while the second hard mask 520 is formed on the front surface of the first wafer 100, the second hard mask 520 is also formed on the back surface of the first wafer 100, that is, the second hard mask 520 is provided on both the front and back surfaces of the first wafer 100; when the second hard mask 520 on the front surface is subsequently removed, the second hard mask 520 on the back surface is also removed.
[0074] S12, bonding the second wafer to the first wafer, and the groove and the second wafer are covered to form a cavity.
[0075] See also Figure 8 Specifically, the second wafer 200 is bonded to one side of the first wafer 100 provided with the groove 130 and the silicon groove 151 . The material of the second wafer 200 is degenerately doped single crystal silicon. The groove 130 and the second wafer 200 are covered to form a cavity 131 .
[0076] In one embodiment, after step S12, the method further includes:
[0077] See also Figure 8 and Fig. 9 A fifth hard mask 530 is formed on the reverse side of the first wafer 100 and the side of the second wafer 200 facing away from the first wafer 100 , that is, the fifth hard mask 530 is disposed on both the reverse side of the first wafer 100 and the front side of the second wafer 200 ; then, the fifth hard mask 530 on the front side of the second wafer 200 is removed.
[0078] See also Fig.10 In one embodiment, after removing the fifth hard mask 530 located on the front side of the second wafer 200 , the method further includes:
[0079] A bonding film and a third hard mask are formed on the side of the second wafer 200 facing away from the first wafer 100, that is, the bonding film and the third hard mask are sequentially stacked on the front side of the second wafer 200, wherein the bonding film can be formed by low pressure chemical vapor deposition (LPCVD) or molecular beam epitaxy (MBE), and the bonding film is formed of polysilicon; then, the third hard mask is patterned by a photolithography process to form a patterned third hard mask to expose a portion of the bonding film; then, with the patterned third hard mask as a shield, the bonding film is patterned by a DRIE process to form a bonding layer 400 exposing a portion of the second wafer 200, and the bonding layer 400 is used to bond with the cap layer; then, the third hard mask and the fifth hard mask 530 located on the reverse side of the first wafer 100 are removed.
[0080] S13, patterning the second wafer to form a second anchor portion, a second electrode connecting portion, a resonant body and a through hole, wherein the second anchor portion is connected to the first anchor portion to form an anchor point, the first electrode connecting portion is connected to the second electrode connecting portion to form an electrode, the through hole penetrates the second wafer to communicate with the cavity, and the resonant body is located on both sides of the second electrode connecting portion and is spaced apart from the anchor point and the electrode through the through hole.
[0081] See also Fig.11Specifically, a fourth hard mask is formed on the bonding layer 400 and the second wafer 200; then, the fourth hard mask is patterned to expose a portion of the second wafer 200, such as by using a photolithography process to pattern the fourth hard mask; then, the second wafer 200 is patterned to form a second anchor portion 210, a second electrode connection portion 220, a resonant body 230, a through hole 240 and a second support portion 250, wherein the second anchor portion 210 is connected to the first anchor portion 110 to form an anchor, the first electrode connection portion 120 is connected to the second electrode connection portion 220 to form an electrode, the second support portion 250 is connected to the first support portion 140 to form a support, the through hole 240 penetrates the second wafer 200 to communicate with the cavity 131, and the resonant body 230 is located on both sides of the second electrode connection portion 220 and is spaced apart from the anchor, the electrode and the support through the through hole 240; then, the fourth hard mask is removed. It should be noted that the second hard mask 520, the third hard mask, the fourth hard mask and the fifth hard mask 530 can be silicon nitride (SiN), silicon oxide or titanium nitride (TiN) hard masks, that is, the materials of the second hard mask 520, the third hard mask, the fourth hard mask and the fifth hard mask 530 are composed of at least one of silicon nitride (SiN), silicon oxide and titanium nitride (TiN). In this embodiment, the second hard mask 520, the third hard mask, the fourth hard mask and the fifth hard mask 530 are composed of silicon oxide as an example.
[0082] See also Fig.12 In one embodiment, after step S13, the method further includes:
[0083] The first wafer 100 is thinned on a side facing away from the second wafer 200 to the bottom of the silicon trench 151 , so that the silicon trench 151 forms a through silicon via 150 .
[0084] S14, forming a silicon oxide layer on the second wafer, wherein the silicon oxide layer is located on the anchor point, the electrode, the side wall of the resonator and the inner wall of the cavity.
[0085] See also Fig.12 Specifically, a silicon oxide layer 300 is grown around the electrode, the resonator 230 , the anchor point, the support body, and the first wafer 100 by a low pressure chemical vapor deposition process (LPCVD), so that the silicon oxide layer 300 is attached to the anchor point, the electrode, and the side walls of the resonator 230 and the inner wall of the cavity 131 , and at the same time, the silicon oxide layer 300 is formed on the back side of the first wafer 100 .
[0086] See also Fig.12 In one embodiment, after step S14, the method further includes: removing the silicon oxide layer 300 at the through silicon via 150, so that the conducting portion 160 in the through silicon via 150 is electrically connected to the outside.
[0087] In one embodiment, the time for growing the silicon oxide layer 300 is 1-120 minutes. Specifically, the time for growing the silicon oxide layer 300 can be 1 minute, 20 minutes, 30 minutes, 45 minutes, 85 minutes, 104 minutes, 117 minutes or 120 minutes, etc. By controlling the growth time of the silicon oxide layer 300, the thickness of the silicon oxide layer 300 is controlled. At the same time, when the growth time of the silicon oxide layer 300 is set within this range, the growth quality of the film layer is better.
[0088] In one embodiment, the thickness of the silicon oxide layer 300 is 0.01-2 μm. Specifically, the thickness of the silicon oxide layer may be 0.01 μm, 0.06 μm, 0.09 μm, 0.14 μm, 0.29 μm, 1.3 μm, 1.85 μm or 2 μm.
[0089] In the present application, after the resonator 230, the electrode and the anchor point are formed by etching, the silicon oxide layer 300 is formed on the resonator 230, the electrode and the anchor point, so that the silicon oxide layer 300 is provided on the sidewalls of the anchor point, the electrode and the resonator 230, and the silicon oxide layer 300 extends into the cavity 131 to be provided on the inner wall of the cavity 131, so that the dielectric layer between the electrodes is changed from air to the silicon oxide layer 300, thereby reducing the distance between the two electrodes, that is, the distance between the electrodes can meet the design requirements, and because the distance between the electrodes is reduced, the capacitance between the two electrodes has a larger capacitance under the same area and distance, thereby generating a larger electric field, that is, having a larger electrostatic force while reducing the driving voltage, and at the same time, because the inner wall of the cavity 131 A silicon oxide layer 300 is provided on the outer surface of the resonator 230 and the outer surface of the anchor point to protect the cavity 131, the resonator 230 and the anchor point to avoid damage, thereby improving the performance of the electrostatic resonator 10; in addition, in the present application, when the first wafer 100 is patterned to form the groove 130, the silicon oxide layer 300 is not formed in the inner wall of the groove 130, but the second wafer 200 is first patterned to form the resonator 230, the anchor point and the electrode, and then the silicon oxide layer 300 is formed on the outer surface of the resonator 230, the outer surface of the electrode and the outer surface of the anchor point. The preparation process of the electrostatic resonator 10 is simplified, the production cycle is shortened, and the production cost is reduced.
[0090] The above descriptions are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structural or equivalent process transformations made using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. An electrostatic resonator, characterized in that: include: A first wafer, comprising a first anchor portion, a first electrode connection portion and a groove; wherein the first electrode connection portion is arranged on both sides of the first anchor portion, the groove is arranged on both sides of the first electrode connection portion, and the first anchor portion and the first electrical connection portion are spaced apart by the groove; A second wafer is bonded to the first wafer, and the groove and the second wafer are covered to form a cavity; the second wafer has a second anchor portion, a second electrode connecting portion, a resonant body, and a through hole; wherein the second anchor portion is connected to the first anchor portion to form an anchor, the first electrode connecting portion is connected to the second electrode connecting portion to form an electrode, the through hole passes through the second wafer to communicate with the cavity, and the resonant body is located on both sides of the second electrode connecting portion and is spaced apart from the anchor and the electrode through the through hole; The silicon oxide layer is arranged on the anchor point, the electrode, the side wall of the resonator and the inner wall of the cavity.
2. The electrostatic resonator according to claim 1, characterized in that The first wafer further includes a through silicon via, which is located at the bottom of the cavity and penetrates the first wafer to communicate with the cavity.
3. The electrostatic resonator according to claim 1, characterized in that The electrostatic resonator further includes a capping layer connected to a side of the second wafer facing away from the first wafer.
4. The electrostatic resonator according to claim 1, characterized in that The electrostatic resonator further includes a bonding layer disposed on the anchor point.
5. A method for preparing an electrostatic resonator, characterized in that: For preparing the electrostatic resonator according to any one of claims 1 to 4, comprising: The first wafer is patterned to form a first anchor portion, a first electrode connection portion and a groove; the first electrode connection portion is arranged on both sides of the first anchor portion, the groove is arranged on both sides of the first electrode connection portion, and the first anchor portion and the first electrical connection portion are spaced apart by the groove; Bonding the second wafer to the first wafer, wherein the groove and the second wafer are covered to form a cavity; The second wafer is patterned to form a second anchor portion, a second electrode connection portion, a resonant body, and a through hole; wherein the second anchor portion is connected with the first anchor portion to form an anchor point, the first electrode connection portion is connected with the second electrode connection portion to form an electrode, the through hole penetrates the second wafer to communicate with the cavity, and the resonant body is located at both sides of the second electrode connection portion and is spaced apart from the anchor point and the electrode through the through hole; A silicon oxide layer is formed on the second wafer, wherein the silicon oxide layer is located on the anchor point, the electrode, the side wall of the resonator, and the inner wall of the cavity.
6. The method for preparing an electrostatic resonator according to claim 5, characterized in that: Before patterning the first wafer, the method further includes: providing a first wafer; forming a first hard mask on the first wafer; performing patterning on the first hard mask to expose a portion of the first wafer; Performing patterning on the exposed first wafer to form silicon grooves; The first hard mask is removed.
7. The method for preparing an electrostatic resonator according to claim 5, characterized in that: The process of patterning the first wafer includes: forming a second hard mask on the first wafer; performing patterning on the second hard mask to expose a portion of the first wafer; The exposed portion of the first wafer is patterned to form a first anchor portion, a first electrode connection portion, a groove, and a first support portion; the first electrode connection portion is disposed on both sides of the first anchor portion, the first support portion is located on a side of the first electrical connection portion away from the first anchor portion, and the first electrode connection portion is spaced from the first anchor portion and the first support portion by the groove; The second hard mask is removed.
8. The method for preparing an electrostatic resonator according to claim 7, characterized in that: After bonding the second wafer to the first wafer and before patterning the second wafer, the method further includes: forming a bonding film and a third hard mask on a surface of the second wafer facing away from the first wafer; performing patterning on the third hard mask film to expose a portion of the bonding film; The bonding film is patterned to form a bonding layer that exposes a portion of the second wafer.
9. The method for preparing an electrostatic resonator according to claim 8, characterized in that: The patterning process of the second wafer includes: forming a fourth hard mask on the bonding layer and the second wafer; performing patterning on the fourth hard mask to expose a portion of the second wafer; The second wafer is patterned to form a second anchor portion, a second electrode connecting portion, a resonant body, a through hole and a second supporting portion; wherein the second anchor portion is connected to the first anchor portion to form an anchor point, the first electrode connecting portion is connected to the second electrode connecting portion to form an electrode, the second supporting portion and the first supporting portion form a supporting body, the through hole passes through the second wafer to communicate with the cavity, the resonant body is located on both sides of the second electrode connecting portion and is spaced apart from the anchor point, the electrode and the supporting body through the through hole.
10. The method for preparing an electrostatic resonator according to claim 6, characterized in that: After patterning the second wafer and before forming a silicon oxide layer on the second wafer, the method further includes: A thinning process is performed on a side of the first wafer facing away from the second wafer, and the side of the first wafer is thinned to the bottom of the silicon groove, so that a through silicon via is formed in the silicon groove.