Semiconductor memory device and manufacturing method thereof

Abstract

The embodiment of the invention relates to a semiconductor memory device and a manufacturing method thereof. A semiconductor memory device according to an embodiment includes: a first stacked body in which a first insulating layer, a first conductive layer, and a second insulating layer are stacked in this order in a first direction; a semiconductor film provided spaced apart from the first laminate and extending in the first direction; a tunnel insulating film provided between the first laminate and the semiconductor film and extending in the first direction; a first barrier insulating film provided between the first conductive layer and the tunnel insulating film; and a first charge storage film having: a first portion provided between the tunnel insulating film and the first barrier insulating film; a second portion provided between the tunnel insulating film and the first insulating layer and connected to the first portion; and a third portion provided between the tunnel insulating film and the second insulating layer and connected to the first portion. And a metal oxide or a metal nitrogen oxide.

Description

[0001] Related Applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-100615 (filing date: June 20, 2023). This application incorporates all the contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the same. Background Art

[0004] Large-capacity nonvolatile memories are being developed continuously. Such large-capacity nonvolatile memories can perform low-voltage and low-current operations, high-speed switching, and miniaturization and high integration of storage cells.

[0005] In a memory cell array of a large-capacity nonvolatile memory, a plurality of metal wirings called bit lines and word lines are arranged. Voltage is applied to the bit lines and word lines connected to the cells, and data is written to a memory cell corresponding to the bit lines and word lines. A semiconductor memory device having a three-dimensional arrangement of memory cells having a laminated film in which a conductive layer and an insulating layer are alternately laminated to form the word lines is proposed. Summary of the invention

[0006] The semiconductor storage device of the embodiment comprises: a first stacked body, in which a first insulating layer, a first conductive layer and a second insulating layer are stacked in sequence in a first direction; a semiconductor film, which is separated from the first stacked body and extends in the first direction; a tunnel insulating film, which is arranged between the first stacked body and the semiconductor film and extends in the first direction; a first blocking insulating film, which is arranged between the first conductive layer and the tunnel insulating film; and a first charge storage film, which comprises: a first part, which is arranged between the tunnel insulating film and the first blocking insulating film; a second part, which is arranged between the tunnel insulating film and the first insulating layer and connected to the first part; and a third part, which is arranged between the tunnel insulating film and the second insulating layer and connected to the first part; and contains a metal oxide or a metal nitride oxide.

[0007] According to this embodiment, a semiconductor memory device having a high charge retention characteristic can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a block diagram of the semiconductor memory device according to the first embodiment.

[0009] Figure 2 This is an equivalent circuit diagram of a memory cell array of the semiconductor memory device according to the first embodiment.

[0010] Figure 3This is a schematic cross-sectional view of a main part of the semiconductor memory device according to the first embodiment.

[0011] Figure 4 It is a schematic cross-sectional view showing the method for manufacturing the semiconductor memory device according to the first embodiment.

[0012] Figure 5 It is a schematic cross-sectional view showing the method for manufacturing the semiconductor memory device according to the first embodiment.

[0013] Figure 6 It is a schematic cross-sectional view showing the method for manufacturing the semiconductor memory device according to the first embodiment.

[0014] Figure 7 It is a schematic cross-sectional view showing the method for manufacturing the semiconductor memory device according to the first embodiment.

[0015] Figure 8 It is a schematic cross-sectional view showing the method for manufacturing the semiconductor memory device according to the first embodiment.

[0016] Fig. 9 It is a schematic cross-sectional view showing the method for manufacturing the semiconductor memory device according to the first embodiment.

[0017] Fig.10 (a) and (b) are schematic cross-sectional views of the main parts of the semiconductor memory device according to the second embodiment.

[0018] Fig.11 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the second embodiment. DETAILED DESCRIPTION

[0019] Hereinafter, the embodiments will be described using the drawings. In the drawings, the same or similar parts are denoted by the same or similar reference numerals.

[0020] In this specification, in order to indicate the positional relationship of parts, the upper direction of the drawings is described as "up", and the lower direction of the drawings is described as "down". In this specification, the concepts of "up" and "down" are not necessarily terms that indicate the relationship with the direction of gravity.

[0021] In the qualitative analysis and quantitative analysis of the chemical composition of the components constituting the semiconductor memory device in this specification, for example, secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectrometry (EDX), or electron energy loss spectrometry (EELS) can be used.

[0022] Furthermore, the thickness of components constituting the semiconductor memory device, the distance between components, and the like can be measured using, for example, a transmission electron microscope (TEM).

[0023] In addition, the constituent materials of the parts constituting the semiconductor storage device and the size comparison of the existence ratios can be carried out, for example, using a transmission electron microscope, X-ray diffraction analysis (X-ray Diffraction: XRD), electron beam diffraction analysis (Electron Beam Diffraction: EBD), X-ray photoelectron spectroscopy analysis (X-ray Photoelectron Spectroscopy: XPS), or synchronous X-ray scattering analysis (Synchrotron Radiation X-ray Absorption Fine Structure: XAFS).

[0024] (First embodiment)

[0025] The semiconductor storage device of this embodiment comprises: a first stacked body, in which a first insulating layer, a first conductive layer and a second insulating layer are stacked in sequence in a first direction; a semiconductor film, which is separated from the first stacked body and extends in the first direction; a tunnel insulating film, which is arranged between the first stacked body and the semiconductor film and extends in the first direction; a first blocking insulating film, which is arranged between the first conductive layer and the tunnel insulating film; and a first charge storage film, which comprises: a first part, which is arranged between the tunnel insulating film and the first blocking insulating film; a second part, which is arranged between the tunnel insulating film and the first insulating layer and connected to the first part; and a third part, which is arranged between the tunnel insulating film and the second insulating layer and connected to the first part; and contains a metal oxide or a metal nitride oxide.

[0026] The manufacturing method of the semiconductor memory device of the present embodiment forms a second stacked body in which a first insulating layer, a first sacrificial layer and a second insulating layer are sequentially stacked in a first direction; an opening portion is formed which penetrates the second stacked body and extends in the first direction, so that the side surface of the first insulating layer, the side surface of the first sacrificial layer and the side surface of the second insulating layer are exposed in the opening portion; a first film containing N (nitrogen) or Si (silicon) is formed on the side surface of the first sacrificial layer; a first charge storage film having a first portion, a second portion and a third portion and containing a metal oxide or a metal nitride oxide is formed; The stacked films are formed as follows: the second part is adjacent to the first insulating layer and the first film, the third part is adjacent to the second insulating layer and the first film, the first film is arranged between the first sacrificial layer and the first part, and the first part is connected to the second part and the third part; the first film is oxidized to form a first blocking insulating film; a tunnel insulating film extending in the first direction is formed in a manner in which the first blocking insulating film is arranged between the second stacked body and the tunnel insulating film; a semiconductor film extending in the first direction is formed in a manner in which the tunnel insulating film is arranged between the second stacked body and the semiconductor film.

[0027] The following describes the overall configuration of semiconductor storage device 100. Semiconductor storage device 100 of the present embodiment is a NAND flash memory capable of storing data in a nonvolatile manner. Figure 1 2 is a block diagram of a semiconductor memory device 100 according to the present embodiment.

[0028] The semiconductor memory device 100 includes a memory cell array 90 , a row decoder 91 , a column decoder 98 , a sense amplifier 99 , an input / output circuit 94 , a command register 95 , an address register 96 , a sequencer (control circuit) 97 , and the like.

[0029] The memory cell array 90 includes j blocks BLK0 to BLK(j-1). j is an integer greater than 1. Each of the multiple blocks BLK includes multiple memory cell transistors. The memory cell transistor includes a memory cell that can be electrically rewritten. The memory cell array 90 includes multiple bit lines, multiple strip lines, and source lines in order to control the voltage applied to the memory cell transistor. The specific structure of the block BLK will be described later.

[0030] The row decoder 91 receives the row address from the address register 96 and decodes the row address. The row decoder 91 selects a word line based on the decoded row address. Then, the row decoder 91 transmits a plurality of voltages required for write, read, and erase operations to the memory cell array 90 .

[0031] The column decoder 98 receives the column address from the address register 96 and decodes the column address. The column decoder 98 performs a selection operation of a bit line and the like based on the decoded column address.

[0032] The sense amplifier 99 detects and amplifies data read from the memory cell transistor to the bit line during a read operation, and transmits write data to the bit line during a write operation.

[0033] The input / output circuit 94 is connected to an external device (host device) via a plurality of input / output lines (DQ lines). The input / output circuit 94 receives a command CMD and an address ADD from the external device. The command CMD received by the input / output circuit 94 is sent to a command register 95. The address ADD received by the input / output circuit 94 is sent to an address register 96. In addition, the input / output circuit 94 transmits and receives data DAT to and from the external device.

[0034] The sequencer 97 receives a control signal CNT from an external device. The control signal CNT includes a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn. The "n" in the signal name indicates that the low level is valid. The sequencer 97 controls the operation of the entire semiconductor memory device 100 based on the command CMD held by the command register 95 and the control signal CNT.

[0035] Figure 2 2 is an equivalent circuit diagram of the semiconductor memory device 100 according to the present embodiment.

[0036] like Figure 2 As shown, the semiconductor memory device 100 includes a plurality of word lines WL, a common source line CSL, a source select gate line SGS, a plurality of drain select gate lines SGD, a plurality of bit lines BL, and a plurality of memory strings MS.

[0037] The memory string MS includes a source selection transistor STS, a plurality of memory cell transistors MT, and a drain selection transistor STD which are connected in series between a common source line CSL and a bit line BL.

[0038] In addition, the number of word lines WL, the number of bit lines BL, the number of memory strings MS, and the number of drain select gate lines SGD are not limited to Figure 2 The number of

[0039] Here, an X direction, a Y direction perpendicular to the X direction, and a Z direction perpendicular to the X direction and the Y direction are defined. The Z direction is an example of a first direction. The X direction is an example of a second direction. The Y direction is an example of a second direction.

[0040] Figure 3 It is a schematic cross-sectional view of a main part of semiconductor memory device 100 according to the present embodiment.

[0041] The first insulating layer 10, the first conductive layer 20, the second insulating layer 12, the second conductive layer 24, and the third insulating layer 14 are sequentially stacked in the Z direction. That is, the insulating layers and the conductive layers are alternately stacked in the Z direction. Thus, the first stacked body S1 is provided. In addition, the first stacked body S1 may also have other insulating layers and conductive layers. In this case, in the first stacked body S1, a plurality of insulating layers and a plurality of conductive layers are stacked one by one in the Z direction.

[0042] The first insulating layer 10, the second insulating layer 12, and the third insulating layer 14 include an insulating material. The first insulating layer 10, the second insulating layer 12, and the third insulating layer 14 include, for example, silicon oxide.

[0043] The first conductive layer 20 and the second conductive layer 24 include a conductive material. For example, the first conductive layer 20 and the second conductive layer 24 include tungsten, titanium nitride, or copper. In addition, the first conductive layer 20 and the second conductive layer 24 may also include other conductive materials such as metals, metal semiconductor compounds, or semiconductors.

[0044] The memory column H1 penetrates the first stacked body S1 in the Z direction. A core insulating film 2, a semiconductor film 3, a tunnel insulating film 4, a first insulating film 5, a second insulating film 6, a third insulating film 7, a first blocking insulating film 30, a second blocking insulating film 32, a first charge storage film 40, and a second charge storage film 50 are provided in the memory column H1.

[0045] The core insulating film 2 extends in the Z direction. The core insulating film 2 includes, for example, silicon oxide.

[0046] The semiconductor film 3 is provided around the core insulating film 2 in the memory pillar H1. The semiconductor film 3 extends in the Z direction. The semiconductor film 3 functions as a channel of the memory pillar H1. The semiconductor film 3 includes a semiconductor material such as polycrystalline silicon.

[0047] The tunnel insulating film 4 is provided around the semiconductor film 3. The tunnel insulating film 4 is an insulating film that allows current to flow when a predetermined voltage is applied, although it has insulating properties. The tunnel insulating film 4 is made of, for example, silicon nitride.

[0048] The first blocking insulating film 30 is provided between the first conductive layer 20 and the tunnel insulating film 4. In addition, a portion of the first blocking insulating film 30 is provided across between the first insulating layer 10 and the tunnel insulating film 4 and between the second insulating layer 12 and the tunnel insulating film 4. The first blocking film 30 is a film that suppresses the flow of charges between the first conductive layer 20 and the tunnel insulating film 4. The first blocking insulating film 30 includes, for example, oxide or oxynitride. The first blocking insulating film 30 includes, for example, silicon oxide or silicon oxynitride. The first blocking insulating film 30 is a film that suppresses the flow of charges between the first charge storage film 40 and the first conductive layer 20.

[0049] The second blocking insulating film 32 is provided between the second conductive layer 24 and the tunnel insulating film 4. In addition, a portion of the second blocking insulating film 32 is provided across between the second insulating layer 12 and the tunnel insulating film 4 and between the third insulating layer 14 and the tunnel insulating film 4. The second blocking insulating film 32 is a film that suppresses the flow of charges between the second conductive layer 24 and the tunnel insulating film 4. The second blocking insulating film 32 includes, for example, oxide or oxynitride. The second blocking insulating film 32 includes, for example, silicon oxide or silicon oxynitride. The second blocking insulating film 32 is a film that suppresses the flow of charges between the second charge storage film 50 and the second conductive layer 24.

[0050] The first charge storage film 40 includes a first portion 42, a second portion 44, and a third portion 46. The first portion 42 is provided between the tunnel insulating film 4 and the first blocking insulating film 30. The second portion 44 is provided between the tunnel insulating film 4 and the first insulating layer 10, and is connected to the first portion 42. The third portion 46 is provided between the tunnel insulating film 4 and the second insulating layer 12, and is connected to the first portion 42. The first charge storage film 40 is a film having a material capable of storing charges.

[0051] The second charge storage film 50 includes a sixth portion 52, a seventh portion 54, and an eighth portion 56. The sixth portion 52 is provided between the tunnel insulating film 4 and the second blocking insulating film 32. The seventh portion 54 is provided between the tunnel insulating film 4 and the second insulating layer 12, and is connected to the sixth portion 52. The eighth portion 56 is provided between the tunnel insulating film 4 and the third insulating layer 14, and is connected to the sixth portion 52. The second charge storage film 50 is a film having a material capable of storing charges.

[0052] The first charge storage film 40 and the second charge storage film 50 contain metal oxide or metal oxynitride. This is because metal oxide or metal oxynitride has a high charge retention property.

[0053] The first charge storage film 40 and the second charge storage film 50 preferably contain at least one first element selected from the group consisting of Al (aluminum), Hf (hafnium), Zr (zirconium), Ti (titanium), V (vanadium), Ta (tantalum) and Nb (niobium), and may be an oxide or oxynitride of the first element. For example, when the first element is Hf, the first charge storage film 40 and the second charge storage film 50 may be HfO or HfON, and when the first element is Zr, the first charge storage film 40 and the second charge storage film 50 may be ZrO or ZrON.

[0054] Alternatively, the first charge storage film 40 and the second charge storage film 50 preferably contain at least one second element selected from the group consisting of N (nitrogen), Si (silicon), Al (aluminum) and lanthanide elements, and Hf or Zr. The first charge storage film 40 and the second charge storage film 50 may be oxides or oxynitrides such as HfAlO, HfAlON, ZrAlO or ZrAlON. Furthermore, the first charge storage film 40 and the second charge storage film 50 preferably contain 20 atomic % or less of the second element.

[0055] The first insulating film 5 is provided between the tunnel insulating film 4 and the first insulating layer 10. The second insulating film 6 is provided between the tunnel insulating film 4 and the second insulating layer 12. The third insulating film 7 is provided between the tunnel insulating film 4 and the third insulating layer 14. The second insulating film 6 is provided between the third portion 46 and the seventh portion 54 in the Z direction. The first insulating film 5, the second insulating film 6, and the third insulating film 7 include insulating materials. The first insulating film 5, the second insulating film 6, and the third insulating film 7 include, for example, silicon oxide. The first insulating film 5, the second insulating film 6, and the third insulating film 7 are films buried between the charge storage films in the Z direction.

[0056] The third barrier insulating film 16 is provided between the first conductive layer 20 and the first insulating layer 10, between the first conductive layer 20 and the first barrier insulating film 30, and between the first conductive layer 20 and the second insulating layer 12. The third barrier insulating film 16 includes a metal insulating material such as aluminum oxide.

[0057] The fourth barrier insulating film 18 is provided between the second conductive layer 24 and the second insulating layer 12, between the second conductive layer 24 and the second barrier insulating film 32, and between the second conductive layer 24 and the third insulating layer 14. The fourth barrier insulating film 18 includes a metal insulating material such as aluminum oxide.

[0058] Furthermore, a barrier metal (not shown) is provided between the first conductive layer 20 and the third barrier insulating film 16 and between the second conductive layer 24 and the fourth barrier insulating film 18. The barrier metal contains, for example, titanium nitride.

[0059] In addition, Figure 3 In the figure, it is shown Figure 2 One of the memory strings MS shown is shown. The semiconductor memory device 100 includes a plurality of memory pillars H1.

[0060] exist Figure 3 In FIG. 1 , a portion surrounded by a dotted line is a portion corresponding to one memory cell MC.

[0061] In addition, a substrate (not shown) is provided under the first stacked body S1. The substrate (not shown) is, for example, a semiconductor wafer or an SOI wafer. A common source line CSL (not shown), a source selection gate line SGS, and a plurality of source selection transistors STS (not shown) are provided between the first stacked body S1 and the substrate (not shown).

[0062] Furthermore, on the first stacked body S1, for example, a plurality of drain selection gate lines SGD, a plurality of bit lines BL, and a plurality of drain selection transistors STD (not shown) are provided.

[0063] Figures 4 to 9 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the present embodiment.

[0064] First, for example, a common source line CSL, a source selection gate line SGS, and a plurality of source selection transistors STS, which are not shown in the figure, are formed on a substrate, which is not shown in the figure.

[0065] Next, for example, by plasma CVD (Plasma-enhanced Chemical Vapor Deposition), a second stacked body S2 is formed on the common source line CSL, the source selection gate line SGS, and the plurality of source selection transistors STS, in which the first insulating layer 10, the first sacrificial layer 70, the second insulating layer 12, the second sacrificial layer 72, and the third insulating layer 14 are stacked in sequence in the Z direction. Here, the first insulating layer 10, the second insulating layer 12, and the third insulating layer 14 include, for example, silicon oxide. In addition, the first sacrificial layer 70 and the second sacrificial layer 72 include, for example, silicon nitride ( Figure 4 ).

[0066] Next, an opening H2 (through hole) is formed, for example, by RIE (Reactive Ion Etching) to penetrate the second laminate S2 in the Z direction and extend in the Z direction. Thus, the side surface 11 of the first insulating layer, the side surface 71 of the first sacrificial layer, the side surface 13 of the second insulating layer, the side surface 73 of the second sacrificial layer, and the side surface 15 of the third insulating layer are exposed in the opening H2 ( Figure 5 ).

[0067] Next, the adsorption inhibitor I is adsorbed on the side surface 11 of the first insulating layer, the side surface 13 of the second insulating layer, and the side surface 15 of the third insulating layer. The adsorption inhibitor I is not particularly limited, and for example, C (carbon) or hydrocarbons can be used.

[0068] Next, for example, by selective growth (Area Selective Deposition: ASD, area selective deposition), a first film 80 including N (nitrogen) or Si (silicon) is formed on the side 71 of the first sacrificial layer. In addition, for example, by selective growth, a second film 82 including N (nitrogen) or Si (silicon) is formed on the side 73 of the second sacrificial layer. For example, by selective CVD, a first film 80 and a second film 82 including silicon nitride are formed. Here, a portion of the first film 80 is sometimes formed adjacent to the side 11 of the first insulating layer and the side 13 of the second insulating layer. In addition, a portion of the second film 82 is sometimes formed adjacent to the side 13 of the second insulating layer and the side 15 of the third insulating layer. The first film 80 and the second film 82 are formed to be separated from each other ( Figure 6 ).

[0069] In addition, in the following figures, illustration of the adsorption inhibitor I is omitted.

[0070] Next, for example, by selective growth, the first charge storage film 40 having the first portion 42, the second portion 44, and the third portion 46 and containing a metal oxide or a metal oxynitride is formed. Here, the first charge storage film 40 is formed in such a manner that the second portion 44 is adjacent to the first insulating layer 10 and the first film 80, the third portion 46 is adjacent to the second insulating layer 12 and the first film 80, the first film 80 is provided between the first sacrificial layer 70 and the first portion 42, and the first portion 42 is connected to the second portion 44 and the third portion 46.

[0071] In addition, for example, by selective growth, the second charge storage film 50 including the sixth portion 52, the seventh portion 54, and the eighth portion 56 and containing a metal oxide or a metal oxynitride is formed. Here, the second charge storage film 50 is formed in such a manner that the seventh portion 54 is adjacent to the second insulating layer 12 and the second film 82, the eighth portion 56 is adjacent to the third insulating layer 14 and the second film 82, the second film 82 is provided between the second sacrificial layer 72 and the sixth portion 52, and the sixth portion 52 is connected to the seventh portion 54 and the eighth portion 56.

[0072] Next, the first film 80 is oxidized to form the first blocking insulating film 30. In addition, the second film 82 is oxidized to form the second blocking insulating film 32. For example, a gas containing oxygen is supplied into the opening H2, and the first charge storage film 40 is used as a catalyst to oxidize the first film 80 via the first charge storage film 40, thereby forming the first blocking insulating film 30. In addition, a gas containing oxygen is supplied into the opening H2, and the second charge storage film 50 is used as a catalyst to oxidize the second film 82 via the second charge storage film 50, thereby forming the second blocking insulating film 32 ( Figure 8 ).

[0073] Next, a film containing, for example, silicon oxide is formed on the side surface 11 of the first insulating layer, the lower surface of the second portion 44, the side surface of the first portion 42, the side surface 13 of the second insulating layer, the side surface of the sixth portion 52, and the upper surface of the eighth portion 56. Next, a portion of the film containing silicon oxide is removed by, for example, RIE so that the side surface of the first portion 42 and the side surface of the sixth portion 52 are exposed. Thus, the first insulating film 5 is formed on the side surface 11 of the first insulating layer. In addition, the second insulating film 6 is formed on the side surface 13 of the second insulating layer. In addition, the third insulating film 7 ( Fig. 9 ).

[0074] Next, in the opening H2, for example, by ALD (Atomic Layer Deposition), a tunnel insulating film 4 and a portion of the semiconductor film 3 are sequentially formed. Next, for example, by etching, a portion of the tunnel insulating film 4 and the semiconductor film 3 are removed from the bottom of the opening H2. Next, in the opening H2, for example, the remaining portion of the semiconductor film 3 and the core insulating film 2 are sequentially formed by ALD. As a result, the tunnel insulating film 4, the semiconductor film 3, and the core insulating film 2 are sequentially formed in the opening H2.

[0075] In other words, in the opening H2, the tunnel insulating film 4 extending in the first direction is formed in such a manner that the first barrier insulating film 30 and the second barrier insulating film 32 are provided between the second laminate S2 and the tunnel insulating film 4. Next, in the opening H2, the semiconductor film 3 extending in the first direction is formed in such a manner that the tunnel insulating film 4 is provided between the second laminate S2 and the semiconductor film 3. Next, in the opening H2, the core insulating film 2 extending in the first direction is formed in such a manner that the semiconductor film 3 is provided between the second laminate S2 and the core insulating film 2.

[0076] Next, a slit (not shown) is formed in the second laminate S2. Next, a chemical solution such as phosphoric acid is supplied using the slit to remove the first sacrificial layer 70 and the second sacrificial layer 72. Next, the third barrier insulating film 16 and the first conductive layer 20 are sequentially formed on the portion where the first sacrificial layer 70 is removed. Furthermore, the fourth barrier insulating film 18 and the second conductive layer 24 are sequentially formed on the portion where the second sacrificial layer 72 is removed. In this way, the first sacrificial layer 70 is replaced by the third barrier insulating film 16 and the first conductive layer 20. Furthermore, the second sacrificial layer 72 is replaced by the fourth barrier insulating film 18 and the second conductive layer 24. Thus, the first laminate S1 is formed.

[0077] Next, a plurality of drain selection gate lines SGD, a plurality of bit lines BL, and a plurality of drain selection transistors STD (not shown) are formed on the second stacked body S2 , thereby obtaining the semiconductor memory device 100 of the present embodiment.

[0078] Next, the effects of the semiconductor memory device of this embodiment will be described.

[0079] The film thickness of the insulating layer in the Z direction and the film thickness of the conductive layer in the Z direction in the first stacked body S1 tend to become thinner due to the high storage density of the semiconductor memory device. In this case, the interval between the adjacent memory cells MC in the Z direction becomes narrower. Therefore, interference and charge transfer between the adjacent memory cells MC in the Z direction may become a problem.

[0080] To solve the above problem, it is conceivable to reduce the thickness of the charge storage film in the X direction or the Y direction. However, when silicon nitride is used as the charge storage film, when the thickness in the X direction or the Y direction becomes thinner than about 5 nm, for example, the charge storage amount decreases sharply.

[0081] Therefore, it is considered to use a film including a metal oxide or a metal nitride oxide extending in the Z direction as the charge storage film. However, there is a problem that charge transfer occurs between memory cells MC adjacent to each other in the Z direction.

[0082] Therefore, the semiconductor storage device of this embodiment comprises: a first blocking insulating film, arranged between the first conductive layer and the tunnel insulating film; and a first charge storage film, comprising: a first part, arranged between the tunnel insulating film and the first blocking insulating film; a second part, arranged between the tunnel insulating film and the first insulating layer, connected to the first part; and a third part, arranged between the tunnel insulating film and the second insulating layer, connected to the first part, and containing a metal oxide or a metal nitride oxide.

[0083] According to the semiconductor memory device of this embodiment, the charge storage film is divided between the memory cells MC. Therefore, interference and charge transfer between adjacent memory cells MC in the Z direction are suppressed. In addition, the semiconductor memory device of this embodiment can ensure a high electrostatic capacitance. Therefore, a semiconductor memory device with a high charge retention characteristic can be provided.

[0084] The first charge storage film 40 and the second charge storage film 50 preferably contain at least one first element selected from the group consisting of Al (aluminum), Hf (hafnium), Zr (zirconium), Ti (titanium), V (vanadium), Ta (tantalum), and Nb (niobium). This is to make the first charge storage film 40 and the second charge storage film 50 have higher charge retention characteristics.

[0085] In addition, the first charge storage film 40 and the second charge storage film 50 preferably contain at least one second element selected from the group consisting of N (nitrogen), Si (silicon), Al (aluminum) and lanthanide elements, and Hf or Zr. Furthermore, the first charge storage film 40 and the second charge storage film 50 preferably contain 20 atomic % or less of the second element. This is to make the first charge storage film 40 and the second charge storage film 50 have higher charge retention characteristics.

[0086] In the method for manufacturing a semiconductor memory device of the present embodiment, the first film 80 is oxidized to form the first blocking insulating film 30. For example, the first charge storage film 40 is used as a catalyst, and the first film 80 is oxidized via the first charge storage film 40 to form the first blocking insulating film 30. Thus, a blocking insulating film can be formed, and a memory cell MC in which the charge storage film is divided in the Z direction can be formed.

[0087] It is preferable to adsorb the adsorption inhibitor I on the side surface 11 of the first insulating layer, the side surface 13 of the second insulating layer, and the side surface 15 of the third insulating layer. This is to prevent the formation of a film containing a metal oxide or a metal oxynitride on the side surface 11 of the first insulating layer, the side surface 13 of the second insulating layer, and the side surface 15 of the third insulating layer.

[0088] According to the semiconductor memory device of this embodiment, a semiconductor memory device having a high charge retention characteristic can be provided.

[0089] (Second embodiment)

[0090] The semiconductor memory device of the present embodiment is different from the semiconductor memory device of the first embodiment in that the first conductive layer has a fourth portion disposed between the first insulating layer and the second insulating layer, and a first conductive layer disposed between the second portion and the third portion and connected to the fourth portion, and the film thickness in the first direction is thicker than the film thickness of the fourth portion in the first direction. The description of the contents repeated in the first embodiment is omitted here.

[0091] Fig.10 It is a schematic cross-sectional view of a main part of the semiconductor memory device 110 according to the present embodiment. Fig.10 (a) is a schematic cross-sectional view of a main part of the semiconductor memory device 110 according to the present embodiment. Fig.10 (b) is a schematic cross-sectional view of the main part of the semiconductor memory device 110 of this embodiment, near the first conductive layer 20 .

[0092] The first conductive layer 20 includes a fourth portion 21 provided between the first insulating layer 10 and the second insulating layer 12, and a fifth portion 22 provided between the second portion 44 and the third portion 46. The fifth portion 22 is connected to the fourth portion 21. The film thickness of the fifth portion 22 in the Z direction is thicker than the film thickness of the fourth portion 21 in the Z direction.

[0093] The second conductive layer 24 includes a ninth portion 25 provided between the second insulating layer 12 and the third insulating layer 14, and a tenth portion 26 provided between the seventh portion 54 and the eighth portion 56. The tenth portion 26 is connected to the ninth portion 25. The film thickness of the tenth portion 26 in the Z direction is thicker than the film thickness of the ninth portion 25 in the Z direction.

[0094] Fig.11 Schematic cross-sectional views showing a method for manufacturing semiconductor memory device 110 according to the present embodiment.

[0095] The manufacturing method up to the manufacturing of the first charge storage film 40 and the second charge storage film 50 is the same as the manufacturing method of the semiconductor memory device 110 according to the first embodiment.

[0096] In the method for manufacturing the semiconductor memory device 110 of the present embodiment, when the first film 80 is oxidized to form the first blocking insulating film 30, a portion of the first film 80 is left between the first sacrificial layer 70 and the first blocking insulating film 30. In other words, when the first film 80 is oxidized to form the first blocking insulating film 30, the first film 80 is oxidized in such a manner that a portion of the first film 80 is provided between the first sacrificial layer 70 and the first blocking insulating film 30.

[0097] At this time, the length of a portion of the first film 80 in the Z direction is longer than the length of the first sacrificial layer 70 in the Z direction.

[0098] Similarly, when the second film 82 is oxidized to form the second barrier insulating film 32, a portion of the second film 82 is left between the second sacrificial layer 72 and the second barrier insulating film 32. In other words, when the second film 82 is oxidized to form the second barrier insulating film 32, the second film 82 is oxidized in such a manner that a portion of the second film 82 is provided between the second sacrificial layer 72 and the second barrier insulating film 32.

[0099] At this time, the length of a portion of the second film 82 in the Z direction is longer than the length of the second sacrificial layer 72 in the Z direction.

[0100] Next, a portion of the first sacrificial layer 70 and the first film 80 is replaced with the third barrier insulating film 16 and the first conductive layer 20. Thus, the first conductive layer 20 having the fourth portion 21 and the fifth portion 22 is formed.

[0101] Furthermore, a part of the second sacrificial layer 72 and the second film 82 is replaced by the fourth barrier insulating film 18 and the second conductive layer 24. Thus, the second conductive layer 24 having the ninth portion 25 and the tenth portion 26 is formed.

[0102] The subsequent manufacturing method is the same as that of the semiconductor memory device according to the first embodiment.

[0103] When the first film 80 is oxidized to form the first barrier insulating film 30, a portion of the first sacrificial layer 70 may be oxidized. In particular, portions of the upper and lower surfaces of the first sacrificial layer 70 that are in contact with the first barrier film 30 may be oxidized. Therefore, when the first sacrificial layer 70 is replaced with the third barrier insulating film 16 and the first conductive layer 20, the length of the portion of the first conductive layer 20 that faces the first portion 42 in the X direction or the Y direction in the Z direction becomes shorter. Therefore, it is difficult to ensure a high electrostatic capacitance between the first portion 42 and the first conductive layer 20.

[0104] Therefore, in the semiconductor storage device of this embodiment, the first conductive layer 20 has: a fourth portion 21, which is arranged between the first insulating layer 10 and the second insulating layer 12; and a fifth portion 22, which is arranged between the second portion 44 and the third portion 46, connected to the fourth portion 21, and the film thickness in the Z direction is thicker than the film thickness of the fourth portion 21 in the Z direction.

[0105] Thus, a high electrostatic capacitance can be ensured between the first portion 42 and the fifth portion 22 .

[0106] In addition, it is considered that the film thickness of the plurality of insulating layers and the plurality of conductive layers in the first laminate S1 is reduced. In this case, in the manufacturing step, when the sacrificial layer is removed to replace the sacrificial layer with the conductive layer, the film thickness of the plurality of insulating layers is thin, so there is a concern that the strength cannot be ensured. By providing a part of the first film 80 between the first sacrificial layer 70 and the first barrier insulating film 30, the strength can be ensured in the manufacturing step.

[0107] According to the semiconductor memory device of this embodiment, it is also possible to provide a semiconductor memory device that can achieve high integration.

[0108] Although several embodiments and examples of the present invention have been described, these embodiments and examples are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in many other ways, and can be omitted, replaced, and changed in many ways without departing from the scope of the invention. These embodiments or their variations are included in the scope or purpose of the invention, and similarly, they are also included in the invention described in the scope of the patent application and its equivalent scope.

[0109] [Explanation of Symbols]

[0110] 3 Semiconductor films

[0111] 4 Tunnel insulation film

[0112] 101st insulation layer

[0113] 11 Side

[0114] 12 Second insulation layer

[0115] 13 Side

[0116] 143rd insulation layer

[0117] 15 Side

[0118] 16Third barrier insulating film

[0119] 201st conductive layer

[0120] 21 Part 4

[0121] 22 Part 5

[0122] 24 2nd conductive layer

[0123] 30 1st barrier insulating film

[0124] 32 2nd barrier insulating film

[0125] 401st charge storage film

[0126] 42 Part 1

[0127] 44 Part 2

[0128] 46 Part 3

[0129] 50 Second charge storage film

[0130] 52 Part 6

[0131] 54 Part 7

[0132] 56 Part 8

[0133] 701st Sacrificial Layer

[0134] 71 side

[0135] 72 Second Sacrificial Layer

[0136] 73 side

[0137] 80 1st Film

[0138] 100 Semiconductor storage device

[0139] 110 Semiconductor storage device

[0140] H2 opening

[0141] I adsorption inhibitor

[0142] S1 1st layer

[0143] S2: second layered body.

Claims

1. A semiconductor storage device comprising: A first laminated body, wherein a first insulating layer, a first conductive layer, and a second insulating layer are laminated in sequence in a first direction; A semiconductor film is disposed apart from the first stacked body and extends in the first direction; a tunnel insulating film, provided between the first stacked body and the semiconductor film, and extending in the first direction; a first barrier insulating film disposed between the first conductive layer and the tunnel insulating film; and The first charge storage film has: The first portion is disposed between the tunnel insulating film and the first barrier insulating film; the second portion is disposed between the tunnel insulating film and the first insulating layer and connected to the first portion; and a third portion, disposed between the tunnel insulating film and the second insulating layer, and connected to the first portion; and Contains metal oxides or metal oxynitrides.

2. The semiconductor memory device according to claim 1, wherein the first charge storage film contains at least one first element selected from the group consisting of Al (aluminum), Hf (hafnium), Zr (zirconium), Ti (titanium), V (vanadium), Ta (tantalum) and Nb (niobium).

3. The semiconductor memory device according to claim 1, wherein The first charge storage film comprises: at least one second element selected from the group consisting of N (nitrogen), Si (silicon), Al (aluminum) and lanthanide elements; and Hf or Zr. 4 . The semiconductor memory device according to claim 3 , wherein the first charge storage film contains 20 atomic % or less of the second element.

5. The semiconductor memory device according to claim 1, wherein The first conductive layer has: a fourth portion, disposed between the first insulating layer and the second insulating layer; and The fifth portion is provided between the second portion and the third portion, is connected to the fourth portion, and has a film thickness in the first direction thicker than a film thickness of the fourth portion in the first direction.

6. The semiconductor memory device according to claim 1, wherein The first laminate comprises the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer, and the third insulating layer laminated in sequence in the first direction; The semiconductor storage device further comprises: a second barrier insulating film disposed between the second conductive layer and the tunnel insulating film and spaced apart from the first barrier insulating film; and The second charge storage film has: a sixth portion, provided between the tunnel insulating film and the second barrier insulating film; a seventh portion, disposed between the tunnel insulating film and the second insulating layer, and connected to the sixth portion; and An eighth portion is disposed between the tunnel insulating film and the third insulating layer and connected to the sixth portion; and The film contains a metal oxide or a metal nitride oxide and is provided apart from the first charge storage film.

7. The semiconductor memory device according to claim 1, further comprising: a third barrier insulating film provided between the first insulating layer, the second insulating layer, the first barrier insulating film, and the first conductive layer.

8. A method for manufacturing a semiconductor memory device, comprising forming a second laminated body in which a first insulating layer, a first sacrificial layer and a second insulating layer are sequentially laminated in a first direction; forming an opening portion penetrating the second laminate and extending in the first direction, so that the side surface of the first insulating layer, the side surface of the first sacrificial layer, and the side surface of the second insulating layer are exposed in the opening portion; forming a first film including N (nitrogen) or Si (silicon) on the side surface of the first sacrificial layer; A first charge storage film having a first portion, a second portion, and a third portion and containing a metal oxide or a metal oxynitride is formed as follows: the second portion is disposed adjacent to the first insulating layer and the first film, the third portion is disposed adjacent to the second insulating layer and the first film, the first film is disposed between the first sacrificial layer and the first portion, and the first portion is connected to the second portion and the third portion; oxidizing the first film to form a first barrier insulating film; forming a tunnel insulating film extending in the first direction in such a manner that the first barrier insulating film is provided between the second stacked body and the tunnel insulating film; and The semiconductor film extending in the first direction is formed so that the tunnel insulating film is provided between the second stacked body and the semiconductor film.

9. The method for manufacturing a semiconductor memory device according to claim 8, wherein after the first film is oxidized to form the first barrier insulating film, The first sacrificial layer is replaced with a first conductive layer.

10. The method for manufacturing a semiconductor memory device according to claim 9, wherein after the first film is oxidized to form the first barrier insulating film, Before replacing the first sacrificial layer with the first conductive layer, The third barrier insulating film is formed so as to be provided between the first insulating layer, the second insulating layer, the first barrier insulating film, and the first conductive layer.

11. The method for manufacturing a semiconductor memory device according to claim 8, wherein when the first film is oxidized to form the first barrier insulating film, A portion of the first film is provided between the first sacrificial layer and the first barrier insulating film. 12 . The method for manufacturing a semiconductor memory device according to claim 11 , wherein a length of the portion of the first film in the first direction is longer than a length of the first sacrificial layer in the first direction.

13. The method for manufacturing a semiconductor memory device according to claim 11, wherein after the first film is oxidized to form the first barrier insulating film, The first sacrificial layer and the portion of the first film are replaced with a first conductive layer.

14. The method for manufacturing a semiconductor memory device according to claim 13, wherein the first conductive layer comprises: a fourth portion, disposed between the first insulating layer and the second insulating layer; and The fifth portion is provided between the second portion and the third portion, is connected to the fourth portion, and has a film thickness in the first direction thicker than a film thickness of the fourth portion in the first direction.

15. The method for manufacturing a semiconductor memory device according to claim 8, wherein after forming the opening portion penetrating the second laminate and extending in the first direction to expose the side surface of the first insulating layer, the side surface of the first sacrificial layer, and the side surface of the second insulating layer, and Before forming the first film including N (nitrogen) or Si (silicon) on the side surface of the first sacrificial layer, an adsorption inhibitor is adsorbed on the side surface of the first insulating layer and the side surface of the second insulating layer.

16. The method for manufacturing a semiconductor memory device according to claim 8, wherein the first charge storage film contains at least one first element selected from the group consisting of Al (aluminum), Hf (hafnium), Zr (zirconium), Ti (titanium), V (vanadium), Ta (tantalum) and Nb (niobium).

17. The method for manufacturing a semiconductor memory device according to claim 8, wherein the first charge storage film contains at least one second element selected from the group consisting of N (nitrogen), Si (silicon), Al (aluminum) and lanthanide elements, and Hf or Zr.

18. The method for manufacturing a semiconductor memory device according to claim 17, wherein the first charge storage film contains 20 atomic % or less of the second element.

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