Digital phased array transceiver calibration method based on zero intermediate frequency architecture

Abstract

The present application discloses a digital phased array transceiver calibration method based on a zero intermediate frequency architecture, which relates to the field of radar communication technology. The invention discloses a digital phased array transceiver calibration method based on a zero intermediate frequency architecture, which includes: obtaining static amplitude and phase compensation values ​​of each transceiver channel in a digital phased array transceiver network relative to a calibration network; dynamically calibrating each of the transceiver channels based on a preset calibration network to obtain dynamic amplitude and phase compensation values ​​of each of the transceiver channels; superimposing the static amplitude and phase compensation values ​​with the dynamic amplitude and phase compensation values ​​to obtain the target amplitude and phase compensation values ​​required for the digital phased array in the transceiver network, and calibrating the digital phased array based on the target amplitude and phase compensation values. The calibration process not only calibrates the inherent phase difference and amplitude difference of each transceiver channel, but also calibrates the random phase difference and amplitude difference caused by environmental factors, thereby improving the accuracy of transceiver calibration of the digital phased array.

Description

Technical Field

[0001] The present application relates to the field of radar communication technology, and in particular to a digital phased array transceiver calibration method based on a zero intermediate frequency architecture. Background Art

[0002] Digital phased array uses digital signal processing technology to control the phase and amplitude of each element in the antenna array, thereby achieving precise control and scanning of the beam.

[0003] At present, digital phased arrays need to be calibrated to achieve amplitude and phase synchronization. The auxiliary calibration antenna is used to send and receive calibration signals to the channel to be calibrated. The digital signal processor calculates the amplitude and phase difference of the data of each transceiver channel to obtain the amplitude and phase compensation value. However, during the calibration process, environmental factors will have a great impact on the calibration accuracy, resulting in low accuracy in the transceiver calibration of the digital phased array. At the same time, during the calibration process, each transceiver channel is required to radiate signals to the outside, which poses a risk of information leakage and theft.

[0004] The above contents are only used to assist in understanding the technical solution of the present application and do not constitute an admission that the above contents are prior art. Summary of the invention

[0005] The main purpose of the present application is to provide a digital phased array transceiver calibration method based on a zero intermediate frequency architecture, aiming to solve the technical problem that the accuracy of the digital phased array transceiver calibration is low due to the great influence of environmental factors on the calibration accuracy, and there is a risk of radiation signal leakage and theft during array calibration.

[0006] To achieve the above objectives, the present application proposes a digital phased array transceiver calibration method based on a zero intermediate frequency architecture, the method comprising:

[0007] Obtaining static amplitude and phase compensation values ​​of each transceiver channel in the digital phased array transceiver network relative to the calibration network;

[0008] Dynamically calibrating each of the transceiver channels based on a preset calibration network to obtain dynamic amplitude and phase compensation values ​​of each of the transceiver channels;

[0009] The static amplitude-phase compensation value and the dynamic amplitude-phase compensation value are superimposed to obtain a target amplitude-phase compensation value required to be used by the digital phased array in a transceiver network, and the digital phased array is calibrated based on the target amplitude-phase compensation value.

[0010] In one embodiment, the digital phased array includes a power division switch unit, a signal processing unit, and a zero intermediate frequency chip, the dynamic amplitude and phase compensation value includes a receiving dynamic amplitude and phase compensation value, and the step of dynamically calibrating each of the transceiver channels based on a preset calibration network to obtain the dynamic amplitude and phase compensation value of each of the transceiver channels includes:

[0011] Controlling the power division switch unit to switch to a preset calibration network;

[0012] Detecting a calibration mode being triggered;

[0013] If the triggered calibration mode is receiving calibration, controlling the zero intermediate frequency chip to send a calibration signal to the signal processing unit through each of the transceiver channels;

[0014] The receiving dynamic amplitude and phase compensation value of each of the transceiver channels is obtained after the signal processing unit processes the calibration signal.

[0015] In one embodiment, the zero intermediate frequency chip includes a calibration chip and a channel chip, and the step of controlling the zero intermediate frequency chip to collect the calibration signal through each of the transceiver channels and send it to the signal processing unit includes:

[0016] Controlling the calibration chip to send a calibration signal to the preset calibration network, so that the preset calibration network performs power division on the calibration signal to obtain an identical power division signal;

[0017] Control each of the channel chips to collect the power division signals through the corresponding transceiver channel, and forward each of the power division signals to the signal processing unit.

[0018] In one embodiment, the dynamic amplitude and phase compensation value further includes a transmission dynamic amplitude and phase compensation value, and the step of dynamically calibrating each of the transceiver channels based on a preset calibration network to obtain the dynamic amplitude and phase compensation value of each of the transceiver channels includes:

[0019] If the triggered calibration mode is transmission calibration, the sampling period of the calibration chip is retrieved;

[0020] Based on the sampling period, controlling the calibration chip to sequentially collect the calibration signal sent by the channel chip through the corresponding transceiver channel;

[0021] Controlling the calibration chip to forward the calibration signal to the signal processing unit;

[0022] The transmission dynamic amplitude and phase compensation value of each of the transceiver channels is obtained, wherein the transmission dynamic amplitude and phase compensation value is obtained by the signal processing unit performing dynamic amplitude difference and phase difference analysis on the calibration signal.

[0023] In one embodiment, the power division switch unit includes a power divider, and the step of controlling the calibration chip to sequentially collect the calibration signal sent by the channel chip through the corresponding transceiver channel based on the sampling period includes:

[0024] Based on the sampling period, determining a target transceiver channel that currently needs to be calibrated from the transceiver channels;

[0025] Controlling the channel chip corresponding to the target transceiver channel, and sending the calibration signal to the calibration chip through the power division switch unit;

[0026] The calibration chip is controlled to collect calibration signals sent by the remaining channel chips through the corresponding transceiver channels according to the sampling period until calibration signals sent through all the transceiver channels are collected.

[0027] In one embodiment, the static amplitude and phase compensation value includes receiving a static compensation value, and the step of obtaining the static amplitude and phase compensation value of each transceiver channel in the digital phased array transceiver network relative to the calibration network includes:

[0028] If it is determined that the triggered calibration mode is receiving calibration, then controlling the power division switch unit in the digital phased array to be a calibration network;

[0029] Acquire a first receiving amplitude and phase detected by a preset vector network analyzer on each transceiver channel in a calibration network, wherein the first receiving amplitude and phase is measured by interconnecting an output end of the preset vector network analyzer with a receiving port of the calibration network and an input end of the preset vector network analyzer with a transceiver channel;

[0030] Control the power division switch unit to be a transceiver network, and obtain a second receiving amplitude phase obtained by detecting each transceiver channel in the transceiver network based on the preset vector network analyzer, wherein the second receiving amplitude phase is measured by interconnecting the output end of the preset vector network analyzer with the receiving port of the transceiver network and the input end of the preset vector network analyzer with the transceiver channel;

[0031] Based on the difference operation of the first receiving amplitude phase and the second receiving amplitude phase of each of the transceiver channels, the receiving static compensation value of each of the transceiver channels is obtained.

[0032] In one embodiment, the static amplitude and phase compensation value includes a transmission static compensation value, and the step of obtaining the static amplitude and phase compensation value of each transceiver channel in the digital phased array transceiver network relative to the calibration network further includes:

[0033] If it is determined that the triggered calibration mode is the transmission calibration, then controlling the output end of the preset vector network analyzer to be interconnected with the transceiver channel, and the input end of the preset vector network analyzer to be interconnected with the output port of the calibration network;

[0034] Acquire a first transmission amplitude and phase detected by the preset vector network analyzer on each of the transceiver channels in a calibration network;

[0035] Control the power division switch unit to be a transceiver network, and control the output end of the preset vector network analyzer to be interconnected with the transceiver channel, and the input end of the preset vector network analyzer to be interconnected with the output port of the transceiver network;

[0036] Acquire a second transmission amplitude and phase detected by the preset vector network analyzer on each of the transceiver channels in the transceiver network;

[0037] Based on the difference calculation between the first transmission amplitude and the second transmission amplitude of each of the transceiver channels, the transmission static compensation value of each of the transceiver channels is obtained.

[0038] In addition, to achieve the above-mentioned purpose, the present application also proposes a digital phased array transceiver calibration device based on a zero intermediate frequency architecture, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the digital phased array transceiver calibration method based on a zero intermediate frequency architecture as described above.

[0039] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the digital phased array transceiver calibration method based on the zero intermediate frequency architecture as described above are implemented.

[0040] In addition, to achieve the above-mentioned purpose, the present application also provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the steps of the digital phased array transceiver calibration method based on zero intermediate frequency architecture as described above.

[0041] One or more technical solutions proposed in this application have at least the following technical effects:

[0042] Since in a digital phased array, there is a certain fixed phase difference and fixed amplitude difference between the transceiver channels in the calibration network and the transceiver network, therefore, by statically calibrating each transceiver channel in the digital phased array, the fixed static amplitude and phase compensation value of each transceiver channel can be determined, and when the digital phased array is powered on, each zero intermediate frequency chip has a certain power-on random phase difference and random amplitude difference, so it is necessary to dynamically calibrate all transceiver channels through a preset calibration network to obtain the dynamic amplitude and phase compensation value between the transceiver channels of each zero intermediate frequency chip, and then superimpose the static amplitude and phase compensation value of each transceiver channel with the dynamic amplitude and phase compensation value to obtain the final target amplitude and phase compensation value, and perform calibration compensation during the actual signal transmission and reception process. Since the calibration network is performed in an internal loop, the calibration error caused by external environmental factors is reduced, thereby improving the accuracy of the amplitude and phase consistency of the digital phased array based on the zero intermediate frequency architecture during transmission and reception. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0045] Figure 1 This is the hardware interconnection block diagram of the digital phased array transceiver calibration system based on the zero intermediate frequency architecture of this application;

[0046] Figure 2 This is the hardware block diagram of the power division switch unit in the digital phased array transceiver calibration system based on the zero intermediate frequency architecture of this application;

[0047] Figure 3 A flowchart diagram of a first embodiment of a digital phased array transceiver calibration method based on a zero intermediate frequency architecture is provided for this application;

[0048] Figure 4 A flowchart diagram of Embodiment 2 of the digital phased array transceiver calibration method based on a zero intermediate frequency architecture provided in the present application;

[0049] Figure 5 A dynamic receiving calibration interaction block diagram provided in Embodiment 2 of the digital phased array transceiver calibration method based on a zero intermediate frequency architecture of the present application;

[0050] Figure 6 A dynamic transmission calibration interaction block diagram provided for Embodiment 2 of the digital phased array transceiver calibration method based on a zero intermediate frequency architecture of the present application;

[0051] Figure 7 A flowchart diagram of Embodiment 3 of the digital phased array transceiver calibration method based on a zero intermediate frequency architecture of the present application is provided;

[0052] Figure 8 This is a static receiving calibration interaction block diagram provided in Example 3 of the digital phased array transceiver calibration method based on the zero intermediate frequency architecture of the present application;

[0053] Fig. 9 This is a static transmission calibration interaction block diagram provided in Example 3 of the digital phased array transceiver calibration method based on the zero intermediate frequency architecture of the present application;

[0054] Fig.10 Schematic diagram of the device structure of the hardware operating environment involved in the digital phased array transceiver calibration method based on the zero intermediate frequency architecture in the embodiment of the present application.

[0055] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0056] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0057] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0058] The main solution of the embodiment of the present application is: the phased array controller obtains the static amplitude and phase compensation value of each transceiver channel in the digital phased array transceiver network relative to the calibration network; dynamically calibrates each of the transceiver channels based on a preset calibration network to obtain the dynamic amplitude and phase compensation value of each of the transceiver channels; superimposes the static amplitude and phase compensation value with the dynamic amplitude and phase compensation value to obtain the target amplitude and phase compensation value that the digital phased array needs to use in the transceiver network, and calibrates the digital phased array based on the target amplitude and phase compensation value.

[0059] In this embodiment, for the convenience of description, the following description is made with the phased array controller as the execution subject.

[0060] Since the existing technology requires array calibration to achieve amplitude and phase synchronization, the auxiliary antenna is used to send and receive correction signals to the channel to be calibrated, and the amplitude and phase difference of the data of each transceiver channel is calculated by the digital signal processor to obtain the amplitude and phase compensation value. However, during the calibration process, environmental factors will have a great impact on the calibration accuracy, resulting in low accuracy in the transceiver calibration of the digital phased array. At the same time, during the array calibration process, each transceiver channel is required to radiate signals to the outside, which poses a risk of information leakage and theft.

[0061] The present application provides a solution. Since in a digital phased array, there is a certain fixed phase difference and fixed amplitude difference between the transceiver channels in the calibration network and the transceiver network. Therefore, by statically calibrating each transceiver channel in the digital phased array, a fixed static amplitude-phase compensation value of each transceiver channel can be determined. When the digital phased array is powered on, each zero intermediate frequency chip has a certain power-on random phase difference and random amplitude difference. Therefore, it is necessary to dynamically calibrate all transceiver channels through a preset calibration network to obtain a dynamic amplitude-phase compensation value between the transceiver channels of each zero intermediate frequency chip. Then, by superimposing the static amplitude-phase compensation value of each transceiver channel with the dynamic amplitude-phase compensation value, a final target amplitude-phase compensation value is obtained. Calibration compensation is performed during the actual signal transmission and reception process. Since the calibration network is performed in an internal loop, the calibration error caused by external environmental factors is reduced, thereby improving the accuracy of the amplitude-phase consistency of the digital phased array based on the zero intermediate frequency architecture during transmission and reception.

[0062] Based on this, the embodiment of the present application provides a digital phased array transceiver calibration system based on a zero intermediate frequency architecture, referring to Figure 1 , Figure 1 This is the hardware interconnection block diagram of the digital phased array system for this application.

[0063] The data phased array system includes a radio frequency transceiver unit, a power division switch unit, a zero intermediate frequency transceiver chip, a signal processing unit, a clock network and a power network, and a phased array controller.

[0064] The RF transceiver unit consists of an RF switch, a low noise amplifier, and a digitally controlled attenuator;

[0065] The power division switch unit consists of a power divider, a radio frequency switch, and a transceiver;

[0066] The zero intermediate frequency transceiver chip may be AD9361. Each AD9361 can realize 2-way RF transmission and 2-way RF reception. It is used as a calibration chip and also as a channel chip, wherein each channel chip corresponds to 2-way transceiver channels.

[0067] The signal processing module consists of an FPGA (Field-Programmable Gate Array) and its external memory. FPGA is an integrated circuit that can be programmed on site.

[0068] The clock generation unit is composed of a constant temperature crystal oscillator, a phase-locked loop clock chip and a clock shunt chip; the clock generation unit is used to provide an accurate time reference for the digital phased array system and unify the time data for the entire digital phased array system; wherein the constant temperature crystal oscillator can be a crystal oscillator that uses a constant temperature tank to keep the temperature of the quartz crystal resonator in the crystal oscillator constant, and minimizes the change in the oscillator output frequency caused by the ambient temperature change; the phase-locked loop clock chip can be used to generate clock signals of various frequencies; the clock shunt chip can be used to distribute a single clock signal to multiple outputs, and provide a synchronous clock for all units and modules;

[0069] The power generation unit consists of a DCDC (DC-DC Converter) point-of-load power supply and an LDO (Low Dropout Voltage Regulator) low-noise linear regulator.

[0070] It should be noted that the zero-IF transceiver chip can support RF transceiver in the L / S / C bands, and further realize full digital domain multi-beam transceiver in the L / S / C bands through different configurations; among them, zero-IF transceiver means that the baseband zero-frequency signal can be directly up-converted into a RF signal, or the RF signal can be directly down-converted into a baseband zero-frequency signal.

[0071] The RF transceiver module can be used for transceiver switching of the zero intermediate frequency chip and interconnected with the power division switch unit.

[0072] The signal processing module can receive and generate calibration data, and is also used to determine the phase difference and amplitude difference of each channel, and calculate the superimposed static compensation value and dynamic compensation value, etc.

[0073] The power division switch unit can be used to realize the switching of the calibration network and the transceiver network in the digital phased array, as well as the mode switching of the receiving calibration and the transmitting calibration.

[0074] refer to Figure 2 The power division switch unit can switch the calibration network and the transceiver network in the digital phased array. The RF switch in the power division switch unit can realize the switching of the two networks. Among them, the calibration network has one end for the calibration input and output port (interconnected with the calibration AD9361 (chip)), and one end for the TX / RX (transmit / receive) port of the RF transceiver unit (interconnected with the transceiver AD9361); the transceiver network has one end for the TX / RX port of the RF transceiver unit (interconnected with the transceiver AD9361), and one end for the system's RF (RF) RF port (the system's transceiver channel).

[0075] It is understandable that this system is mainly composed of several unit modules, which can be freely combined into various channel arrays according to the reasonable scale of the phased array antenna, which can shorten the project development cycle, reduce project costs, reduce system design risks, and meet the needs of different projects. In addition, the transceiver based on the zero intermediate frequency architecture can save RF devices such as frequency converters, filters, and phase shifters. The full digital domain processing solves the problem of traditional miniaturization and flexibly realizes the transceiver of L / S / C bands.

[0076] It should be noted that the execution subject of this embodiment may be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device capable of realizing the above functions, a phased array controller, etc. The following takes the phased array controller as an example to illustrate this embodiment and the following embodiments.

[0077] Based on a digital phased array transceiver calibration system based on a zero intermediate frequency architecture, the present application embodiment provides a digital phased array transceiver calibration method based on a zero intermediate frequency architecture, referring to Figure 3 , Figure 3 This is a flowchart of a first embodiment of a digital phased array transceiver calibration method based on a zero intermediate frequency architecture of the present application.

[0078] In this embodiment, the digital phased array transceiver calibration method based on the zero intermediate frequency architecture includes steps S10 to S30:

[0079] Step S10, obtaining static amplitude and phase compensation values ​​of each transceiver channel in the digital phased array transceiver network relative to the calibration network;

[0080] It should be noted that static calibration can be to calibrate the fixed phase difference and fixed amplitude difference of each transceiver channel in the calibration network and the transceiver network in the digital phased array. The static amplitude-phase compensation value can be the fixed amplitude compensation value and the fixed phase compensation value after calibrating the fixed phase difference and fixed amplitude difference of each transceiver channel. Among them, the phase difference can be the degree of deviation between the phase of the signal during transmission and the phase of the original signal. The amplitude difference can be the degree of deviation between the measured value and the true value.

[0081] It should be noted that the static amplitude and phase compensation value includes a receiving static amplitude and phase compensation value and a transmitting static amplitude and phase compensation value.

[0082] Step S20, dynamically calibrating each of the transceiver channels based on a preset calibration network to obtain dynamic amplitude and phase compensation values ​​of each of the transceiver channels;

[0083] It should be noted that the dynamic calibration may be to calibrate the random phase difference and random amplitude difference between the zero intermediate frequency chips of each transceiver channel at power-on. The dynamic amplitude-phase compensation value may be the random phase compensation value and random amplitude compensation value after calibrating the random phase difference and random amplitude difference between the zero intermediate frequency chips of each transceiver channel at power-on.

[0084] It should be noted that the dynamic amplitude and phase compensation value includes the receiving dynamic amplitude and phase compensation value and the transmitting dynamic amplitude and phase compensation value. The calibration network is an internal network of the system, and the dynamic amplitude and phase compensation value obtained by it is not affected by external environmental factors, thereby improving the accuracy of the digital phased array transceiver calibration.

[0085] It is understandable that since there is a certain power-on random phase difference and random amplitude difference between the zero intermediate frequency chips of each transceiver channel, before the digital phased array is powered on and the transceiver network officially works, all transceiver channels in the digital phased array need to be dynamically calibrated through the calibration network, and the data is analyzed by the signal processing unit to obtain the dynamic amplitude and phase compensation values ​​between each transceiver channel, so as to calibrate the digital phased array for transceiver data through the dynamic amplitude and phase compensation values, that is, the dynamic amplitude and phase compensation values.

[0086] Step S30, superimposing the static amplitude-phase compensation value and the dynamic amplitude-phase compensation value to obtain a target amplitude-phase compensation value required to be used by the digital phased array in a transceiver network, and calibrating the digital phased array based on the target amplitude-phase compensation value.

[0087] In the specific implementation, the calibration network and the transceiver network are statically calibrated through instruments to obtain the static amplitude and phase compensation value of each transceiver channel; after the digital phased array is powered on, multiple AD9361s are dynamically calibrated through the calibration network to obtain the dynamic amplitude and phase compensation value of each transceiver channel; the static and dynamic amplitude and phase compensation values ​​are superimposed and calculated, and in the digital phased array transceiver network, this compensation value is added in the digital domain to realize the multi-channel synchronous transceiver of AD9361. There is no need to synchronize the amplitude and phase calibration through antenna radiation outside the system.

[0088] The present embodiment provides a digital phased array transceiver calibration method based on a zero intermediate frequency architecture. Since in a digital phased array, a transceiver channel has a certain fixed phase difference and a fixed amplitude difference in a calibration network and a transceiver network, a fixed static amplitude-phase compensation value of each transceiver channel can be determined by statically calibrating each transceiver channel in the digital phased array. When the digital phased array is powered on, each zero intermediate frequency chip has a certain power-on random phase difference and random amplitude difference. Therefore, it is necessary to dynamically calibrate all transceiver channels through a preset calibration network to obtain a dynamic amplitude-phase compensation value between transceiver channels of each zero intermediate frequency chip. Then, the static amplitude-phase compensation value of each transceiver channel is superimposed with the dynamic amplitude-phase compensation value to obtain a final target amplitude-phase compensation value. Calibration compensation is performed during actual signal transceiver processing. Since the calibration network is performed in an internal loop, the calibration error caused by external environmental factors is reduced, thereby improving the accuracy of amplitude-phase consistency during transceiver transmission of a digital phased array based on a zero intermediate frequency architecture.

[0089] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can refer to the above introduction, and will not be repeated later. Figure 4 , step S20 also includes steps S21 to S24:

[0090] Step S21, controlling the power division switch unit to switch to a preset calibration network;

[0091] Step S22, detecting a triggered calibration mode;

[0092] Step S23, if the triggered calibration mode is receiving calibration, controlling the zero intermediate frequency chip to send a calibration signal to the signal processing unit through each of the transceiver channels;

[0093] Step S24, obtaining the receiving dynamic amplitude and phase compensation value of each of the transceiver channels obtained after the signal processing unit processes the calibration signal.

[0094] It should be noted that the preset calibration network can be used to ensure the amplitude and phase consistency of the system during the transmission and reception process. The calibration mode includes receiving calibration and transmitting calibration. The receiving dynamic amplitude and phase compensation value can be the compensation value obtained after dynamic calibration of each transceiver channel during the receiving calibration process.

[0095] Specifically, step S23 may be that if the triggered calibration mode is receiving calibration, the calibration chip is controlled to send a calibration signal to the channel chip of each transceiver channel, and the calibration signal is collected and forwarded to the signal processing unit. Step S24 may be that after the signal processing unit processes the calibration signal, the receiving dynamic amplitude and phase compensation value of each transceiver channel is obtained.

[0096] It is understandable that if the triggered receiving calibration is determined, the power division switch unit is controlled to switch its configuration to a preset calibration network, which can ensure that the signal can be transmitted along a predetermined path during the calibration process, thereby ensuring the accuracy of the calibration.

[0097] It can be understood that by obtaining the receiving dynamic amplitude and phase compensation value of each transceiver channel, it can be ensured that each transceiver channel can accurately receive and process the signal, and because in a multi-channel system, the performance of each transceiver channel may vary due to hardware differences, temperature changes or other factors, by dynamically calibrating the receiving amplitude and phase, it can be ensured that all channels can achieve consistent performance standards.

[0098] Furthermore, step S23 further includes:

[0099] Controlling the calibration chip to send a calibration signal to the preset calibration network, so that the preset calibration network performs power division on the calibration signal to obtain an identical power division signal;

[0100] Control each of the channel chips to collect the power division signals through the corresponding transceiver channel, and forward each of the power division signals to the signal processing unit.

[0101] It should be noted that power division can be the distribution of signal energy among multiple transceiver channels. The power division signal can be a signal with a certain signal energy.

[0102] It can be understood that by controlling the calibration chip to send calibration signals, these calibration signals are sent to the preset calibration network, and the energy of the input signal is evenly distributed to multiple output ports through the preset calibration network to ensure that the power division signal obtained at each output port is as consistent as possible in amplitude and phase, so that the dynamic amplitude and phase compensation values ​​obtained for subsequent signal processing are within the controllable range within the channel chip.

[0103] In the specific implementation, refer to Figure 5The dynamic receiving calibration is as follows: the power division switch unit is switched to the calibration network through the RF switch, and the calibration AD9361 transmits the calibration signal to the calibration output port of the calibration network; the FPGA initiates the simultaneous sampling moment, 1#~8#AD9361 simultaneously samples the calibration signal output by RX1~RX16, and sends the sampling data to the FPGA; the FPGA analyzes the relevant data, obtains the dynamic amplitude difference and phase difference of RX2~RX16 based on RX1, converts it into the receiving dynamic compensation value and writes it into the external memory.

[0104] Furthermore, after step S20, the following steps are further included:

[0105] If the triggered calibration mode is transmission calibration, the sampling period of the calibration chip is retrieved;

[0106] Based on the sampling period, controlling the calibration chip to sequentially collect the calibration signal sent by the channel chip through the corresponding transceiver channel;

[0107] Controlling the calibration chip to collect the calibration signal and then forwarding the calibration signal to the signal processing unit;

[0108] The transmission dynamic amplitude and phase compensation value of each of the transceiver channels is obtained, wherein the transmission dynamic amplitude and phase compensation value is obtained by the signal processing unit performing dynamic amplitude difference and phase difference analysis on the calibration signal.

[0109] It should be noted that the sampling period may be a period for collecting calibration signals. The transmission dynamic amplitude and phase compensation value may be a compensation value obtained after dynamic calibration of each transceiver channel during the transmission calibration process.

[0110] It can be understood that when the need for emission calibration is detected, in order to perform emission calibration, the key parameters (sampling period) in the calibration process of the calibration chip are called up, the time interval for the calibration chip to collect signals is determined by the sampling period, and the accuracy of the calibration process is ensured by precisely controlling the sampling period.

[0111] Further, the step of controlling the calibration chip to sequentially collect the calibration signals sent by the channel chip through the corresponding transceiver channel based on the sampling period includes:

[0112] Based on the sampling period, determining a target transceiver channel that currently needs to be calibrated from the transceiver channels;

[0113] Controlling the channel chip corresponding to the target transceiver channel, and sending the calibration signal to the calibration chip through the power division switch unit;

[0114] The calibration chip is controlled to collect calibration signals sent by the remaining channel chips through the corresponding transceiver channels according to the sampling period until calibration signals sent through all the transceiver channels are collected.

[0115] In the specific implementation, refer to Figure 6 The power division switch unit is switched to the calibration network through the RF switch. The FPGA allows the 1#~8# chips (AD9361) AD9361 to output the calibration signals through TX1~TX16 according to the sampling period of the calibration AD9361. The calibration AD9361 samples the calibration signals output by TX1~TX16 according to the sampling period, and sends the 16 sampling data to the FPGA. The FPGA analyzes the relevant data to obtain the dynamic amplitude difference and phase difference of TX2~TX16 based on TX1, converts them into transmission dynamic compensation values ​​and writes them into the external memory.

[0116] Based on the first and second embodiments of the present application, in the third embodiment of the present application, the same or similar contents as those in the above embodiments can be referred to the above introduction, and will not be described in detail later. Figure 7 , step S10 includes steps S1 to S4:

[0117] Step S1, if it is determined that the triggered calibration mode is receiving calibration, then controlling the power division switch unit in the digital phased array to be a calibration network;

[0118] Step S2, obtaining a first receiving amplitude and phase detected by a preset vector network analyzer on each transceiver channel in a calibration network, wherein the first receiving amplitude and phase is measured by interconnecting an output end of the preset vector network analyzer with a receiving port of the calibration network and an input end of the preset vector network analyzer with a transceiver channel;

[0119] Step S3, controlling the power division switch unit to be a transceiver network, obtaining a second receiving amplitude phase obtained by detecting each transceiver channel in the transceiver network based on the preset vector network analyzer, wherein the second receiving amplitude phase is measured by interconnecting the output end of the preset vector network analyzer with the receiving port of the transceiver network and the input end of the preset vector network analyzer with the transceiver channel;

[0120] Step S4, performing a difference operation based on the first receiving amplitude phase and the second receiving amplitude phase of each of the transceiver channels to obtain a receiving static compensation value of each of the transceiver channels.

[0121] It should be noted that a vector network analyzer may be a radio frequency measuring instrument, which is mainly used to measure the performance parameters of high frequency devices and the amplitude and phase of radio frequency signals.

[0122] It can be understood that according to the first receiving amplitude phase and the second receiving amplitude phase data measured by the preset vector network analyzer, the difference between the first receiving amplitude phase and the second receiving amplitude phase is calculated, and the receiving static compensation value of each channel in the calibration network and the transceiver network is calculated based on these differences.

[0123] In the specific implementation, refer to Figure 8 , the power division switch unit is switched to the calibration network through the RF switch, the output port of the vector network analyzer is interconnected with the calibration input port, the input port of the vector network analyzer is interconnected with the RX1 interface, and the first receiving amplitude and phase of RX1 is obtained by test; the power division switch unit is switched to the transceiver network through the RF switch, the output port of the vector network analyzer is switched to be interconnected with RF1, and the second receiving amplitude and phase of RX1 is obtained by test, and the first receiving amplitude and phase are differentiated from the second receiving amplitude and phase to obtain the receiving static amplitude and phase compensation value of the transceiver channel RX1; similarly, the static amplitude difference and phase difference of RX2~RX16 are obtained by test; these amplitude differences and phase differences are converted to the receiving static compensation values ​​of all channels of RX1~RX16, and written into the memory plug-in of FPGA.

[0124] Optionally, step S10 further includes:

[0125] If it is determined that the triggered calibration mode is the transmission calibration, then controlling the output end of the preset vector network analyzer to be interconnected with the transceiver channel, and the input end of the preset vector network analyzer to be interconnected with the output port of the calibration network;

[0126] Acquire a first transmission amplitude and phase detected by the preset vector network analyzer on each of the transceiver channels in a calibration network;

[0127] Control the power division switch unit to be a transceiver network, and control the output end of the preset vector network analyzer to be interconnected with the transceiver channel, and the input end of the preset vector network analyzer to be interconnected with the output port of the transceiver network;

[0128] Acquire a second transmission amplitude and phase detected by the preset vector network analyzer on each of the transceiver channels in the transceiver network;

[0129] Based on the difference calculation between the first transmission amplitude and the second transmission amplitude of each of the transceiver channels, the transmission static compensation value of each of the transceiver channels is obtained.

[0130] In the specific implementation, refer to Fig. 9, the power division switch unit is switched to the calibration network through the RF switch, the output port of the vector network analyzer is interconnected with the TX1 interface, the input port of the vector network analyzer is interconnected with the calibration output port, and the first transmission amplitude and phase of TX1 is obtained by test; the power division switch unit is switched to the transceiver network through the RF switch, the input port of the vector network analyzer is switched to be interconnected with RF1, and the second transmission amplitude and phase of TX1 is obtained by test, and the first transmission amplitude and phase are differentiated from the second transmission amplitude and phase to obtain the transmission static amplitude and phase compensation value of the transceiver channel TX1; similarly, the static amplitude difference and phase difference of RX2~RX16 during transmission are obtained by test; these amplitude differences and phase differences are converted to the transmission static compensation values ​​of all channels of RX1~RX16, and written into the memory plug-in of FPGA.

[0131] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the digital phased array transceiver calibration method based on the zero intermediate frequency architecture of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

[0132] The present application provides a digital phased array transceiver calibration device based on a zero intermediate frequency architecture, and the digital phased array transceiver calibration device based on a zero intermediate frequency architecture includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor, so that the at least one processor can execute the digital phased array transceiver calibration method based on the zero intermediate frequency architecture in the above-mentioned embodiment 1.

[0133] Reference below Fig.10 , which shows a schematic diagram of the structure of a digital phased array transceiver calibration device based on a zero intermediate frequency architecture suitable for implementing the embodiment of the present application. The digital phased array transceiver calibration device based on a zero intermediate frequency architecture in the embodiment of the present application may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig.10 The digital phased array transceiver calibration device based on the zero intermediate frequency architecture shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0134] like Fig.10As shown, the digital phased array transceiver calibration device based on the zero intermediate frequency architecture may include a processing device 1001 (such as a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM: Read Only Memory) 1002 or the program loaded from the storage device 1003 to the random access memory (RAM: Random Access Memory) 1004. In RAM1004, various programs and data required for the operation of the digital phased array transceiver calibration device based on the zero intermediate frequency architecture are also stored. The processing device 1001, ROM1002 and RAM1004 are connected to each other through a bus 1005. The input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems may be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 may allow the digital phased array transceiver calibration device based on the zero intermediate frequency architecture to communicate wirelessly or wired with other devices to exchange data. Although the figure shows a digital phased array transceiver calibration device based on the zero intermediate frequency architecture with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems may be implemented or have instead.

[0135] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0136] The digital phased array transceiver calibration device based on zero intermediate frequency architecture provided by the present application adopts the digital phased array transceiver calibration method based on zero intermediate frequency architecture in the above-mentioned embodiment, which can solve the technical problem that the accuracy of transceiver calibration of the digital phased array is low due to the large influence of environmental factors on the calibration accuracy. Compared with the prior art, the beneficial effects of the digital phased array transceiver calibration device based on zero intermediate frequency architecture provided by the present application are the same as the beneficial effects of the digital phased array transceiver calibration method based on zero intermediate frequency architecture provided by the above-mentioned embodiment, and the other technical features of the digital phased array transceiver calibration device based on zero intermediate frequency architecture are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0137] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0138] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0139] The present application provides a computer-readable storage medium having computer-readable program instructions (i.e., computer programs) stored thereon, and the computer-readable program instructions are used to execute the digital phased array transceiver calibration method based on the zero intermediate frequency architecture in the above-mentioned embodiment.

[0140] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM: Random Access Memory), a read-only memory (ROM: Read Only Memory), an erasable programmable read-only memory (EPROM: Erasable Programmable Read Only Memory or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM: CD-Read Only Memory), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency: Radio Frequency), etc., or any suitable combination of the above.

[0141] The computer-readable storage medium may be included in the digital phased array transceiver calibration device based on the zero intermediate frequency architecture; or may exist independently without being assembled into the digital phased array transceiver calibration device based on the zero intermediate frequency architecture.

[0142] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by a digital phased array transceiver calibration device based on a zero intermediate frequency architecture, the digital phased array transceiver calibration device based on a zero intermediate frequency architecture: obtains static amplitude and phase compensation values ​​after static calibration of each transceiver channel in the digital phased array; dynamically calibrates each of the transceiver channels based on a preset calibration network to obtain dynamic amplitude and phase compensation values ​​of each of the transceiver channels; superimposes the static amplitude and phase compensation values ​​with the dynamic amplitude and phase compensation values ​​to obtain target amplitude and phase compensation values ​​that the digital phased array needs to use in the transceiver network, and calibrates the digital phased array based on the target amplitude and phase compensation values.

[0143] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0144] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0145] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0146] The readable storage medium provided by the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned digital phased array transceiver calibration method based on zero intermediate frequency architecture, and can solve the technical problem that the accuracy of transceiver calibration of the digital phased array is low due to the large influence of environmental factors on the calibration accuracy. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by the present application are the same as the beneficial effects of the digital phased array transceiver calibration method based on zero intermediate frequency architecture provided by the above-mentioned embodiment, and will not be repeated here.

[0147] The present application also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the above-mentioned digital phased array transceiver calibration method based on zero intermediate frequency architecture.

[0148] The computer program product provided by the present application can solve the technical problem that the accuracy of transceiver calibration of a digital phased array is low due to the large impact of environmental factors on the calibration accuracy. Compared with the prior art, the beneficial effects of the computer program product provided by the present application are the same as the beneficial effects of the digital phased array transceiver calibration method based on the zero intermediate frequency architecture provided by the above embodiment, and will not be elaborated here.

[0149] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A digital phased array transceiver calibration method based on a zero intermediate frequency architecture, characterized in that: The method includes: Obtaining static amplitude and phase compensation values ​​for each transceiver channel in a digital phased array transceiver network relative to a calibration network, wherein the digital phased array includes a power division switch unit, a signal processing unit, and a zero intermediate frequency chip, wherein the zero intermediate frequency chip includes a calibration chip and a channel chip, and the static amplitude and phase compensation values ​​include receiving static compensation values; Dynamically calibrating each of the transceiver channels based on a preset calibration network to obtain a dynamic amplitude and phase compensation value of each of the transceiver channels, wherein the dynamic amplitude and phase compensation value includes a receiving dynamic amplitude and phase compensation value and a transmitting dynamic amplitude and phase compensation value; The static amplitude-phase compensation value and the dynamic amplitude-phase compensation value are superimposed to obtain a target amplitude-phase compensation value required to be used by the digital phased array in a transceiver network, and the digital phased array is calibrated based on the target amplitude-phase compensation value; The step of dynamically calibrating each of the transceiver channels based on a preset calibration network to obtain a dynamic amplitude and phase compensation value of each of the transceiver channels comprises: Controlling the power division switch unit to switch to a preset calibration network; Detecting a calibration mode being triggered; If the triggered calibration mode is receiving calibration, the calibration chip is controlled to send a calibration signal to the preset calibration network, so that the preset calibration network performs power division on the calibration signal to obtain the same power division signal; Control each of the channel chips to collect the power division signal through the corresponding transceiver channel, and forward each of the power division signals to the signal processing unit; Acquire the receiving dynamic amplitude and phase compensation value of each of the transceiver channels obtained after the signal processing unit processes the calibration signal; If the triggered calibration mode is transmission calibration, the sampling period of the calibration chip is retrieved; Based on the sampling period, controlling the calibration chip to sequentially collect the calibration signal sent by the channel chip through the corresponding transceiver channel; Controlling the calibration chip to forward the calibration signal to the signal processing unit; Acquire a transmission dynamic amplitude and phase compensation value of each of the transceiver channels, wherein the transmission dynamic amplitude and phase compensation value is obtained by the signal processing unit performing dynamic amplitude difference and phase difference analysis on the calibration signal; The step of obtaining a static amplitude and phase compensation value of each transceiver channel in the digital phased array transceiver network relative to the calibration network comprises: If it is determined that the triggered calibration mode is receiving calibration, then controlling the power division switch unit in the digital phased array to be a calibration network; Acquire a first receiving amplitude and phase detected by a preset vector network analyzer on each transceiver channel in a calibration network, wherein the first receiving amplitude and phase is measured by interconnecting an output end of the preset vector network analyzer with a receiving port of the calibration network and an input end of the preset vector network analyzer with a transceiver channel; Control the power division switch unit to be a transceiver network, and obtain a second receiving amplitude phase obtained by detecting each transceiver channel in the transceiver network based on the preset vector network analyzer, wherein the second receiving amplitude phase is measured by interconnecting the output end of the preset vector network analyzer with the receiving port of the transceiver network and the input end of the preset vector network analyzer with the transceiver channel; Based on the difference operation of the first receiving amplitude phase and the second receiving amplitude phase of each of the transceiver channels, the receiving static compensation value of each of the transceiver channels is obtained.

2. The method according to claim 1, characterized in that The power division switch unit includes a power divider, and the step of controlling the calibration chip to sequentially collect the calibration signal sent by the channel chip through the corresponding transceiver channel based on the sampling period includes: Based on the sampling period, determining a target transceiver channel that currently needs to be calibrated from the transceiver channels; Controlling the channel chip corresponding to the target transceiver channel, and sending the calibration signal to the calibration chip through the power division switch unit; The calibration chip is controlled to collect calibration signals sent by the remaining channel chips through the corresponding transceiver channels according to the sampling period until calibration signals sent through all the transceiver channels are collected.

3. The method according to claim 1, characterized in that The static amplitude and phase compensation value includes a transmission static compensation value, and the step of obtaining the static amplitude and phase compensation value of each transceiver channel in the digital phased array transceiver network relative to the calibration network also includes: If it is determined that the triggered calibration mode is the transmission calibration, then controlling the output end of the preset vector network analyzer to be interconnected with the transceiver channel, and the input end of the preset vector network analyzer to be interconnected with the output port of the calibration network; Acquire a first transmission amplitude and phase detected by the preset vector network analyzer on each of the transceiver channels in a calibration network; Control the power division switch unit to be a transceiver network, and control the output end of the preset vector network analyzer to be interconnected with the transceiver channel, and the input end of the preset vector network analyzer to be interconnected with the output port of the transceiver network; Acquire a second transmission amplitude and phase detected by the preset vector network analyzer on each of the transceiver channels in the transceiver network; Based on the difference calculation between the first transmission amplitude and the second transmission amplitude of each of the transceiver channels, the transmission static compensation value of each of the transceiver channels is obtained.

4. A digital phased array transceiver calibration device based on a zero intermediate frequency architecture, characterized in that: The device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the digital phased array transceiver calibration method based on zero intermediate frequency architecture as described in any one of claims 1 to 3.

5. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by the processor, the steps of the digital phased array transceiver calibration method based on zero intermediate frequency architecture are implemented as described in any one of claims 1 to 3.

6. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the digital phased array transceiver calibration method based on a zero intermediate frequency architecture are implemented as claimed in any one of claims 1 to 3.

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