LDO circuit and power supply integrated circuit

Abstract

The present invention provides an LDO circuit and a power supply integrated circuit, wherein the LDO circuit includes a power tube, an error amplifier circuit, a first voltage switching circuit, a second voltage switching circuit and a third voltage switching circuit. When the first voltage is greater than the second voltage, the first voltage switching circuit receives the second potential and turns on, and transmits the high-potential input voltage to the substrate of the power tube. At the same time, the error amplifier circuit outputs the second potential, the power tube turns on, and the driving operation of the power tube is realized. When the first voltage is less than the second voltage, the second voltage switching circuit and the third voltage switching circuit receive the fourth potential and turn on in a controlled manner, and output the high-potential output voltage to the substrate and gate of the power tube. The PN junction of the power tube is reverse biased, and no reverse current is generated, thereby improving the working safety of the LDO circuit and the integrated circuit and reducing the circuit energy consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to an LDO circuit and a power supply integrated circuit. Background Art

[0002] With the development of the integrated circuit industry, the functions of electronic products are changing with each passing day, which has put forward more requirements on their power supply, such as high performance and low cost. Among them, power tubes are widely used in power management circuits, such as linear step-down converters (Low Dropout Regulator, LDO), DC-DC switching converters, lithium battery chargers, etc.

[0003] In certain cases, the input of the LDO circuit is connected to a discharged battery, such as Figure 1 As shown, the voltage at the output end of the LDO circuit is maintained by a large capacitor. When the input voltage is lower than the output voltage, the capacitor at the output end is discharged through the parasitic diode of the power tube during discharge, and a reverse voltage (Reverse-Voltage) appears on the power tube, causing the system to consume too much current and generate heat. Summary of the invention

[0004] The present invention aims to provide an LDO circuit, aiming to solve the problem of reverse current in traditional LDO circuits.

[0005] A first aspect of an embodiment of the present invention provides an LDO circuit, including:

[0006] A power tube, wherein a source of the power tube is used to input a first voltage, and a drain of the power tube is used to output a second voltage;

[0007] An error amplifier circuit, wherein a reference end of the error amplifier circuit is used to input a reference voltage, a feedback end of the error amplifier circuit is connected to an output end of the power tube, and an output end of the error amplifier circuit is connected to a gate of the power tube;

[0008] a first voltage switching circuit, wherein a first end of the first voltage switching circuit is connected to a source of the power tube, a second end of the first voltage switching circuit is connected to a substrate of the power tube, a control end of the first voltage switching circuit is connected to an output end of the error amplifier circuit, the first voltage switching circuit is turned off based on a first potential trigger of its own control end and is turned on based on a second potential trigger of its own control end, and a voltage of the first potential is greater than a voltage of the second potential;

[0009] a second voltage switching circuit, wherein a first end of the second voltage switching circuit is connected to the substrate of the power tube, a second end of the second voltage switching circuit is connected to the output end of the power tube, a control end of the second voltage switching circuit is connected to the source of the power tube, the second voltage switching circuit is turned off based on a third potential of its control end and turned on based on a fourth potential of its control end, and a voltage of the third potential is greater than a voltage of the fourth potential;

[0010] A third voltage switching circuit, wherein the first end of the third voltage switching circuit is respectively connected to the output end of the error amplifier circuit and the control end of the first voltage switching circuit, the second end of the third voltage switching circuit is connected to the output end of the power tube, the control end of the third voltage switching circuit is connected to the source of the power tube, and the third voltage switching circuit is turned off based on the third potential trigger of its own control end and turned on based on the fourth potential trigger of its own control end.

[0011] Optionally, the power tube is a first PMOS tube.

[0012] Optionally, the first voltage switching circuit includes a second PMOS tube, the drain of the second PMOS tube constitutes the first end of the first voltage switching circuit, the source of the second PMOS tube and the substrate of the second PMOS tube are connected to constitute the second end of the first voltage switching circuit, and the gate of the second PMOS tube constitutes the control end of the first voltage switching circuit.

[0013] Optionally, the second voltage switching circuit includes a third PMOS tube, the drain of the third PMOS tube constitutes the second end of the second voltage switching circuit, the source of the third PMOS tube and the substrate of the third PMOS tube are connected to constitute the first end of the second voltage switching circuit, and the gate of the third PMOS tube constitutes the control end of the second voltage switching circuit.

[0014] Optionally, the third voltage switching circuit includes a fourth PMOS tube, the drain of the fourth PMOS tube constitutes the second end of the third voltage switching circuit, the source of the fourth PMOS tube constitutes the first end of the third voltage switching circuit, the gate of the fourth PMOS tube constitutes the control end of the third voltage switching circuit, and the substrate of the fourth PMOS tube is connected to the substrate of the power tube.

[0015] Optionally, the first voltage switching circuit includes a first NMOS tube and a first inverter, the drain of the first NMOS tube constitutes the first end of the first voltage switching circuit, the source of the first NMOS tube and the substrate of the first NMOS tube are connected to constitute the second end of the first voltage switching circuit, the gate of the first NMOS tube is connected to the output end of the first inverter, and the input end of the first inverter constitutes the control end of the first voltage switching circuit.

[0016] Optionally, the second voltage switching circuit includes a second NMOS tube and a second inverter, the drain of the second NMOS tube constitutes the second end of the second voltage switching circuit, the source of the second NMOS tube and the substrate of the second NMOS tube are connected to constitute the first end of the second voltage switching circuit, the gate of the second NMOS tube is connected to the output end of the second inverter, and the input end of the second inverter constitutes the control end of the second voltage switching circuit.

[0017] Optionally, the third voltage switching circuit includes a third NMOS tube and a third inverter, the drain of the third NMOS tube constitutes the second end of the second voltage switching circuit, the source of the third NMOS tube constitutes the first end of the third voltage switching circuit, the gate of the third NMOS tube is connected to the output end of the third inverter, the input end of the third inverter constitutes the control end of the third voltage switching circuit, and the substrate of the third NMOS tube is connected to the substrate of the power tube.

[0018] Optionally, the error amplifier circuit includes an error amplifier, a non-phase input terminal of the error amplifier constitutes a feedback terminal of the error amplifier circuit, an inverting input terminal of the error amplifier constitutes a reference terminal of the error amplifier circuit, and an output terminal of the error amplifier constitutes an output terminal of the error amplifier circuit.

[0019] A second aspect of an embodiment of the present invention provides a power integrated circuit, comprising the LDO circuit as described above.

[0020] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned LDO circuit includes a power tube, an error amplifier circuit, a first voltage switching circuit, a second voltage switching circuit and a third voltage switching circuit; when the first voltage is greater than the second voltage, the first voltage switching circuit receives the second potential and turns on, and transmits the high-potential input voltage to the substrate of the power tube; at the same time, the error amplifier circuit outputs the second potential, the power tube turns on, and the driving operation of the power tube is realized; when the first voltage is less than the second voltage, the second voltage switching circuit and the third voltage switching circuit receive the fourth potential and turn on in a controlled manner, and output the high-potential output voltage to the substrate and gate of the power tube; the PN junction of the power tube is reverse biased, and no reverse current is generated, thereby improving the working safety of the LDO circuit and the integrated circuit, and reducing the circuit energy consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0022] Figure 1 is a circuit diagram of a traditional LDO circuit;

[0023] Figure 2 A schematic diagram of the structure of an LDO circuit provided by an embodiment of the present invention;

[0024] Figure 3 A first schematic diagram of an LDO circuit provided by an embodiment of the present invention;

[0025] Figure 4 A second schematic diagram of an LDO circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0027] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0028] A first aspect of an embodiment of the present invention provides an LDO circuit for stabilizing and outputting a second voltage Vout.

[0029] like Figure 2 As shown, in this embodiment, the LDO circuit includes:

[0030] A power tube M1, wherein a source of the power tube M1 is used to input a first voltage Vin, and a drain of the power tube M1 is used to output a second voltage Vout;

[0031] The error amplifier circuit 10, the reference end of the error amplifier circuit 10 is used to input the reference voltage Vref, the feedback end of the error amplifier circuit 10 is connected to the output end of the power tube M1, and the output end of the error amplifier circuit 10 is connected to the gate of the power tube M1;

[0032] A first voltage switching circuit 20, wherein a first end of the first voltage switching circuit 20 is connected to the source of the power tube M1, a second end of the first voltage switching circuit 20 is connected to the substrate of the power tube M1, a control end of the first voltage switching circuit 20 is connected to the output end of the error amplifier circuit 10, the first voltage switching circuit 20 is turned off based on a first potential trigger of its own control end and is turned on based on a second potential trigger of its own control end, and the voltage of the first potential is greater than the voltage of the second potential;

[0033] A second voltage switching circuit 30, wherein a first end of the second voltage switching circuit 30 is connected to the substrate of the power tube M1, a second end of the second voltage switching circuit 30 is connected to the output end of the power tube M1, a control end of the second voltage switching circuit 30 is connected to the source of the power tube M1, the second voltage switching circuit 30 is turned off based on a third potential of its own control end and is turned on based on a fourth potential of its own control end, and the voltage of the third potential is greater than the voltage of the fourth potential;

[0034] The third voltage switching circuit 40, the first end of the third voltage switching circuit 40 is respectively connected to the output end of the error amplifier circuit 10 and the control end of the first voltage switching circuit 20, the second end of the third voltage switching circuit 40 is connected to the output end of the power tube M1, the control end of the third voltage switching circuit 40 is connected to the source of the power tube M1, the third voltage switching circuit 40 is turned off based on the third potential of its own control end and is turned on based on the fourth potential of its own control end.

[0035] In this embodiment, the first voltage Vin is the input voltage of the LDO circuit, the second voltage Vout is the output voltage of the LDO circuit, the power tube M1 and the error amplifier circuit 10 constitute the output stage of the LDO circuit, the error amplifier circuit 10 compares the second voltage Vout with the reference voltage Vref, and outputs a comparison signal Vea, thereby feedback-adjusting the current and output voltage of the power tube M1 so that its output voltage is stabilized at the reference voltage Vref.

[0036] When a high-potential first voltage Vin is input to the input end of the LDO circuit, that is, when the first voltage Vin is greater than the second voltage Vout of the output voltage, the comparison signal Vea is the second potential, and the comparison signal Vea is output to the first voltage switching circuit 20. The first voltage switching circuit 20 is turned on and transmits the first voltage Vin to the substrate of the power tube M1. The gate of the power tube M1 is at the second potential. The first voltage Vin is greater than the voltage of the second potential. A voltage difference is formed between the gate and the substrate of the power tube M1, and a current path is formed between the source and the gate of the power tube M1. The first voltage Vin is converted by the power tube M1 and output as the second voltage Vout to the rear-end load, and the power tube M1 outputs a current of corresponding magnitude to the rear-end load.

[0037] At the same time, the control ends of the second voltage switching circuit 30 and the third voltage switching circuit 40 receive a third potential, the voltage of the third potential is the current first voltage Vin, the second voltage switching circuit 30 and the third voltage switching circuit 40 are turned off, and there is no DC conductive branch except the power tube M1, so there is no static current consumption.

[0038] The reverse current of the LDO circuit includes the leakage current generated when the PN junction parasitic diode of the power tube M1 is reversely conducted, and the reverse current of the path from the output end to the input end of the LDO circuit when the first voltage Vin is less than the second voltage Vout and voltage reversal occurs and the first voltage switching circuit 20 and the third voltage switching circuit 40 are turned on.

[0039] When the first voltage Vin of the LDO circuit is less than the second voltage Vout, that is, the input voltage is less than the output voltage, the second voltage switching circuit 30 and the third voltage switching circuit 40 receive a fourth potential, which is the first voltage Vin at the current low potential. The second voltage switching circuit 30 and the third voltage switching circuit 40 are turned on, and the second voltage switching circuit 30 transmits the high potential second voltage Vout to the substrate of the power tube M1. At the same time, the third voltage switching circuit 40 transmits the high potential second voltage Vout to the gate of the power tube M1 and the control end of the first voltage switching circuit 20. The first voltage switching circuit 20 receives the first potential, which is the high potential of the second voltage Vout. The first voltage switching circuit 20 is turned off, that is, there is no reverse current in the path formed from the output end of the LDO circuit, the third voltage switching circuit 40, the second voltage switching circuit 30 to the input end.

[0040] At the same time, the gate and substrate of the power tube M1 both receive the high-potential second voltage Vout, the PN junction of the power tube M1 is reverse biased, the parasitic diode is turned off, no leakage current is generated in the power tube M1, and the LDO circuit as a whole has no reverse current, thereby improving the working safety of the LDO circuit and the integrated circuit and reducing the circuit energy consumption.

[0041] The power tube M1 can be an NMOS tube or a PMOS tube. The error amplifier circuit 10 can select the corresponding error amplifier U1 and the connection method based on the type of the power tube M1. In an optional embodiment, Figure 3 As shown, the power tube M1 is a first PMOS tube, which is triggered to turn on when receiving a low level output by the error amplifier circuit 10, and is triggered to turn off when receiving a high level output by the error amplifier circuit 10. Correspondingly, Figure 3 As shown, in an optional embodiment, the error amplifier circuit 10 includes an error amplifier U1, the non-phase input terminal of the error amplifier U1 constitutes the feedback terminal of the error amplifier circuit 10, the inverting input terminal of the error amplifier U1 constitutes the reference terminal of the error amplifier circuit 10, and the output terminal of the error amplifier U1 constitutes the output terminal of the error amplifier circuit 10.

[0042] When it is detected that the second voltage Vout is greater than the reference voltage Vref, the comparison signal Vea increases, the output current of the first PMOS tube increases, and the output second voltage Vout decreases. Correspondingly, when it is detected that the second voltage Vout is less than the reference voltage Vref, the comparison signal Vea decreases, the current of the first PMOS tube decreases, and the output second voltage Vout increases. Finally, through the feedback adjustment of the error amplifier U1, the second voltage Vout is stabilized at the reference voltage Vref.

[0043] The first voltage switching circuit 20, the second voltage switching circuit 30 and the third voltage switching circuit 40 can use corresponding switch tubes, comparison circuits, etc. In an optional embodiment, as shown in FIG. Figure 3 As shown, the first voltage switching circuit 20 includes a second PMOS tube M2, the drain of the second PMOS tube M2 constitutes the first end of the first voltage switching circuit 20, the source of the second PMOS tube M2 and the substrate of the second PMOS tube M2 are connected to constitute the second end of the first voltage switching circuit 20, and the gate of the second PMOS tube M2 constitutes the control end of the first voltage switching circuit 20.

[0044] The second voltage switching circuit 30 includes a third PMOS tube M3, the drain of the third PMOS tube M3 constitutes the second end of the second voltage switching circuit 30, the source of the third PMOS tube M3 and the substrate of the third PMOS tube M3 are connected to constitute the first end of the second voltage switching circuit 30, and the gate of the third PMOS tube M3 constitutes the control end of the second voltage switching circuit 30.

[0045] The third voltage switching circuit 40 includes a fourth PMOS tube M4, a drain of the fourth PMOS tube M4 constitutes a second end of the third voltage switching circuit 40, a source of the fourth PMOS tube M4 constitutes a first end of the third voltage switching circuit 40, a gate of the fourth PMOS tube M4 constitutes a control end of the third voltage switching circuit 40, and a substrate of the fourth PMOS tube M4 is connected to a substrate of the power tube M1.

[0046] In this embodiment, when the LDO circuit normally inputs a high-potential first voltage Vin and outputs a low-potential second voltage Vout, that is, when the first voltage Vin is greater than the output voltage second voltage Vout, and the voltage difference is greater than the threshold voltage of the power tube M1, the comparison signal Vea is the second potential, the comparison signal Vea is output to the second PMOS tube M2, the second PMOS tube M2 is turned on, and the first voltage Vin is transmitted to the substrate of the power tube M1, the gate of the power tube M1 is the second potential, the first voltage Vin is greater than the voltage of the second potential, a voltage difference is formed between the gate of the power tube M1 and the substrate, a current path is formed between the source and the gate of the power tube M1, the first voltage Vin is converted by the power tube M1 and output to the second voltage Vout to the back-end load, and the power tube M1 outputs a current of corresponding magnitude to the back-end load.

[0047] At the same time, the control ends of the third PMOS tube M3 and the fourth PMOS tube M4 receive a third potential, the voltage of the third potential is the current first voltage Vin, the third PMOS tube M3 and the fourth PMOS tube M4 are turned off, and there is no DC conductive branch except the power tube M1, so there is no static current consumption.

[0048] The reverse current of the LDO circuit includes the leakage current generated when the PN junction parasitic diode of the power tube M1 is reversely conducted, and the reverse current of the path from the output end to the input end of the LDO circuit when the second PMOS tube M2 and the fourth PMOS tube M4 are turned on when the first voltage Vin is less than the second voltage Vout and voltage reverse occurs.

[0049] When the first voltage Vin of the LDO circuit is less than the second voltage Vout, that is, the input voltage is less than the output voltage, and the difference between the second voltage Vout and the first voltage Vin is greater than the threshold voltages of the third PMOS tube M3 and the fourth PMOS tube M4, the third PMOS tube M3 and the fourth PMOS tube M4 receive a fourth potential, which is the first voltage Vin of the current low potential, and the third PMOS tube M3 and the fourth PMOS tube M4 are turned on, and the third PMOS tube M3 transmits the second voltage Vout of high potential to the substrate of the power tube M1. At the same time, the fourth PMOS tube M4 transmits the second voltage Vout of high potential to the gate of the power tube M1 and the control end of the second PMOS tube M2, and the control end of the second PMOS tube M2 receives the first potential, which is the high potential of the second voltage Vout, and the second PMOS tube M2 is turned off, that is, there is no reverse current in the path formed from the output end of the LDO circuit, the fourth PMOS tube M4, the third PMOS tube M3 to the input end.

[0050] At the same time, the gate and substrate of the power tube M1 both receive the high-potential second voltage Vout, the PN junction of the power tube M1 is reverse biased, the parasitic diode is turned off, no leakage current is generated in the power tube M1, and the LDO circuit as a whole has no reverse current, thereby improving the working safety of the LDO circuit and the integrated circuit and reducing the circuit energy consumption.

[0051] At the same time, by using four PMOS tubes to form the conversion unit between the input and output of the LDO circuit, the conversion unit area is small, the chip cost of the integrated circuit is reduced, and there is no need to set up Figure 1 The additional impedance connected in series with the power tube M1 reduces the voltage difference effect caused by the impedance.

[0052] The switch tubes of the first voltage switching circuit 20, the second voltage switching circuit 30 and the third voltage switching circuit 40 may also be NMOS tubes of opposite types. In an optional embodiment, as shown in FIG. Figure 4 As shown, the first voltage switching circuit 20 includes a first NMOS tube M5 and a first inverter INV1, the drain of the first NMOS tube M5 constitutes a first end of the first voltage switching circuit 20, the source of the first NMOS tube M5 and the substrate of the first NMOS tube M5 are connected to constitute a second end of the first voltage switching circuit 20, the gate of the first NMOS tube M5 is connected to the output end of the first inverter INV1, and the input end of the first inverter INV1 constitutes a control end of the first voltage switching circuit 20.

[0053] The second voltage switching circuit 30 includes a second NMOS tube M6 and a second inverter INV2. The drain of the second NMOS tube M6 constitutes the second end of the second voltage switching circuit 30. The source of the second NMOS tube M6 and the substrate of the second NMOS tube M6 are connected to constitute the first end of the second voltage switching circuit 30. The gate of the second NMOS tube M6 is connected to the output end of the second inverter INV2. The input end of the second inverter INV2 constitutes the control end of the second voltage switching circuit 30.

[0054] The third voltage switching circuit 40 includes a third NMOS tube M7 and a third inverter INV3. The drain of the third NMOS tube M7 constitutes the second end of the second voltage switching circuit 30, the source of the third NMOS tube M7 constitutes the first end of the third voltage switching circuit 40, the gate of the third NMOS tube M7 is connected to the output end of the third inverter INV3, the input end of the third inverter INV3 constitutes the control end of the third voltage switching circuit 40, and the substrate of the third NMOS tube M7 is connected to the substrate of the power tube M1.

[0055] In this embodiment, when the LDO circuit normally inputs the first voltage Vin of the high potential and outputs the second voltage Vout of the low potential, that is, when the first voltage Vin is greater than the output voltage second voltage Vout, and the voltage difference is greater than the threshold voltage of the power tube M1, the comparison signal Vea is the second potential, the second potential is the low potential, the first inverter INV1 reversely outputs the high potential to the first NMOS tube M5, the first NMOS tube M5 is turned on, and transmits the first voltage Vin to the substrate of the power tube M1, the gate of the power tube M1 is the second potential, the first voltage Vin is greater than the voltage of the second potential, a voltage difference is formed between the gate of the power tube M1 and the substrate, a current path is formed between the source and the gate of the power tube M1, the first voltage Vin is converted by the power tube M1 and outputted as the second voltage Vout to the rear-end load, and the power tube M1 outputs a current of corresponding magnitude to the rear-end load.

[0056] At the same time, the second inverter INV2 and the third inverter INV3 receive the third potential of high potential, and output low potential to the control ends of the second NMOS tube M6 and the third NMOS tube M7 respectively. The voltage of the third potential is the current first voltage Vin, the second NMOS tube M6 and the third NMOS tube M7 are turned off, and there is no DC conductive branch except the power tube M1, so there is no static current consumption.

[0057] The reverse current of the LDO circuit includes the leakage current generated when the PN junction parasitic diode of the power tube M1 is reversely conducted, and the reverse current of the path from the output end to the input end of the LDO circuit when the first NMOS tube M5 and the third NMOS tube M7 are turned on when the first voltage Vin is less than the second voltage Vout and voltage reverse occurs.

[0058] When the first voltage Vin of the LDO circuit is less than the second voltage Vout, that is, the input voltage is less than the output voltage, the second inverter INV2 and the third inverter INV3 receive the fourth potential of the low potential, and convert and output the high potential to the second NMOS tube M6 and the third NMOS tube M7, the fourth potential is the first voltage Vin of the current low potential, the second NMOS tube M6 and the third NMOS tube M7 are turned on, the second NMOS tube M6 transmits the high potential second voltage Vout to the substrate of the power tube M1, and at the same time, the third NMOS tube M7 transmits the high potential second voltage Vout to the gate of the power tube M1 and the control end of the first NMOS tube M5, the first inverter INV1 receives the first potential, the first potential is the high potential of the second voltage Vout, the first inverter INV1 reversely outputs a low potential, and the first NMOS tube M5 is turned off, that is, there is no reverse current in the path formed from the output end of the LDO circuit, the third NMOS tube M7, the second NMOS tube M6 to the input end.

[0059] At the same time, the gate and substrate of the power tube M1 both receive the high-potential second voltage Vout, the PN junction of the power tube M1 is reverse biased, the parasitic diode is turned off, no leakage current is generated in the power tube M1, and the LDO circuit as a whole has no reverse current, thereby improving the working safety of the LDO circuit and the integrated circuit and reducing the circuit energy consumption.

[0060] At the same time, by using four NMOS tubes and three inverters to form the conversion unit between the input and output of the LDO circuit, the conversion unit area is small, which reduces the chip cost of the integrated circuit and does not need to be set up. Figure 1 The additional impedance connected in series with the power tube M1 reduces the voltage difference effect caused by the impedance.

[0061] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned LDO circuit includes a power tube M1, an error amplifier circuit 10, a first voltage switching circuit 20, a second voltage switching circuit 30 and a third voltage switching circuit 40; when the first voltage Vin is greater than the second voltage Vout, the first voltage switching circuit 20 receives the second potential and turns on, and transmits the high-potential input voltage to the substrate of the power tube M1; at the same time, the error amplifier circuit 10 outputs the second potential, the power tube M1 turns on, and the driving operation of the power tube M1 is realized; when the first voltage Vin is less than the second voltage Vout, the second voltage switching circuit 30 and the third voltage switching circuit 40 receive the fourth potential and are controlled to turn on, and output the high-potential output voltage to the substrate and gate of the power tube M1; the PN junction of the power tube M1 is reverse biased, and no reverse current is generated, thereby improving the working safety of the LDO circuit and the integrated circuit, and reducing the circuit energy consumption.

[0062] The present invention also proposes a power supply integrated circuit, which includes an LDO circuit. The specific structure of the LDO circuit refers to the above embodiment. Since the power supply integrated circuit adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0063] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. An LDO circuit, characterized in that: include: a power tube, wherein a source of the power tube is used to input a first voltage, and a drain of the power tube is used to output a second voltage; an error amplifier circuit, wherein a reference terminal of the error amplifier circuit is used to input a reference voltage, a feedback terminal of the error amplifier circuit is connected to the output terminal of the power tube, and the output terminal of the error amplifier circuit is connected to the gate of the power tube; a first voltage switching circuit, wherein a first end of the first voltage switching circuit is connected to the source of the power transistor, a second end of the first voltage switching circuit is connected to the substrate of the power transistor, a control end of the first voltage switching circuit is connected to the output end of the error amplifier circuit, the first voltage switching circuit is triggered to be turned off based on a first potential at its control end and is triggered to be turned on based on a second potential at its control end, and a voltage of the first potential is greater than a voltage of the second potential; a second voltage switching circuit, wherein a first end of the second voltage switching circuit is connected to the substrate of the power transistor, a second end of the second voltage switching circuit is connected to the output end of the power transistor, a control end of the second voltage switching circuit is connected to the source of the power transistor, the second voltage switching circuit is triggered to be turned off based on a third potential at its control end and to be turned on based on a fourth potential at its control end, and the voltage of the third potential is greater than the voltage of the fourth potential; A third voltage switching circuit, wherein the first end of the third voltage switching circuit is respectively connected to the output end of the error amplifier circuit and the control end of the first voltage switching circuit, the second end of the third voltage switching circuit is connected to the output end of the power tube, the control end of the third voltage switching circuit is connected to the source of the power tube, and the third voltage switching circuit is triggered to shut down based on the third potential of its own control end and to turn on based on the fourth potential of its own control end.

2. The LDO circuit according to claim 1, wherein: The power tube is a first PMOS tube.

3. The LDO circuit according to claim 1, wherein: The first voltage switching circuit includes a second PMOS transistor, the drain of the second PMOS transistor constitutes the first end of the first voltage switching circuit, the source of the second PMOS transistor and the substrate of the second PMOS transistor are connected to constitute the second end of the first voltage switching circuit, and the gate of the second PMOS transistor constitutes the control end of the first voltage switching circuit.

4. The LDO circuit according to claim 1, wherein: The second voltage switching circuit includes a third PMOS transistor, the drain of the third PMOS transistor constitutes the second end of the second voltage switching circuit, the source of the third PMOS transistor and the substrate of the third PMOS transistor are connected to constitute the first end of the second voltage switching circuit, and the gate of the third PMOS transistor constitutes the control end of the second voltage switching circuit.

5. The LDO circuit according to claim 1, wherein: The third voltage switching circuit includes a fourth PMOS tube, the drain of the fourth PMOS tube constitutes the second end of the third voltage switching circuit, the source of the fourth PMOS tube constitutes the first end of the third voltage switching circuit, the gate of the fourth PMOS tube constitutes the control end of the third voltage switching circuit, and the substrate of the fourth PMOS tube is connected to the substrate of the power tube.

6. The LDO circuit according to claim 1, wherein: The first voltage switching circuit includes a first NMOS transistor and a first inverter. The drain of the first NMOS transistor constitutes a first end of the first voltage switching circuit. The source of the first NMOS transistor and the substrate of the first NMOS transistor are connected to constitute a second end of the first voltage switching circuit. The gate of the first NMOS transistor is connected to the output end of the first inverter. The input end of the first inverter constitutes a control end of the first voltage switching circuit.

7. The LDO circuit according to claim 1, wherein: The second voltage switching circuit includes a second NMOS transistor and a second inverter. The drain of the second NMOS transistor constitutes the second end of the second voltage switching circuit. The source of the second NMOS transistor and the substrate of the second NMOS transistor are connected to constitute the first end of the second voltage switching circuit. The gate of the second NMOS transistor is connected to the output end of the second inverter. The input end of the second inverter constitutes the control end of the second voltage switching circuit.

8. The LDO circuit according to claim 1, wherein: The third voltage switching circuit includes a third NMOS transistor and a third inverter. The drain of the third NMOS transistor constitutes the second end of the second voltage switching circuit, the source of the third NMOS transistor constitutes the first end of the third voltage switching circuit, the gate of the third NMOS transistor is connected to the output end of the third inverter, the input end of the third inverter constitutes the control end of the third voltage switching circuit, and the substrate of the third NMOS transistor is connected to the substrate of the power tube.

9. The LDO circuit according to claim 1, wherein: The error amplifier circuit includes an error amplifier, a non-inverting input terminal of the error amplifier constitutes a feedback terminal of the error amplifier circuit, an inverting input terminal of the error amplifier constitutes a reference terminal of the error amplifier circuit, and an output terminal of the error amplifier constitutes an output terminal of the error amplifier circuit.

10. A power integrated circuit, characterized in that: The invention comprises the LDO circuit according to any one of claims 1 to 9.

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