Manufacturing method for etching small-size composite film layer structure
By utilizing polymer protective layer and Bosch etching process in the same etching device, drilling and debris problems in composite film layer structures are solved, and precise etching of high-deep aspect ratio silicon materials and device performance improvements are achieved.
Patent Information
- Application Number
- CN202411330466.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-24
- Publication Date
- 2024-12-24
AI Technical Summary
The prior art has the problem of drilling and debrising when etching the "silicon nitride-silicon nitride/silicon oxide" composite film layer structure, especially during the etching of the silicon layer, which affects the device performance and manufacturing accuracy.
Continuous etching is performed within the same etching device, using the polymer naturally generated during the etching process to form a protective layer, preventing drilling and etching, and performing passivation deposition processes and etching through the Bosch etching process cycle The etching process forms a high aspect ratio through silicon via hole.
It effectively prevents drilling and corrosion, improves etching accuracy and through-hole quality, reduces etching accuracy losses caused by environmental changes, and reduces wafer fragment problems caused by thermal stress.
Smart Images
Figure CN119181636A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor process technology, and in particular to a method for etching a small-size composite film layer structure. Background Art
[0002] In the prior art, etching of multi-layer composite film structures such as "silicon nitride-silicon-silicon nitride / silicon oxide" often faces many challenges. In particular, during the etching of the silicon layer, the undercutting phenomenon is particularly prominent (e.g. Figure 1 This not only damages the device performance, but also interferes with the smooth progress of subsequent processes. In addition, when etching to the bottom of the dielectric layer, fragmentation problems also occur from time to time. The existence of these problems limits the accuracy and reliability of device manufacturing.
[0003] In traditional processes, etching of such composite film structures usually requires transferring wafers between different etching machines and completing the process step by step according to the order of the film layers. Although this method is feasible to a certain extent, it is not ideal when pursuing high aspect ratio silicon material morphology. As the mainstream technology in the field of deep silicon etching, the Bosch process is favored for its high efficiency and ability to achieve high aspect ratio structures. However, even so, the Bosch process has its limitations when facing silicon substrates with special high aspect ratio structures. In particular, if you try to prevent drilling by adjusting the passivation protection link, it will break the "passivation-etching" balance inherent in the Bosch process, which will affect the correct formation of the silicon structure. Summary of the invention
[0004] In order to solve all or part of the problems of the above-mentioned prior art, the present invention provides a manufacturing method for etching a small-sized composite film layer structure. By continuously performing etching in the same etching equipment, during the process of etching the first dielectric layer, naturally generated polymer deposition forms a protective layer, which provides initial protection for the subsequent etching of the silicon substrate and effectively prevents the occurrence of drilling corrosion.
[0005] To achieve the above object, the present invention provides the following technical solutions:
[0006] A method for manufacturing a small-size composite film structure by etching, comprising:
[0007] S1. Providing a silicon substrate, a first dielectric layer is formed on the surface of the silicon substrate;
[0008] S2. placing the silicon substrate in a deep silicon etching chamber of the same etching equipment;
[0009] S3. Etching the first dielectric layer using a first etching process to form a first through hole penetrating the silicon substrate, and the polymer generated during the etching process is naturally deposited on the sidewalls and bottom of the first through hole to form a preliminary protective layer;
[0010] S4. Etching the silicon substrate below the first through hole using a Bosch etching process, wherein the Bosch etching process cyclically performs a passivation deposition process and a second etching process until a through silicon via is formed.
[0011] By continuously etching in the same etching equipment, the transfer of wafers between different machines is avoided, and the loss of etching accuracy caused by environmental changes is reduced. In the process of forming the first through hole, the polymer produced by etching is automatically deposited on the sidewalls and bottom of the through hole, forming a preliminary protective layer. This protective layer is crucial for subsequent etching steps, helping to protect the sidewalls of the through hole, preventing drilling when etching the silicon substrate, and ensuring the verticality and dimensional accuracy of the silicon through hole.
[0012] A second dielectric layer is formed on the bottom surface of the silicon substrate. When the Bosch etching process is performed in step S4, the second dielectric layer serves as an etching stop layer of the silicon substrate.
[0013] The method further includes step S5. Using a third etching process to etch the second dielectric layer to form a second through hole.
[0014] The etching steps of the first dielectric layer, the silicon substrate and the second dielectric layer are all performed sequentially in the same etching chamber.
[0015] The parameters of the first etching process in step S3 are: the etching chamber pressure is 10 mTorr to 200 mTorr, the etching source RF power is 1000 W to 5000 W, the etching bias RF power is 0 W to 1000 W, the etching gas includes SF6, AR, O2, C4F8, wherein the flow rate of SF6 is 200 SCCM to 2000 SCCM, the flow rate of AR is 100 SCCM to 1000 SCCM, the flow rate of O2 is 10 SCCM to 500 SCCM, the flow rate of C4F8 is 20 SCCM to 500 SCCM, and the etching time is 5 seconds to 200 seconds. The time will vary according to the etching depth, so it can exceed the upper limit.
[0016] The parameters of the passivation deposition process in step S4 are: the chamber pressure is 10 mTorr to 150 mTorr, the source RF power is 1000 W to 5000 W, the bias RF power is 0 W to 1000 W, the passivation deposition gas includes C4F8, wherein the flow rate of C4F8 is 200 SCCM to 1000 SCCM, and the passivation deposition time is 1 second to 8 seconds.
[0017] The parameters of the second etching process in step S4 are: the etching chamber pressure is 10 mTorr to 100 mTorr, the etching source RF power is 1000 W to 5000 W, the etching bias RF power is 50 W to 1000 W, the etching gas includes SF6 and O2, wherein the flow rate of SF6 is 100 SCCM to 1000 SCCM, the flow rate of O2 is 50 SCCM to 300 SCCM, and the etching time is 1 second to 10 seconds.
[0018] The parameters of the third etching process described in step S5 are: the etching chamber pressure is 10 mTorr to 200 mTorr, the etching source RF power is 1000 W to 5000 W, the etching bias RF power is 0 W to 1000 W, the etching gas includes SF6, AR, O2, C4F8, wherein the flow rate of SF6 is 200 SCCM to 2000 SCCM, the flow rate of AR is 100 SCCM to 1000 SCCM, the flow rate of O2 is 10 SCCM to 500 SCCM, the flow rate of C4F8 is 20 SCCM to 500 SCCM, and the etching time is 5 seconds to 200 seconds. The time will vary according to the etching depth, so it can exceed the upper limit.
[0019] The first dielectric layer and the second dielectric layer are designed to be a single-layer or multi-layer structure, and are composed of one of silicon nitride, silicon oxide or aluminum oxide.
[0020] In the method, the temperature during the etching process is controlled between 0°C and 20°C.
[0021] The present invention has at least the following beneficial effects:
[0022] By implementing a continuous etching process within the same etching equipment, the transfer of wafers between different machines is avoided, reducing the potential impact of environmental changes on etching accuracy. When etching the first dielectric layer, naturally occurring polymer deposition forms a protective layer. This innovative step effectively prevents drilling during the etching of the silicon substrate, improving the accuracy of etching and the quality of the through-holes. Through the cyclic passivation and etching steps of the Bosch etching process, the present invention achieves high aspect ratio etching of the silicon substrate while maintaining the verticality and accuracy of the through-hole sidewalls. When etching the second dielectric layer, the deep silicon etching chamber can not only provide sufficient energy to achieve deep etching of the bottom of the high aspect ratio structure, but also has a cooling function to effectively cool the wafer, thereby reducing the problem of wafer fragments caused by thermal stress. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0024] Figure 1 It is a structural schematic diagram of the drilling morphology of the silicon substrate in the prior art.
[0025] Figure 2 Schematic diagram of the structure of the composite membrane layer in Example 1 of the present invention.
[0026] Figure 3 Schematic diagram of the structure of the composite membrane layer in Example 2 of the present invention.
[0027] Reference numerals: 1 - first dielectric layer; 101 - first through hole; 2 - silicon substrate; 201 - through silicon via; 3 - second dielectric layer. DETAILED DESCRIPTION
[0028] The technical solutions in the specific embodiments of the present invention are described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0029] Example 1
[0030] In the embodiment of the present invention, in combination with reference Figure 2 As shown, a method for etching a small-size composite film layer structure is provided, comprising:
[0031] S1. Providing a silicon substrate, a first dielectric layer is formed on the surface of the silicon substrate;
[0032] S2. placing the silicon substrate in a deep silicon etching chamber of the same etching equipment, and performing an etching operation out of the chamber;
[0033] S3. Etching the first dielectric layer using a first etching process to form a first through hole extending through the silicon substrate, wherein the polymer generated during the etching process is naturally deposited on the sidewalls and bottom of the first through hole to form a preliminary protective layer;
[0034] S4. The silicon substrate located below the first through hole is etched using a Bosch etching process. The Bosch etching process includes: performing a passivation deposition process to form a continuous protective layer on the sidewall and bottom of the first through hole; performing a second etching process to etch the silicon substrate, and cyclically performing the passivation deposition process and the second etching process until a through silicon via is formed.
[0035] Among them, the first dielectric layer can be silicon oxide, silicon nitride or carbon-doped silicon dioxide, etc., or other dielectric layers. Its main function is to serve as an isolation layer during the etching process to prevent the etching gas from directly contacting the silicon substrate, thereby controlling the depth and shape of the etching and ensuring the accuracy of the etching process. The first dielectric layer can be designed as a single layer or a multilayer structure. The single-layer structure simplifies the manufacturing process, while the multilayer structure can provide more complex functions, such as achieving specific electrical or optical properties through the combination of different layers. If a multilayer structure is adopted, the material of each dielectric layer can be the same or different. This design can be customized according to the needs of actual applications to meet different performance requirements. In addition, the "first through hole" mentioned here refers to the through hole first formed during the etching process, which penetrates the first dielectric layer and reaches the silicon substrate. The formation of this through hole is the basis for subsequent etching steps. The "silicon through hole" is formed by further etching process on the basis of the first through hole. It penetrates the entire silicon substrate to form the required high aspect ratio structure.
[0036] In this embodiment, the first dielectric layer on the silicon substrate is first etched using a first etching process, with the purpose of forming a first through hole that penetrates the silicon substrate. This step is the basis of the entire process. During the etching process, the reaction of the etching gas with the first dielectric layer causes the polymer to be naturally deposited on the sidewalls and bottom of the through hole to form a preliminary protective layer. This protective layer is essential for maintaining the shape of the through hole and preventing damage to the sidewalls during subsequent etching. Subsequently, the silicon substrate located below the first through hole is etched using a Bosch etching process. The Bosch process is a deep silicon etching technology that is particularly suitable for manufacturing microstructures with a high aspect ratio. The Bosch etching process includes periodically performing a passivation deposition process and a second etching process. The passivation deposition process forms a continuous protective layer on the sidewalls and bottom of the through hole, while the second etching process removes the silicon material and gradually penetrates into the silicon substrate. By alternately performing the passivation deposition and etching processes, the etching depth can be accurately controlled, and a silicon through hole with a high aspect ratio is finally formed.
[0037] The innovation of the present invention is that the entire process is completed in the same etching chamber, and the polymer naturally generated when etching the first dielectric layer is used to form a preliminary protective layer, which effectively prevents the silicon substrate from being drilled when etching begins. This method not only retains the high efficiency and high aspect ratio characteristics of the Bosch process, but also achieves fine and precise etching of specific structures through the naturally deposited protective layer, meeting the manufacturing requirements for silicon substrates with special high aspect ratio structures. Through this optimized process flow, the accuracy of the etching process and the high quality of the product can be ensured.
[0038] Specifically, the parameters of the first etching process are: the pressure in the etching chamber is 40 mTorr, the etching source RF power is 2500 W, the etching bias RF power is 100 W, the etching gas includes SF6, AR, O2, wherein the flow rate of SF6 is 650 SCCM, the flow rate of AR is 100 SCCM, the flow rate of O2 is 100 SCCM, and the etching time is 40 seconds; the pressure in the etching chamber can also be 150 mTorr, the etching source RF power is 0 W, the etching bias RF power is 500 W, the etching gas includes AR, C4F8, wherein the flow rate of C4F8 is 100 SCCM, the flow rate of AR is 300 SCCM, and the etching time is 180 seconds, and the time is related to the etching depth. Time is related to the etching depth.
[0039] Among them, the etching chamber pressure is 10 mTorr to 200 mTorr, the etching source RF power is 1000 W to 5000 W, the etching bias RF power is 0 W to 1000 W, and the etching gases include SF6, AR, O2, and C4F8, among which the flow rate of SF6 is 200 SCCM to 2000 SCCM, the flow rate of AR is 100 SCCM to 1000 SCCM, the flow rate of O2 is 10 SCCM to 500 SCCM, and the flow rate of C4F8 is 20 SCCM to 500 SCCM. The etching time is 5 seconds to 200 seconds, and the time will vary according to the etching depth, so it can exceed the upper limit.
[0040] Parameters of Bosch etching process, including passivation deposition process: during passivation, the chamber pressure is 60 mTorr, the source RF power power is 2500 W, the bias RF power power is 0 W, the passivation gas includes C4F8, where the flow rate of C4F8 is 425 SCCM, and the passivation time is 1.6 seconds; during etching, it needs to be divided into two parts, so the pressure in the etching chamber is 25 mTorr and 35 mTorr respectively, the etching source RF power power is 2500 W, the etching bias RF power power is 140 to 150 W and 0 W respectively, the etching gas includes SF6, where the flow rate of SF6 is 375 SCCM and 650 SCCM respectively, and the etching time is 3 seconds and 2 seconds respectively.
[0041] Among them, the chamber pressure is 10 mTorr to 150 mTorr, the source RF power is 1000 W to 5000 W, the bias RF power is 0 W to 1000 W, the passivation deposition gas includes C4F8, wherein the flow rate of C4F8 is 200 SCCM to 1000 SCCM, and the passivation deposition time is 1 second to 8 seconds; in the second step of the etching process, the etching chamber pressure is 10 mTorr to 100 mTorr, the etching source RF power is 1000 W to 5000, the etching bias RF power is 50 W to 1000 W, the etching gas includes SF6, O2, wherein the flow rate of SF6 is 100 SCCM to 1000 SCCM, the flow rate of O2 is 50 SCCM to 300 SCCM, and the etching time is 1 second to 5 seconds. These values are all relatively suitable numerical ranges obtained through experimental verification. In addition to the above parameters, other parameter values can also be selected as long as the corresponding effect can be achieved.
[0042] By controlling the temperature during the etching process within a suitable range of 0-20°C, it is possible to ensure a fast etching rate and avoid problems such as thermal damage caused by excessive temperature. In this embodiment, the etching equipment used is SPTSOmegaFxp, and the design of the deep silicon etching chamber takes into account the effective transfer of energy and temperature management. The chamber can not only provide the necessary energy to the bottom of the high aspect ratio structure to achieve deep and uniform etching, but also integrates a cooling mechanism. This mechanism can effectively cool the wafer during the etching process, significantly reducing the risk of wafer fragments caused by thermal stress.
[0043] Example 2
[0044] A method for etching a small-size composite film structure is provided. The difference from Example 1 is that in this embodiment, Figure 3 As shown, a second dielectric layer is also formed on the bottom surface of the silicon substrate. When etching the silicon substrate, the second dielectric layer serves as an etching stop layer of the silicon substrate to ensure that the etching process automatically stops when a predetermined depth is reached, thereby improving the etching accuracy. After the silicon substrate is etched through, the second dielectric layer is exposed, and the third etching process is continued to be used to etch the newly exposed second dielectric layer. Through the third etching process, a second through hole penetrating the second dielectric layer is formed.
[0045] The second dielectric layer can be made of a variety of materials, including but not limited to silicon oxide, silicon nitride, and possible other dielectric materials such as Al2O3. The key is that the selected material must meet the required isolation performance to ensure that the areas that do not need to be etched can be effectively protected during the etching process. The design of the second dielectric layer can be a single-layer or multi-layer structure to meet different electrical and mechanical performance requirements. The single-layer structure simplifies the manufacturing process, while the multi-layer structure can provide more complex functions, such as achieving specific electrical or optical properties through the combination of different layers. The material of each dielectric layer can be selected to be the same or different according to actual needs.
[0046] Specifically, the parameters of the third etching process are: the pressure in the chamber is 40 mTorr, the power of the etching source RF power is 2500 watts, the power of the etching bias RF power is 100 watts, the etching gas includes SF6, AR, and O2, wherein the flow rate of SF6 is 650 SCCM, the flow rate of AR is 100 SCCM, and the flow rate of O2 is 100 SCCM, and the etching time is 40 seconds; the pressure in the etching chamber can also be 150 mTorr, the power of the etching source RF power is 0 watts, the power of the etching bias RF power is 500 watts, the etching gas includes AR and C4F8, wherein the flow rate of C4F8 is 100 SCCM, the flow rate of AR is 300 SCCM, and the etching time is 180 seconds, and the time is related to the etching depth. Time is related to the etching depth.
[0047] Among them, the etching chamber pressure is 10 mTorr to 200 mTorr, the etching source RF power is 1000 W to 5000 W, the etching bias RF power is 0 W to 1000 W, and the etching gas includes SF6, AR, O2, and C4F8, wherein the flow rate of SF6 is 200 SCCM to 2000 SCCM, the flow rate of AR is 100 SCCM to 1000 SCCM, the flow rate of O2 is 10 SCCM to 500 SCCM, and the flow rate of C4F8 is 20 SCCM to 500 SCCM. The time will vary according to the etching depth, so it can exceed the upper limit. These values are all relatively suitable numerical ranges obtained through experimental verification. In addition to the above parameters, other parameter values can also be selected as long as the corresponding effect can be achieved.
[0048] In summary, the manufacturing method provided by the present invention realizes accurate processing of different film layer structures by using a continuous etching method without leaving the chamber in the same etching equipment. This improved technology not only effectively reduces the drilling and fragmentation problems that may occur during the etching process, but also promotes the realization of high aspect ratio silicon material morphology under small size, and further improves the performance of the final device. First, the first dielectric layer is etched by the first etching process to form a first through hole that penetrates the silicon substrate. During the preliminary etching process, due to the reaction of the etching gas and the dielectric layer, a polymer will be naturally deposited on the side wall and bottom of the first through hole to form a preliminary protective layer. Subsequently, the silicon substrate is further etched by the Bosch etching process to form a through hole structure with a high aspect ratio. The Bosch process effectively avoids lateral etching through periodic passivation and etching steps, and ensures the verticality and precision of the through hole. The initially formed protective layer not only protects the side wall of the through hole and avoids drilling, but also provides necessary protection for subsequent etching steps. Through the above steps, the present invention can form a through hole structure with high precision and high aspect ratio on a silicon substrate. These structures are of great significance for the fabrication of micro-devices in fields such as microelectronics, optoelectronics, and biomedical engineering.
[0049] It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made to the present invention without departing from the principles of the present invention. These improvements and modifications also fall within the scope of protection of the claims of the present invention.
Claims
1. A method for etching a small-size composite film structure, characterized in that: include: S1. Providing a silicon substrate, a first dielectric layer is formed on the surface of the silicon substrate; S2. placing the silicon substrate in a deep silicon etching chamber of the same etching equipment; S3. Etching the first dielectric layer using a first etching process to form a first through hole penetrating the silicon substrate, and the polymer generated during the etching process is naturally deposited on the sidewalls and bottom of the first through hole to form a preliminary protective layer; S4. Etching the silicon substrate below the first through hole using a Bosch etching process, wherein the Bosch etching process cyclically performs a passivation deposition process and a second etching process until a through silicon via is formed.
2. The method according to claim 1, characterized in that A second dielectric layer is formed on the bottom surface of the silicon substrate. When the Bosch etching process is performed in step S4, the second dielectric layer serves as an etching stop layer of the silicon substrate.
3. The method according to claim 2, characterized in that The method further includes step S5. Using a third etching process to etch the second dielectric layer to form a second through hole.
4. The method according to claim 3, characterized in that The etching steps of the first dielectric layer, the silicon substrate and the second dielectric layer are all performed sequentially in the same etching chamber.
5. The method according to claim 1, characterized in that The parameters of the first etching process in step S3 are: the etching chamber pressure is 10 mTorr to 150 mTorr, the etching source RF power is 1000 W to 5000 W, the etching bias RF power is 0 W to 1000 W, and the etching gas includes SF6, AR, O2, and C4F8, wherein the flow rate of SF6 is 200 SCCM to 2000 SCCM, the flow rate of AR is 100 SCCM to 1000 SCCM, the flow rate of O2 is 10 SCCM to 500 SCCM, and the flow rate of C4F8 is 20 SCCM to 500 SCCM.
6. The method according to claim 1, characterized in that The parameters of the passivation deposition process in step S4 are: the etching chamber pressure is 10 mTorr to 150 mTorr, the etching source RF power is 1000 W to 5000 W, the etching bias RF power is 0 W to 1000 W, and the passivation deposition gas includes C4F8, wherein the flow rate of C4F8 is 200 SCCM to 1000 SCCM.
7. The method according to claim 1, characterized in that The parameters of the second etching process in step S4 are: the etching chamber pressure is 10 mTorr to 100 mTorr, the etching source RF power is 1000 W to 5000 W, the etching bias RF power is 50 W to 1000 W, and the etching gas includes SF6 and O2, wherein the flow rate of SF6 is 100 SCCM to 1000 SCCM, and the flow rate of O2 is 50 SCCM to 300 SCCM.
8. The method according to claim 3, characterized in that The parameters of the third etching process described in step S5 are: the etching chamber pressure is 10 mTorr to 150 mTorr, the etching source RF power is 1000 W to 5000 W, the etching bias RF power is 0 W to 1000 W, and the etching gas includes SF6, AR, O2, and C4F8, wherein the flow rate of SF6 is 200 SCCM to 2000 SCCM, the flow rate of AR is 100 SCCM to 1000 SCCM, the flow rate of O2 is 10 SCCM to 500 SCCM, and the flow rate of C4F8 is 20 SCCM to 500 SCCM.
9. The method according to claim 2, characterized in that: The first dielectric layer and the second dielectric layer are designed to be a single-layer or multi-layer structure, and are composed of one of silicon nitride, silicon oxide or aluminum oxide.
10. The method according to claim 1, characterized in that The temperature during the etching process is controlled between 0°C and 20°C.