Power device unit and semiconductor packaging structure

Abstract

The present invention provides a power device unit and a semiconductor packaging structure, wherein the power device unit comprises: a semiconductor chip, a source electrode is arranged on the first surface of the semiconductor chip, and a drain electrode is arranged on the second surface of the semiconductor chip; a first terminal comprises a first connecting plate segment and a first lead-out plate segment connected to the first connecting plate segment, the first connecting plate segment is conductively connected to the source electrode; a second terminal comprises a second connecting plate segment and a second lead-out plate segment connected to the second connecting plate segment, the second connecting plate segment is conductively connected to the drain electrode; wherein the first connecting plate segment, the semiconductor chip and the second connecting plate segment are arranged in a stacked manner. The technical solution of the present application can effectively solve the problem of low reliability of power semiconductor devices in the related art.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power device unit and a semiconductor packaging structure. Background Art

[0002] Power semiconductor devices are a type of semiconductor devices designed to process and control higher voltages and currents. Unlike small-signal semiconductor devices used for signal processing, power semiconductor devices are mainly used for the conversion, distribution and control of electrical energy, and they play a vital role in the field of power electronics.

[0003] Silicon carbide devices are one type of power semiconductor devices. With their excellent physical and chemical properties, silicon carbide devices have shown significant advantages in the field of power and radio frequency devices. Compared with traditional silicon devices, silicon carbide devices have lower on-resistance, faster switching speed and higher operating temperature capability, so they are widely used in power supplies, automobiles, railways, industrial equipment and home consumer electronic devices. The performance advantages of silicon carbide devices are mainly reflected in stronger high-voltage characteristics, better high-temperature characteristics and lower energy loss. In related technologies, due to the large parasitic inductance of silicon carbide devices, silicon carbide devices may generate additional losses during the conduction and cutoff process. These losses are released in the form of heat, which may cause the device to overheat and affect the heat dissipation performance and life of the device. In addition, the larger mutual inductance may cause the silicon carbide device to be subjected to greater thermal and electrical stress during the switching process, which may accelerate the aging process of the silicon carbide device and reduce the reliability and life of the device. Summary of the invention

[0004] The main purpose of the present invention is to provide a power device unit and a semiconductor packaging structure to solve the problem of low reliability of power semiconductor devices in the related art.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present invention, a power device unit is provided, comprising: a semiconductor chip, a source electrode is arranged on the first surface of the semiconductor chip, and a drain electrode is arranged on the second surface of the semiconductor chip; a first terminal, comprising a first connecting plate segment and a first lead-out plate segment connected to the first connecting plate segment, the first connecting plate segment is conductively connected to the source electrode; a second terminal, comprising a second connecting plate segment and a second lead-out plate segment connected to the second connecting plate segment, the second connecting plate segment is conductively connected to the drain electrode; wherein the first connecting plate segment, the semiconductor chip and the second connecting plate segment are arranged in an overlapping manner.

[0006] Furthermore, the first lead-out plate segment and the second lead-out plate segment extend in the same direction, the first terminal further includes a first intermediate plate segment arranged between the first connecting plate segment and the first lead-out plate segment, the second terminal further includes a second intermediate plate segment arranged between the second connecting plate segment and the second lead-out plate segment, and the distance between the first intermediate plate segment and the second intermediate plate segment gradually increases in the direction away from the semiconductor chip.

[0007] Further, a minimum distance between the first lead-out plate segment and the second lead-out plate segment is greater than or equal to a maximum distance between the first middle plate segment and the second middle plate segment.

[0008] Further, a projection of the first connecting plate segment on the source electrode occupies 50% to 90% of the source electrode; and / or a projection of the second connecting plate segment on the drain electrode occupies 50% to 90% of the drain electrode.

[0009] Further, the thickness of the first connecting plate segment is greater than the thickness of the second connecting plate segment; and / or the area of ​​the first connecting plate segment is smaller than the area of ​​the second connecting plate segment.

[0010] Further, the thickness of the first connecting plate segment is between 0.5 mm and 2.5 mm; and / or the thickness of the second connecting plate segment is between 0.5 mm and 2 mm.

[0011] Furthermore, the first connecting plate segment has an avoidance recess, which is arranged on a surface of the first connecting plate segment facing the semiconductor chip, and the source electrode includes a first source electrode and a second source electrode which are arranged at intervals, and the avoidance recess is located between the first source electrode and the second source electrode.

[0012] Furthermore, the power device unit also includes a third terminal, a gate spaced apart from the source is provided on the first surface of the semiconductor chip, the third terminal is conductively connected to the gate, the third terminal is a plate-like structure and the thickness direction of the third terminal is perpendicular to the thickness direction of the first terminal, and the extension direction of the third terminal is the same as the extension direction of the first terminal.

[0013] Furthermore, the power device unit further includes a first heat sink, which is arranged on a surface of the first connecting plate segment away from the source; and / or the power device unit further includes a second heat sink, which is arranged on a surface of the second connecting plate segment away from the drain.

[0014] According to another aspect of the present invention, a semiconductor packaging structure is provided, including: a housing having a receiving cavity; a power device unit, a part of which is disposed in the receiving cavity, and the power device unit is the power device unit described above.

[0015] Furthermore, an inlet and an outlet are provided on the shell, and the heat dissipation medium can enter into the accommodating cavity through the inlet and be discharged to the outside of the shell through the outlet.

[0016] Furthermore, the shell includes a first cover plate, a second cover plate and a surrounding plate arranged between the first cover plate and the second cover plate, the surrounding plate includes a first side plate and a second side plate arranged opposite to each other, the inlet is arranged on the first side plate, the outlet is arranged on the second side plate, and the first lead-out plate section of the first terminal and the second lead-out plate section of the second terminal of the power device unit are both passed through the first cover plate.

[0017] Furthermore, the first side plate and the second side plate extend along a preset direction, there are multiple power device units, and the multiple power device units are arranged at intervals along the preset direction. The semiconductor chip of the power device unit is arranged at an angle to the first side plate. In the preset direction, the first end of the first side plate and the first end of the second side plate are arranged correspondingly, the second end of the first side plate and the second end of the second side plate are arranged correspondingly, the inlet is located at the first end of the first side plate, and the outlet is located at the second end of the second side plate.

[0018] Furthermore, the semiconductor packaging structure also includes a plurality of flow channel plates arranged at intervals along a preset direction, and the plurality of flow channel plates are alternately arranged with the plurality of power device units. In two adjacent flow channel plates, one end of one flow channel plate is connected to the first side plate, and the other end is spaced apart from the second side plate, and one end of the other flow channel plate is connected to the second side plate, and the other end is spaced apart from the first side plate.

[0019] Furthermore, the semiconductor packaging structure further includes a first sealing sleeve arranged between the first lead-out plate section of the first terminal and the housing, and a second sealing sleeve arranged between the second lead-out plate section of the second terminal and the housing.

[0020] By applying the technical solution of the present invention, the semiconductor chip can realize the basic functions of the power device unit, the first surface of the semiconductor chip is provided with a source electrode, the second surface of the semiconductor chip is provided with a drain electrode, the first terminal is conductively connected to the source electrode, the second terminal is conductively connected to the drain electrode, the first terminal and the second terminal are conductively connected to external components, so that the semiconductor chip and the external components form a current loop, the first terminal includes a first connecting plate segment and a first lead-out plate segment connected to the first connecting plate segment, the first lead-out plate segment is used to be conductively connected to the external component, the first connecting plate segment is used to be conductively connected to the source electrode, the second terminal includes a second connecting plate segment and a second lead-out plate segment connected to the second connecting plate segment, the second lead-out plate segment is used to be conductively connected to the external component, The second connecting plate segment is used for conductive connection with the drain. Since the first connecting plate segment, the semiconductor chip and the second connecting plate segment are stacked, the spacing between the first connecting plate segment and the second connecting plate segment is small, and the first connecting plate segment and the second connecting plate segment are in a parallel or nearly parallel state, so that the area surrounded by the current loop formed between the first terminal, the semiconductor chip and the second terminal is small, so that the parasitic inductance of this loop is small, and then the parasitic inductance of the power device unit is small, so that the power device unit generates less additional losses during the conduction and cutoff process, so that these losses released in the form of heat are small, reducing the possibility of overheating of the power device unit, and thus ensuring the reliability of the power device unit. Therefore, the technical solution of the present application can effectively solve the problem of low reliability of power semiconductor devices in related technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings constituting a part of the present application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0022] Figure 1 A schematic diagram of the three-dimensional structure of an embodiment of a power device unit according to the present invention is shown;

[0023] Figure 2 Shows Figure 1 A schematic top view of a power device unit;

[0024] Figure 3 Shows Figure 1 A bottom view schematic diagram of a power device unit;

[0025] Figure 4 Shows Figure 1 A front view schematic diagram of a power device unit;

[0026] Figure 5 Shows Figure 1 A side view schematic diagram of a power device unit;

[0027] Figure 6 Shows Figure 1 A schematic diagram of the split structure of a power device unit;

[0028] Figure 7 Shows Figure 1 A schematic diagram of the split structure of the power device unit from another angle;

[0029] Figure 8 Shows Figure 1 A schematic front view of a split structure of a power device unit;

[0030] Fig. 9 A schematic cross-sectional view of an embodiment of a semiconductor package structure according to the present invention is shown;

[0031] Fig.10 Shows Fig. 9 A schematic cross-sectional view of a semiconductor package structure from another angle.

[0032] The above drawings include the following reference numerals:

[0033] a. Preset direction;

[0034] 10. semiconductor chip; 11. source; 111. first source; 112. second source; 12. drain; 13. gate;

[0035] 20. first terminal; 21. first connecting plate section; 211. avoidance recess; 22. first lead-out plate section; 23. first intermediate plate section;

[0036] 30. second terminal; 31. second connecting plate section; 32. second lead-out plate section; 33. second intermediate plate section;

[0037] 40. The third terminal;

[0038] 51. a first heat sink; 52. a second heat sink;

[0039] 60. Shell; 61. Accommodating chamber; 62. Inlet; 63. Outlet; 64. First cover plate; 65. Second cover plate; 66. Enclosure; 661. First side plate; 662. Second side plate; 67. Flow channel plate. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0042] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present invention. Meanwhile, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, and therefore, once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0043] like Figures 1 to 8 As shown, the present application provides a power device unit, and an embodiment of the power device unit of the present application includes: a semiconductor chip 10, a first terminal 20, and a second terminal 30; a source 11 is provided on the first surface of the semiconductor chip 10, and a drain 12 is provided on the second surface of the semiconductor chip 10; the first terminal 20 includes a first connecting plate segment 21 and a first lead-out plate segment 22 connected to the first connecting plate segment 21, and the first connecting plate segment 21 is conductively connected to the source 11; the second terminal 30 includes a second connecting plate segment 31 and a second lead-out plate segment 32 connected to the second connecting plate segment 31, and the second connecting plate segment 31 is conductively connected to the drain 12; wherein the first connecting plate segment 21, the semiconductor chip 10 and the second connecting plate segment 31 are stacked.

[0044] By applying the technical solution of this embodiment, the semiconductor chip 10 can realize the basic functions of the power device unit. The first surface of the semiconductor chip 10 is provided with a source 11, and the second surface of the semiconductor chip 10 is provided with a drain 12. The first terminal 20 is conductively connected to the source 11, and the second terminal 30 is conductively connected to the drain 12. The first terminal 20 and the second terminal 30 are conductively connected to external components, so that the semiconductor chip 10 and the external components form a current loop. The first terminal 20 includes a first connecting plate segment 21 and a first lead-out plate segment 22 connected to the first connecting plate segment 21, and the first lead-out plate segment 22 is used for conductive connection with external components. The first connecting plate segment 21 is used for conductive connection with the source 11. The second terminal 30 includes a second connecting plate segment 31 and a second lead-out plate segment 32 connected to the second connecting plate segment 31. The second lead-out plate segment 32 The first connecting plate segment 21, the semiconductor chip 10 and the second connecting plate segment 31 are arranged in a stacked manner, so that the spacing between the first connecting plate segment 21 and the second connecting plate segment 31 is small, and the first connecting plate segment 21 and the second connecting plate segment 31 are arranged in parallel or nearly parallel, so that the area surrounded by the current loop formed between the first terminal 20, the semiconductor chip 10 and the second terminal 30 is small, so that the parasitic inductance of this loop is small, and then the parasitic inductance of the power device unit is small, so that the power device unit generates less additional losses during the conduction and cutoff process, so that these losses released in the form of heat are small, and the possibility of overheating of the power device unit is reduced, thereby ensuring the reliability of the power device unit. Therefore, the technical solution of this embodiment can effectively solve the problem of low reliability of power semiconductor devices in related technologies.

[0045] It should be noted that in the case of alternating or changing current (the application conditions of power semiconductor devices will have repeated switching conditions, which can be understood as the current is constantly switched on and off to form a changing current condition), the inductance of the conductor will form a certain impedance (in this embodiment, after the semiconductor chip 10 is turned on, the current loop formed by the first terminal 20, the semiconductor chip 10 and the second terminal 30 is the above-mentioned conductor), and the higher the frequency, the greater the impedance and the greater the accompanying loss. The current loop formed by the first terminal 20, the semiconductor chip 10 and the second terminal 30 will surround a certain area. According to the law of electromagnetic induction, if there is a changing magnetic field in the area surrounded by this current loop, an induced current will be generated in the current loop, forming interference and loss. The changes in the spatial magnetic field are everywhere, so the larger the area surrounded by the current loop, the more serious the loss. In the related art, the chip (drain), drain copper layer, and ceramic lining are connected in sequence, the source copper layer is also connected to the ceramic lining, the drain copper layer and the source copper layer are connected on the same surface of the ceramic lining and are spaced apart, the drain terminal is connected to the drain copper layer, the source terminal is connected to the source copper layer, and the source copper layer and the source of the chip are also connected through bonding wires, thereby forming a current loop of the drain terminal, drain copper layer, chip, bonding wire, source copper layer, and source terminal. The area enclosed by this current loop is obviously larger, and its parasitic inductance is also larger.

[0046] like Figures 1 to 8 As shown, the first lead plate section 22 and the second lead plate section 32 extend in the same direction, the first terminal 20 further includes a first intermediate plate section 23 disposed between the first connection plate section 21 and the first lead plate section 22, the second terminal 30 further includes a second intermediate plate section 33 disposed between the second connection plate section 31 and the second lead plate section 32, and the distance between the first intermediate plate section 23 and the second intermediate plate section 33 gradually increases in the direction away from the semiconductor chip 10. Specifically, Figure 4 For example, “the first lead-out plate segment 22 and the second lead-out plate segment 32 extend in the same direction” means that the first lead-out plate segment 22 and the second lead-out plate segment 32 extend in the same direction. Figure 4The distance between the first middle plate segment 23 and the second middle plate segment 33 gradually increases in the direction away from the semiconductor chip 10, that is, the first middle plate segment 23 is arranged away from the semiconductor chip 10 in the direction from the first connecting plate segment 21 to the first lead-out plate segment 22, and the second middle plate segment 33 is arranged away from the semiconductor chip 10 in the direction from the second connecting plate segment 31 to the second lead-out plate segment 32, so that the distance between the first lead-out plate segment 22 and the second lead-out plate segment 32 is increased compared with the distance between the first connecting plate segment 21 and the second connecting plate segment 31 (the distance here refers to the minimum distance between the first connecting plate segment 21 and the second connecting plate segment 31), thereby increasing the insulation performance between the first lead-out plate segment 22 and the second lead-out plate segment 32, thereby ensuring the reliability of the power device unit. In addition, for the semiconductor packaging structure, the overall voltage level is improved, which means that the voltage level of the power device unit is improved, and then the voltage level of the semiconductor chip in the power device unit is improved. The higher the voltage level, the higher the safety performance requirements for the power device unit. In other words, it is necessary to increase the distance between the first lead-out plate segment 22 and the second lead-out plate segment 32 to cope with the increase in the voltage level of the semiconductor chip. Specifically, the distance between the first lead-out plate segment 22 and the second lead-out plate segment 32 is positively correlated with the voltage level of the semiconductor chip 10. More specifically, for every 1Kv increase in the voltage level of the semiconductor chip 10, the distance between the first lead-out plate segment 22 and the second lead-out plate segment 32 will increase by 2mm to 3mm. For every 1Kv increase in the voltage level of the semiconductor chip 10, the distance between the first lead-out plate segment 22 and the second lead-out plate segment 32 can increase by 2.4mm, 2.45mm, 2.5mm, 2.55mm or 2.6mm. In addition, the minimum distance between the first lead-out plate section 22 and the second lead-out plate section 32 is greater than or equal to the maximum distance between the first intermediate plate section 23 and the second intermediate plate section 33, that is, the first lead-out plate section 22 and the second lead-out plate section 32 are arranged in parallel or the distance between the first lead-out plate section 22 and the second lead-out plate section 32 gradually increases in the direction away from the semiconductor chip 10, thereby ensuring that the minimum distance between the first lead-out plate section 22 and the second lead-out plate section 32 is not less than the maximum distance between the first intermediate plate section 23 and the second intermediate plate section 33, thereby ensuring the insulation performance between the first lead-out plate section 22 and the second lead-out plate section 32.

[0047] In addition, the projection of the first connecting plate segment 21 on the source electrode 11 accounts for 50% to 90% of the source electrode 11, and the projection of the second connecting plate segment 31 on the drain electrode 12 accounts for 50% to 90% of the drain electrode 12. Specifically, the projection of the first connecting plate segment 21 on the source electrode 11 accounts for 50% to 90% of the source electrode 11, so that the area of ​​the first connecting plate segment 21 is relatively large, thereby reducing the self-inductance of the first connecting plate segment 21, and the projection of the second connecting plate segment 31 on the drain electrode 12 accounts for 50% to 90% of the drain electrode 12, so that the area of ​​the second connecting plate segment 31 is relatively large, thereby reducing the self-inductance of the second connecting plate segment 31. By reducing the self-inductance of the first connecting plate segment 21 and the second connecting plate segment 31, it is avoided that the self-inductance is too large and a large induced electromotive force is generated when the current changes, the energy lost in the form of heat is reduced, the efficiency of the circuit is guaranteed, and the Joule heat generated when the current changes can be reduced, and the additional heat loss is reduced, especially in high-frequency operation, and the possibility of overheating of the power device unit is reduced. Specifically, the projection of the first connecting plate segment 21 on the source 11 may account for 50%, 60%, 70%, 80%, 85% or 90% of the source 11 , and the projection of the second connecting plate segment 31 on the drain 12 may account for 50%, 60%, 70%, 80%, 85% or 90% of the drain 12 .

[0048] like Figures 1 to 8 As shown, the thickness of the first connecting plate segment 21 is greater than the thickness of the second connecting plate segment 31; since the source 11 generates more heat than the drain 12 during operation, the thickness of the first connecting plate segment 21 is greater than the thickness of the second connecting plate segment 31, so that the contact area between the first connecting plate segment 21 and the heat dissipation medium (mentioned later) is larger, which is more conducive to the heat dissipation of the power device unit, thereby ensuring the reliability of the power device unit. The area of ​​the first connecting plate segment 21 is smaller than the area of ​​the second connecting plate segment 31, thereby ensuring the contact area between the second connecting plate segment 31 and the heat dissipation medium to ensure the heat dissipation effect on the power device unit.

[0049] like Figures 1 to 8 As shown, the thickness of the first connecting plate segment 21 is between 0.5 mm and 2.5 mm; the thickness of the second connecting plate segment 31 is between 0.5 mm and 2 mm. Specifically, such a configuration ensures, on the one hand, the transfer efficiency of the heat generated by the semiconductor chip 10 during operation (the path from the semiconductor chip to the heat sink), and on the other hand, ensures the connection strength between the first connecting plate segment 21 and the semiconductor chip 10 and between the second connecting plate segment 31 and the semiconductor chip 10. Specifically, the thickness of the first connecting plate segment 21 can be 0.5 mm, 0.75 mm, 1 mm, 1.5 mm, 2 mm or 2.5 mm; the thickness of the second connecting plate segment 31 can be 0.5 mm, 0.75 mm, 1 mm, 1.5 mm or 2 mm.

[0050] like Figures 1 to 8As shown, the first connecting plate segment 21 has an avoidance recess 211, which is arranged on the surface of the first connecting plate segment 21 facing the semiconductor chip 10. The source 11 includes a first source 111 and a second source 112 arranged at intervals, and the avoidance recess 211 is located between the first source 111 and the second source 112. Specifically, a gate 13 arranged at intervals from the source 11 is arranged on the first surface of the semiconductor chip 10. The gate 13 adjusts the current flow between the source 11 and the drain 12 by controlling the voltage thereon. When the voltage of the gate 13 is higher than the threshold voltage, a conductive channel is formed between the gate 13 and the substrate, allowing the current to flow from the source 11 to the drain 12. The gate 13 can be used to turn on or off the semiconductor chip 10 to control the circuit. When the voltage of the gate 13 is lower than the threshold voltage, the semiconductor chip 10 is in a closed state, and almost no current flows between the source 11 and the drain 12. A busbar of the gate 13 is disposed between the first source 111 and the second source 112 . The avoidance recess 211 can allow the first connecting plate segment 21 to avoid the busbar of the gate 13 .

[0051] like Figures 1 to 8 As shown, the power device unit further includes a third terminal 40, which is conductively connected to the gate 13, and is a plate-like structure, and the thickness direction of the third terminal 40 is perpendicular to the thickness direction of the first terminal 20, and the extension direction of the third terminal 40 is the same as the extension direction of the first terminal 20. Specifically, the third terminal 40 is a plate-like structure, and the thickness direction of the third terminal 40 is perpendicular to the thickness direction of the first terminal 20, so that the layout of the third terminal 40 and the first terminal 20 is more reasonable, so that the size of the power device unit is smaller.

[0052] In related technologies, the packaging technology route for power semiconductor devices is to seal the chip with insulating materials, increase the heat dissipation area and reduce thermal resistance by improving the connection structure and double-sided heat dissipation. However, as silicon carbide chip technology develops towards higher temperatures and greater power, the current packaging structure, even the double-sided heat dissipation structure, has become an important constraint on the silicon carbide chip to exert its high temperature and high power advantages.

[0053] In this embodiment, if Figures 1 to 8As shown, the power device unit further includes a first heat sink 51, which is disposed on the surface of the first connecting plate segment 21 away from the source 11; the power device unit further includes a second heat sink 52, which is disposed on the surface of the second connecting plate segment 31 away from the drain 12. Specifically, the arrangement of the first heat sink 51 and the second heat sink 52 makes it easier to dissipate the heat generated by the semiconductor chip 10 when it is working, reduces the thermal resistance of the semiconductor chip 10, thereby improving the heat dissipation of the power device unit and giving full play to the performance of the silicon carbide chip. Specifically, the number of the first heat sink 51 is greater than 2, the first heat sink 51 is a cylindrical structure, and a plurality of the first heat sinks 51 are arranged in an array. In other embodiments, the first heat sink may be a heat sink fin; the number of the second heat sink 52 is greater than 2, the second heat sink 52 is a cylindrical structure, and a plurality of the second heat sinks 52 are arranged in an array. In other embodiments, the second heat sink may be a heat sink fin.

[0054] In addition, in the present embodiment, a coating is provided on the semiconductor chip 10 except for the electrode. The preferred coating may be a PI coating, which may include multiple layers. PI is polyimide. The PI coating can ensure the insulation, long-term temperature resistance and water vapor isolation of the semiconductor chip 10. Coating the PI coating on the semiconductor chip 10 has many significant benefits, especially in improving the performance, reliability and durability of the semiconductor chip 10. The following are several main advantages of using a PI coating: 1. Excellent thermal stability: Polyimide materials have excellent thermal stability and can maintain their physical and chemical properties in high temperature environments. For chips working under high temperature conditions, the PI coating can effectively protect the chip from thermal stress, thereby extending the service life of the chip. PI materials are generally able to withstand high temperatures, which makes it very valuable in high-temperature electronic devices and high-power applications. 2. Electrical insulation performance: The PI coating has good electrical insulation performance, which can prevent electrical short circuits and leakage inside the chip. Its high insulation ensures the safe operation of the chip in high voltage and high frequency environments, reducing the risk of electrical failures. This is particularly important for electronic devices that require high reliability. 3. Structural strength and flexibility: Polyimide materials have both high structural strength and flexibility, and can resist external stress and impact. The PI coating applied on the surface of the chip can provide additional protection to prevent the chip from being damaged during manufacturing, transportation and use. At the same time, the flexibility of the PI coating enables it to adapt to slight deformations and stress changes on the chip surface, maintaining the integrity and effectiveness of the coating. 4. Chemical corrosion resistance: PI materials have excellent chemical corrosion resistance and can resist erosion by various chemical reagents, solvents and corrosive gases. Applying PI coating can effectively protect the chip from chemical corrosion, especially in some harsh working environments such as industrial control, chemical production and environmental monitoring equipment. 5. Low dielectric constant: Polyimide has a low dielectric constant, which is an important advantage for high-speed and high-frequency circuits. Low dielectric constant helps reduce loss and delay during signal transmission, improve signal transmission speed and integrity, and thus improve chip performance and efficiency. 6. Process compatibility: PI coating can be applied by a variety of process methods, such as spin coating, spray coating and dip coating, and the process is relatively simple and suitable for large-scale production. This process compatibility enables PI coating to be widely used in the manufacture of different types of chips and electronic devices, providing a flexible solution.

[0055] The power device unit of this embodiment can use a vacuum vapor welding process to achieve the connection between each terminal and the semiconductor chip. The vacuum vapor welding process is an advanced electronic welding technology, which is mainly used in the field of high-end welding. The vacuum vapor welding process achieves efficient, uniform and high-quality welding effects by precisely controlling the heating and cooling processes. It is an effective method to improve product welding quality and production efficiency, especially in applications that require high reliability and high-frequency characteristics, such as automotive electronics, aerospace and military enterprises. This process has been widely used. The vacuum vapor welding process has the following key features and advantages: Efficient heat transfer: Utilize the heat released by the heat medium (such as fluorine oil) during the gasification and liquefaction process to quickly heat the welding components and improve welding efficiency; Uniform heating: During the gas phase transition process, the temperature of the welding surface remains constant to ensure uniform heating of the components; Temperature control: The vacuum vapor welding process can achieve precise temperature control; Vacuum environment :The vacuum formed during the welding process helps to remove bubbles in the molten solder joint and improve the quality of the solder joint; Reduce voids: Due to the high heat transfer efficiency, the solder joint void rate is low during welding, which improves the reliability of welding; No inert gas required: The liquid medium used will not react chemically, so no inert gas protection is required; Reduce maintenance costs: The maintenance cost of the vacuum vapor phase welding process is low because the liquid medium loss rate is low; Flexibility: The latest developments in vacuum vapor phase welding technology have improved the flexibility of the process and can adapt to different production needs; Suitable for mass production: Due to its good heat transfer characteristics, vacuum vapor phase welding is suitable for welding large batches and difficult heat treatment assemblies; Environmental protection: The liquid medium used (such as fluorine oil) is inert and non-toxic, and the cost of waste disposal is low, which meets environmental protection requirements; Reduce energy consumption: The vapor phase reflow system has low power consumption; Compatibility: The process is compatible with tin-lead and lead-free solder pastes on the market and is suitable for a variety of welding needs.

[0056] In addition, the power device unit of this embodiment can use the nanosilver sintering process to realize the connection between each terminal and the semiconductor chip. The power device unit made by the nanosilver sintering process can withstand an operating temperature of more than 300°C, which is higher than the operating temperature of the power device unit made by the traditional welding process. The nanosilver sintering process is an innovative material connection technology, which is particularly suitable for the manufacture of electronic packaging and high-power devices. This process forms a connection layer with high conductivity and high thermal conductivity by sintering nano-scale silver particles at low temperature, and has significant technical advantages and wide application potential. The nanosilver sintering process has become an important technology in the manufacture of electronic packaging and high-power devices due to its low-temperature sintering, high conductivity, high thermal conductivity, structural strength and environmental protection characteristics. The nanosilver sintering process not only improves the performance and reliability of the semiconductor packaging structure, but also provides a green and environmentally friendly solution. The benefits of using the nanosilver sintering process are as follows: 1. Low-temperature sintering: One of the main advantages of the nanosilver sintering process is its low-temperature sintering characteristics. Traditional metal sintering processes usually require high temperatures (over 800°C) to achieve effective sintering, while nanosilver sintering can be completed between 200°C and 300°C. This low-temperature sintering feature makes the process particularly suitable for temperature-sensitive electronic components and materials, such as certain semiconductors and organic materials, thereby avoiding thermal damage and material degradation that may be caused by high temperatures. 2. High conductivity: The connection layer formed by the nanosilver particles after sintering has excellent conductive properties. As a metal, silver has the highest conductivity among all metals. The nanosilver sintering process can achieve close connection between silver particles at a lower temperature, thereby forming a low-resistance connection layer. This can significantly improve the performance and efficiency of electronic devices and circuit boards that require efficient electrical transmission. 3. High thermal conductivity: In addition to high conductivity, the nanosilver sintered layer also has high thermal conductivity. This means that it can effectively dissipate heat and avoid failure or performance degradation of electronic devices due to overheating. In high-power devices such as power semiconductors, LEDs, and high-frequency communication equipment, good thermal management is a key factor in ensuring their stability and long life. 4. Structural strength and stability: The nanosilver sintering process can achieve close bonding of silver particles at a lower temperature, forming a connection layer with high structural strength and stability. Compared with traditional welding methods, the nanosilver sintered layer has higher reliability and durability, and can better resist fatigue and damage caused by stress and thermal cycles. 5. Environmental protection characteristics: The nanosilver sintering process is lead-free and meets environmental protection requirements. Traditional welding processes often use lead-containing solders, which are harmful to the environment and health despite their superior performance. Nanosilver sintering provides a green alternative that is in line with the future environmental protection development trend in the field of electronic packaging and manufacturing. 6. Process flexibility: Nanosilver sintering materials are usually in the form of pastes and can be coated and printed by a variety of methods such as screen printing, spraying or dispensing. This flexibility enables the process to adapt to different manufacturing needs and design requirements, providing higher design freedom and manufacturing efficiency.

[0057] like Fig. 9 as well as Fig.10 As shown, the present application also provides a semiconductor packaging structure, which includes: a housing 60 having a receiving cavity 61; a power device unit, part of which is disposed in the receiving cavity 61, wherein the power device unit is the above-mentioned power device unit. The above-mentioned power device unit can effectively solve the problem of low reliability of power semiconductor devices in the related art, and the semiconductor packaging structure having the above-mentioned power device unit also has the above-mentioned advantages.

[0058] In this embodiment, the shell 60 can be made of ceramic materials, such as aluminum oxide, aluminum nitride, silicon nitride, zirconium oxide, silicon carbide, etc., so that the shell 60 has the advantages of high temperature resistance, corrosion resistance, good thermal conductivity, and high structural strength.

[0059] Alumina has excellent structural strength and chemical corrosion resistance, and is suitable for applications with high durability requirements. Alumina has many benefits in the packaging of power semiconductor devices, mainly including: good insulation performance: Alumina ceramics can effectively isolate circuits, avoid leakage problems, and improve circuit reliability; excellent high temperature resistance: Alumina ceramics remain stable in high temperature environments, are not easy to deform or oxidize, and are suitable for long-term high temperature operation occasions; high strength and hardness: Alumina ceramics have high structural strength and hardness, can withstand pressure and impact, and are not easy to break or wear; excellent chemical stability: It is corrosion-resistant to most chemicals and is suitable for use in chemical erosion environments; good processing performance: Alumina ceramics are easy to process, can be drilled, milled, cut, etc., to meet complex shapes and high precision requirements; light-shielding: Black alumina ceramics can be used as packaging scenarios with light-shielding requirements due to their strong absorption of visible light; airtightness: Black alumina ceramics have better airtightness than plastics, and are suitable for electronic packaging that requires high airtightness and heat shock resistance; cost-effectiveness: Alumina ceramic processing technology is mature, the production cost is low, and it has practical value.

[0060] Zirconia is known for its outstanding toughness and high temperature resistance, and performs well in high temperature and high stress environments. Zirconia has a series of advantages in power semiconductor device packaging, mainly including: high thermal conductivity: Zirconia has high thermal conductivity, which helps to dissipate heat of semiconductor devices and improve the stability and reliability of devices; good insulation performance: Zirconia is an excellent electrical insulation material that can effectively isolate circuits and prevent leakage problems; excellent structural performance: Zirconia has high strength and hardness, can withstand pressure and impact, and is not easy to break or wear; good chemical stability: Zirconia has good corrosion resistance to most chemicals and is suitable for use in chemical corrosion environments; high temperature resistance: Zirconia can remain stable in high temperature environments and is suitable for semiconductor packaging that needs to work at high temperatures; biocompatibility: In some special bio-semiconductor fields, the biocompatibility of zirconia is an important advantage; processing performance: Zirconia has good processing performance and can be precisely processed to meet the delicate requirements of semiconductor packaging; environmental stability: Zirconia can maintain stable performance under various environmental conditions, including humidity, ultraviolet radiation, etc.; low thermal expansion coefficient: Compared with materials such as silicon, zirconia has a lower thermal expansion coefficient, which helps to reduce the internal stress of the package caused by thermal cycles; transparency: In some special optical semiconductor packaging, the transparency of zirconia is an advantage.

[0061] Aluminum nitride has high thermal conductivity and low expansion coefficient, which can effectively dissipate heat and is suitable for high-power electronic devices. Aluminum nitride has a series of significant advantages in the packaging of power semiconductor devices: High thermal conductivity: Aluminum nitride has excellent thermal conductivity, which is 8 to 10 times the thermal conductivity of aluminum oxide, making it an ideal material for high-integration semiconductor substrates and electronic device packaging; Electrical insulation: As a covalently bonded compound, aluminum nitride has high resistivity and high insulation withstand voltage, making it suitable as an insulating material for electronic devices; Thermal expansion coefficient matching: The thermal expansion coefficient of aluminum nitride matches that of silicon, which helps reduce thermal stress and improve the reliability of packaging; Structural strength: Aluminum nitride ceramics have high hardness and good structural strength and can withstand higher loads; Chemical stability: Aluminum nitride can remain stable in a variety of environments and is not easily exposed to most It reacts with a number of chemicals, which makes it reliable for use in chemically corrosive environments; non-toxicity: compared with some other materials, aluminum nitride is non-toxic, which is an important advantage in applications where environmental and health impacts need to be considered; high temperature resistance: aluminum nitride can remain stable in a non-oxidizing atmosphere up to 2000°C and is suitable for high temperature application scenarios; resistance to molten metal erosion: aluminum nitride has good resistance to erosion by molten metal and is suitable for use as parts in contact with molten metal; optical properties: high-purity aluminum nitride ceramics are transparent and have excellent optical properties and can be used in applications requiring high transparency; environmentally friendly materials: aluminum nitride is an environmentally friendly material that does not contain harmful substances and meets the strict environmental protection requirements of modern industry.

[0062] Silicon carbide not only has high hardness and high wear resistance, but also can remain stable at extremely high temperatures, making it very popular in high-temperature electronic devices and high-frequency applications. The diversity and excellent properties of these ceramic materials provide a wide range of choices and significant performance improvements for the design and application of semiconductor packaging structures.

[0063] like Fig. 9 as well as Fig.10 As shown, the housing 60 is provided with an inlet 62 and an outlet 63, and the heat dissipation medium can enter the accommodating cavity 61 through the inlet 62 and be discharged to the outside of the housing 60 through the outlet 63. Specifically, the heat dissipation medium can directly contact the semiconductor chip 10, and can also directly contact the first heat dissipation member 51 and the second heat dissipation member 52, so that the contact area between the heat dissipation medium and the power device unit is large, so that the heat dissipation medium can better take away the heat generated by the semiconductor chip 10 during operation. Specifically, the heat dissipation medium can be a heat transfer oil, and the heat transfer oil can be a mineral heat transfer oil, an alkylbenzene heat transfer oil, an alkylnaphthalene heat transfer oil, an alkylbiphenyl heat transfer oil, a low-melting mixture of biphenyl and biphenyl ether, or an alkylbiphenyl ether heat transfer oil. The mineral heat transfer oil is a product of a certain distillation range in the petroleum refining process, and its main component is a mixture of long-chain alkanes and cycloalkanes. This type of heat transfer oil usually has good thermal conductivity and cost-effectiveness, and is suitable for medium and low temperature ranges; alkylbenzene type heat transfer oil is a compound with alkane side chains attached to the benzene ring, has a low vapor pressure, and does not vaporize under normal operation; it has good thermal stability and is suitable for applications below 300°C; alkylnaphthalene type heat transfer oil: The structure is a compound with alkane side chains attached to the benzene ring, which is suitable for gas phase heating systems in the range of 240~280°C; alkylbiphenyl type heat transfer oil is composed of a short-chain alkyl group combined with a biphenyl ring, has high thermal stability, and is suitable for use in the range of 300~340°C; biphenyl and biphenyl ether low-melting mixture type heat transfer oil is composed of 26.5% biphenyl and 73.5% biphenyl ether, has good thermal stability and high operating temperature (400°C), and is suitable for use in the range of 256~258°C; alkylbiphenyl ether type heat transfer oil is linked by an ether group in the middle of two benzene rings, has low viscosity and good fluidity, is suitable for use in low temperature environments, and the recommended maximum operating temperature does not exceed 330°C. In addition, the heat dissipation medium may also be electronic fluoride liquid.

[0064] In addition, it should be noted that in the related art, for safety reasons, traditional power devices usually have insulating glue encapsulated in a packaging shell (usually made of plastic), and after the insulating glue is cured, an insulating glue layer is formed to ensure the insulation performance of the power device. However, when the power device is aged and eliminated, these organic materials are difficult to recycle, which is not environmentally friendly, and improper operation can easily cause secondary pollution. In the semiconductor packaging structure of this embodiment, the heat dissipation medium itself has insulation properties. In addition to ensuring the insulation performance of the semiconductor packaging structure by using the heat dissipation medium, the potential risks of the semiconductor packaging structure to the environment after aging and elimination can be controlled by reducing the use of organic materials, and the use of ceramic materials, metal materials, etc. are easier to recycle than organic materials.

[0065] like Fig. 9 as well as Fig.10 As shown, the housing 60 includes a first cover plate 64, a second cover plate 65, and a surrounding plate 66 disposed between the first cover plate 64 and the second cover plate 65, the surrounding plate 66 includes a first side plate 661 and a second side plate 662 disposed opposite to each other, the inlet 62 is disposed on the first side plate 661, the outlet 63 is disposed on the second side plate 662, and the first lead-out plate segment 22 of the first terminal 20 and the second lead-out plate segment 32 of the second terminal 30 of the power device unit are both disposed on the first cover plate 64. Specifically, compared with the solution in which the inlet and the outlet are disposed adjacently, with such an arrangement, the housing 60 of this embodiment can allow the heat dissipation medium to flow out of the accommodation cavity 61 through a longer flow path after entering the accommodation cavity 61, so that the heat dissipation medium can fully exchange heat with the semiconductor chip 10, the first heat sink 51, and the second heat sink 52 and take away the heat from the semiconductor chip 10, thereby ensuring the heat dissipation effect on the semiconductor chip 10.

[0066] like Fig. 9 as well as Fig.10As shown, the first side plate 661 and the second side plate 662 extend along a preset direction a, there are multiple power device units, and the multiple power device units are arranged at intervals along the preset direction a. The semiconductor chip 10 of the power device unit is arranged at an angle to the first side plate 661. In the preset direction a, the first end of the first side plate 661 and the first end of the second side plate 662 are arranged correspondingly, and the second end of the first side plate 661 and the second end of the second side plate 662 are arranged correspondingly. The inlet 62 is located at the first end of the first side plate 661, and the outlet 63 is located at the second end of the second side plate 662. Specifically, the semiconductor chip 10 of the power device unit is arranged at an angle to the first side plate 661, so that the plane where the semiconductor chip 10 is located is not perpendicular to the axis of the inlet 62 and the axis of the outlet 63, thereby reducing the possibility of the semiconductor chip 10 hindering the flow of the heat dissipation medium, and also allowing the heat dissipation medium to fully contact with the first heat sink 51 and the second heat sink 52 for heat exchange. Compared with the scheme in which the inlet and outlet are arranged at the same end of the first side plate and the second side plate, the shell 60 of this embodiment can allow the heat dissipation medium to enter the accommodating cavity 61 and then be discharged after at least a diagonal distance, thereby increasing the flow path of the heat dissipation medium, so that the heat dissipation medium can fully exchange heat with the semiconductor chip 10, the first heat sink 51 and the second heat sink 52 and take away the heat from the semiconductor chip 10, thereby ensuring the heat dissipation effect of the semiconductor chip 10.

[0067] like Fig. 9 as well as Fig.10 As shown, the semiconductor packaging structure further includes a plurality of flow channel plates 67 arranged at intervals along a preset direction a, and the plurality of flow channel plates 67 are arranged alternately with the plurality of power device units. In two adjacent flow channel plates 67, one end of one flow channel plate 67 is connected to the first side plate 661, and the other end is arranged at intervals with the second side plate 662, and one end of the other flow channel plate 67 is connected to the second side plate 662, and the other end is arranged at intervals with the first side plate 661. Specifically, the arrangement of the plurality of flow channel plates 67 forms a multi-tortuous flow path in the accommodating cavity 61, thereby further increasing the flow path of the heat dissipation medium, so that the heat dissipation medium can fully exchange heat with the semiconductor chip 10, the first heat sink 51 and the second heat sink 52 of each power device unit and take away the heat from the semiconductor chip 10, thereby ensuring the heat dissipation effect on the semiconductor chip 10.

[0068] In addition, in the present embodiment, the semiconductor packaging structure further includes a first sealing sleeve disposed between the first lead-out plate section 22 of the first terminal 20 and the housing 60, and a second sealing sleeve disposed between the second lead-out plate section 32 of the second terminal 30 and the housing 60. Specifically, the first sealing sleeve is disposed so that the heat dissipation medium does not overflow the accommodation cavity 61 through the hole between the first terminal 20 and the housing 60, and the second sealing sleeve is disposed so that the heat dissipation medium does not overflow the accommodation cavity 61 through the hole between the second terminal 30 and the housing 60.

[0069] In addition, in other embodiments, arc-shaped chamfered portions are provided between the first cover plate and the enclosure plate, and between the second cover plate and the enclosure plate. Specifically, the arc-shaped chamfered portions can not only strengthen the connection strength between the first cover plate and the enclosure plate, and between the second cover plate and the enclosure plate, but also can provide an insulating colloid portion in the accommodating cavity, and the arc-shaped chamfered portions are also beneficial to the degassing effect of the degassing step in the process of pouring the insulating colloid to form the insulating colloid portion, thereby reducing the possibility of residual bubbles.

[0070] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the devices or elements referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of the present invention. The directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0071] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used herein to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" may include both "above" and "below". The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein are interpreted accordingly.

[0072] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0073] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A power device unit, characterized in that: include: A semiconductor chip (10), wherein a source electrode (11) is provided on a first surface of the semiconductor chip (10), and a drain electrode (12) is provided on a second surface of the semiconductor chip (10); A first terminal (20), comprising a first connecting plate segment (21) and a first lead-out plate segment (22) connected to the first connecting plate segment (21), wherein the first connecting plate segment (21) is conductively connected to the source electrode (11); A second terminal (30) comprising a second connecting plate segment (31) and a second lead-out plate segment (32) connected to the second connecting plate segment (31), wherein the second connecting plate segment (31) is conductively connected to the drain electrode (12); Wherein, the first connecting plate segment (21), the semiconductor chip (10) and the second connecting plate segment (31) are stacked; The first lead-out plate section (22) and the second lead-out plate section (32) extend in the same direction, the first terminal (20) further comprises a first intermediate plate section (23) arranged between the first connecting plate section (21) and the first lead-out plate section (22), the second terminal (30) further comprises a second intermediate plate section (33) arranged between the second connecting plate section (31) and the second lead-out plate section (32), and the distance between the first intermediate plate section (23) and the second intermediate plate section (33) gradually increases in a direction away from the semiconductor chip (10).

2. The power device unit according to claim 1, characterized in that: The minimum distance between the first lead-out plate segment (22) and the second lead-out plate segment (32) is greater than or equal to the maximum distance between the first middle plate segment (23) and the second middle plate segment (33).

3. The power device unit according to claim 1, characterized in that: The projection of the first connecting plate segment (21) on the source electrode (11) accounts for 50% to 90% of the source electrode (11); and / or, The projection of the second connecting plate section (31) on the drain (12) accounts for 50% to 90% of the drain (12).

4. The power device unit according to claim 1, characterized in that: The thickness of the first connecting plate segment (21) is greater than the thickness of the second connecting plate segment (31); and / or, The area of ​​the first connecting plate section (21) is smaller than the area of ​​the second connecting plate section (31).

5. The power device unit according to claim 1, characterized in that: The thickness of the first connecting plate segment (21) is between 0.5 mm and 2.5 mm; and / or, The thickness of the second connecting plate section (31) is between 0.5 mm and 2 mm.

6. The power device unit according to any one of claims 1 to 5, characterized in that: The first connecting plate segment (21) has an avoidance recess (211), the avoidance recess (211) being arranged on a surface of the first connecting plate segment (21) facing the semiconductor chip (10), the source electrode (11) comprising a first source electrode (111) and a second source electrode (112) arranged at intervals, the avoidance recess (211) being located between the first source electrode (111) and the second source electrode (112).

7. The power device unit according to claim 6, characterized in that: The power device unit further comprises a third terminal (40); a gate electrode (13) spaced apart from the source electrode (11) is arranged on the first surface of the semiconductor chip (10); the third terminal (40) is conductively connected to the gate electrode (13); the third terminal (40) is a plate-like structure; the thickness direction of the third terminal (40) is perpendicular to the thickness direction of the first terminal (20); and the extension direction of the third terminal (40) is the same as the extension direction of the first terminal (20).

8. The power device unit according to any one of claims 1 to 5, characterized in that: The power device unit further comprises a first heat sink (51), the first heat sink (51) being arranged on a surface of the first connecting plate segment (21) away from the source electrode (11); and / or, The power device unit further comprises a second heat sink (52), wherein the second heat sink (52) is arranged on a surface of the second connecting plate segment (31) away from the drain (12).

9. A semiconductor packaging structure, characterized in that: include: A housing (60) having a receiving cavity (61); A power device unit, part of which is arranged in the accommodating cavity (61), and the power device unit is the power device unit according to any one of claims 1 to 8.

10. The semiconductor package structure according to claim 9, wherein: The housing (60) is provided with an inlet (62) and an outlet (63), and the heat dissipation medium can enter the accommodating cavity (61) through the inlet (62) and be discharged to the outside of the housing (60) through the outlet (63).

11. The semiconductor package structure according to claim 10, characterized in that: The housing (60) comprises a first cover plate (64), a second cover plate (65), and a surrounding plate (66) arranged between the first cover plate (64) and the second cover plate (65); the surrounding plate (66) comprises a first side plate (661) and a second side plate (662) arranged opposite to each other; the inlet (62) is arranged on the first side plate (661), the outlet (63) is arranged on the second side plate (662), and the first lead-out plate section (22) of the first terminal (20) and the second lead-out plate section (32) of the second terminal (30) of the power device unit are both passed through the first cover plate (64).

12. The semiconductor package structure according to claim 11, characterized in that: The first side plate (661) and the second side plate (662) extend along a preset direction (a); there are a plurality of power device units, and the plurality of power device units are arranged at intervals along the preset direction (a); the semiconductor chip (10) of the power device unit is arranged at an angle to the first side plate (661); in the preset direction (a), the first end of the first side plate (661) and the first end of the second side plate (662) are arranged correspondingly, and the second end of the first side plate (661) and the second end of the second side plate (662) are arranged correspondingly; the inlet (62) is located at the first end of the first side plate (661), and the outlet (63) is located at the second end of the second side plate (662).

13. The semiconductor package structure according to claim 12, wherein: The semiconductor packaging structure further comprises a plurality of flow channel plates (67) arranged at intervals along the preset direction (a); the plurality of flow channel plates (67) and the plurality of power device units are arranged alternately; in two adjacent flow channel plates (67), one end of one of the flow channel plates (67) is connected to the first side plate (661), and the other end is arranged at an interval with the second side plate (662); one end of the other flow channel plate (67) is connected to the second side plate (662), and the other end is arranged at an interval with the first side plate (661).

14. The semiconductor package structure according to claim 9, characterized in that: The semiconductor packaging structure further comprises a first sealing sleeve arranged between a first lead-out plate section (22) of the first terminal (20) and the housing (60), and a second sealing sleeve arranged between a second lead-out plate section (32) of the second terminal (30) and the housing (60).

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