Detection method and compensation method for photoetching splicing deviation

Abstract

The invention discloses a detection method and a compensation method for photoetching splicing deviation, and belongs to the technical field of photoetching, and the detection method comprises the following steps: manufacturing a zero layer of an overlay mark containing relative position zero deviation in a splicing seam area; the splicing layer is aligned with the zero layer, and the overlay deviation is measured through the overlay mark; the compensation method comprises the steps that overlay deviation is calculated through the overlay marks, and compensation is carried out. According to the invention, the photoetching splicing deviation can be reduced to a required range.

Description

Technical Field

[0001] The invention belongs to the technical field of photolithography, and in particular relates to a detection method and a compensation method for photolithography splicing deviation. Background Art

[0002] The current mainstream lithography machine manufacturer ASML has a maximum single exposure size of 26mm*33mm. With the development of semiconductor technology, processors, memory, image sensors, FPGAs, and silicon photonic chips are becoming more and more widely used. More and more optical chips will exceed the size of 26mm*33mm, so lithography splicing technology is needed in production.

[0003] Perfect splicing is when two photolithography patterns are completely aligned, which is an ideal state that cannot be achieved. The parameter that measures the alignment accuracy of two photolithography chips is the splicing deviation. There are many sources of deviation, including uneven movement of the wafer stage and the mask stage during photolithography; the alignment accuracy of the wafer and the mask; the heat deformation of the mask during operation; the stress generated by the wafer during processing; and the distortion of the projection light path of the photolithography machine.

[0004] Although there are many sources of deviation, the impact is generally small, about tens to hundreds of nanometers. When the product size is within 26mm*33mm, splicing is not required. Due to the cutting paths between chips, the redundancy of deviation is large and can be ignored. However, when splicing is required, the impact of splicing deviation caused by the above factors must be considered.

[0005] As the manufacturing process becomes more advanced, the requirements for splicing are also getting higher and higher. Take optical chips as an example. The carrier of information transmission in optical chips is light. When splicing lithography, it is necessary to align the optical waveguide as much as possible to reduce the loss of optical signals. The width of the waveguide is generally in the range of several hundred nanometers. The deviation of several tens to several hundred nanometers has a greater impact on the transmission loss. Summary of the invention

[0006] The purpose of the present invention is to provide a method for detecting and compensating lithography splicing deviation in order to overcome the defects of the prior art. The zero-layer lithography is added to produce the splicing seam position to form an alignment mark and a zero-deviation overlay mark, and then the subsequent waveguide layer production is carried out. Since the mask production accuracy is high, it can be considered that there is no deviation in the relative position between the zero-layer overlay marks. At this time, the overlay deviation of the waveguide layer to the zero layer can be used to characterize the splicing deviation. The overlay deviation is calculated by the overlay mark and compensated, so that the lithography splicing deviation can be reduced.

[0007] The object of the present invention is achieved through the following technical solutions:

[0008] A method for detecting photolithography splicing deviation, the method comprising:

[0009] Making a zero layer including an overlay mark with a relative position zero deviation in the joint seam area;

[0010] The zero layer is aligned with the splicing layer to measure the overlay deviation.

[0011] Furthermore, the step of making a zero layer of an overlay mark including a relative position zero deviation in the joint seam area specifically includes:

[0012] By photolithography across the stitching seam, a zero layer is added before the stitching layer, the range of the zero layer includes the stitching position of two photolithography areas, and the zero layer includes the overlay mark and alignment mark of the stitching seam position.

[0013] Furthermore, the overlay marks include at least two groups, which are respectively placed at two ends of the joint seam, and each group includes two marks, which are respectively placed on two sides of the joint seam.

[0014] Furthermore, the step of aligning the zero layer with the splicing layer and measuring the overlay deviation specifically includes:

[0015] Using the alignment mark to make a stitching layer lithography on the stitching layer;

[0016] The size of the stitching deviation is characterized by the size of the overlay deviation of the stitching layer lithography to the zero layer, and the overlay deviation is calculated through the overlay mark.

[0017] On the other hand, the present invention further provides a method for compensating for photolithography stitching deviation, wherein the method measures the photolithography stitching deviation by any of the aforementioned methods, and the compensation method comprises:

[0018] The overlay deviation is compensated to reduce the photolithography stitching deviation to within a preset deviation range threshold.

[0019] Furthermore, the method further comprises:

[0020] At least one group of overlay marks is added between the two groups of overlay marks on each splicing layer, and then deviation detection and compensation are performed.

[0021] The beneficial effects of the present invention are:

[0022] The present invention utilizes cross-joint seam lithography to produce an overlay mark with zero relative position deviation as a reference, and then uses the joint layer lithography to align the zero layer. The overlay deviation can be measured to characterize the joint deviation, and the joint deviation can be compensated by compensating the overlay deviation. The method is simple and easy. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of zero layer lithography and waveguide layer lithography according to an embodiment of the present invention;

[0024] Figure 2 is a schematic diagram of photolithography splicing according to an embodiment of the present invention;

[0025] Figure 3 It is a schematic diagram of the overlay marking style of an embodiment of the present invention.

[0026] Figure markings: 001-zero layer, 011-first zero layer overlay mark, 012-second zero layer overlay mark, 013-third zero layer overlay mark, 014-fourth zero layer overlay mark, 021-first alignment mark, 022-second alignment mark, 101-first waveguide, 102-second waveguide, 111-first overlay mark of first waveguide to zero layer, 112-first overlay mark of second waveguide to zero layer, 113-second overlay mark of first waveguide to zero layer, 114-second overlay mark of second waveguide to zero layer, 201-joining seam, 211-first alignment overlay mark, 212-second alignment overlay mark, 213-third alignment overlay mark, 214-fourth alignment overlay mark. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0028] Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without making any creative work shall fall within the scope of protection of the present invention.

[0029] The requirements for splicing deviation in electrical chip splicing exposure are relatively low. In most cases, only the wires need to be overlapped to form a path for the chip to work properly. Different from electrical chip splicing, the carrier of information transmission in optical chips is light. When splicing lithography, it is necessary to align the optical waveguide as much as possible to reduce the loss of optical signals. The waveguide width is generally in the range of several hundred nanometers, and the splicing deviation has a greater impact on the transmission loss.

[0030] In order to solve the above technical problems, the following embodiments of a method for detecting and compensating a photolithography splicing deviation of the present invention are proposed.

[0031] This embodiment provides a method for measuring and correcting photolithography splicing deviation. Taking splicing optical waveguides as an example, the method specifically includes the following steps:

[0032] Step 1: Add a zero layer before the waveguide layer. The zero layer range needs to include the splicing positions of the two lithography areas.

[0033] Specifically, the zero layer must contain overlay marks at the joint position. For each waveguide layer to be spliced, at least two sets of overlay marks are required, placed at the upper and lower ends of the joint, and each set contains two marks, placed on the left and right sides of the joint. Figure 1 ,like Figure 1 The diagram shows the zero layer lithography and waveguide layer lithography of this embodiment. In the figure, there are two groups of overlay marks on the zero layer 001, each group of overlay marks includes two zero layer overlay marks, the upper end of the zero layer 001 includes the first zero layer overlay mark 011 set on the left and the second zero layer overlay mark 012 set on the right, the lower end of the zero layer 001 includes the third zero layer overlay mark 013 set on the left and the fourth zero layer overlay mark 014 set on the right, and in addition, the left and right layers of the zero layer 001 are respectively engraved with the first alignment mark 021 and the second alignment mark 022. Since the accuracy of the mask is much greater than the lithography splicing accuracy, it can be determined that there is no deviation in the relative positions between the first zero layer overlay mark 011, the second zero layer overlay mark 012, the third zero layer overlay mark 013 and the fourth zero layer overlay mark 014.

[0034] It should be noted that if there is more than one waveguide layer, each waveguide layer must have two sets of engraved marks, with the same requirements as above.

[0035] Step 2: Use the zero-layer alignment mark to align and make the waveguide layer lithography. Figure 1 , Figure 1 The first waveguide 101 on the left side includes two waveguides to be spliced. The first waveguide 101 on the left side is photolithographically processed with a first alignment mark 021. The first waveguide 101 includes a first waveguide to zero layer first overlay mark 111 and a first waveguide to zero layer second overlay mark 113. The second waveguide 102 on the right side is photolithographically processed with a second alignment mark 022. The second waveguide 102 includes a second waveguide to zero layer first overlay mark 112 and a second waveguide to zero layer second overlay mark 114.

[0036] The overlay deviation between the waveguide layer and the zero layer is calculated by using the overlay mark of the zero layer and the overlay mark of the waveguide layer. The calculation method is a commonly used technical means in the art and will not be described in detail here. As mentioned above, there is no deviation in the relative positions between the first zero layer overlay mark 011, the second zero layer overlay mark 012, the third zero layer overlay mark 013 and the fourth zero layer overlay mark 014. Therefore, the overlay deviation between the first waveguide pair zero layer first overlay mark 111, the first waveguide pair zero layer second overlay mark 113, the second waveguide pair zero layer first overlay mark 112 and the second waveguide pair zero layer second overlay mark 114 relative to the first zero layer overlay mark 011, the second zero layer overlay mark 012, the third zero layer overlay mark 013 and the fourth zero layer overlay mark 014 can represent the splicing deviation.

[0037] It should be noted that the method for compensating the overlay deviation is a conventional technical means in the art, and the detailed steps will not be repeated here.

[0038] Step 3: Compensate for the overlay deviation until the stitching deviation is within an acceptable range. Figure 2 ,like Figure 2 Shown is a schematic diagram of photolithography splicing in this embodiment. Figure 2 In the embodiment, the first waveguide 101 and the second waveguide 102 are spliced ​​together by the zero layer to form a waveguide layer. The zero layer 001 includes a splicing seam 201. The first waveguide to zero layer first overlay mark 111, the first waveguide to zero layer second overlay mark 113, the second waveguide to zero layer first overlay mark 112 and the second waveguide to zero layer second overlay mark 114 correspond to the first zero layer overlay mark 011, the second zero layer overlay mark 012, the third zero layer overlay mark 013 and the fourth zero layer overlay mark 014 respectively, and together constitute a first alignment overlay mark 211, a second alignment overlay mark 212, a third alignment overlay mark 213 and a fourth alignment overlay mark 214.

[0039] It should be noted that after the specific deviation value has been determined, the method for compensating the overlay deviation is a conventional technical means in the art, and the detailed steps will not be repeated here.

[0040] Reference Figure 3 ,like Figure 3 The following is a schematic diagram of the overlay marking style. Figure 3 A style of alignment overlay marks is shown. In addition to the overlay mark style exemplified in this embodiment, other patterns may also be used as overlay marks.

[0041] After completing the splicing deviation compensation, subsequent processes such as etching are carried out to form a waveguide layer.

[0042] This embodiment uses cross-splicing seam lithography to produce an overlay mark with zero relative position deviation as a reference, and then uses waveguide layer lithography to align the zero layer. The overlay deviation can be measured to characterize the splicing deviation. The splicing deviation can be compensated by compensating the overlay deviation. The testing method is simple and easy.

[0043] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for detecting photolithography splicing deviation, characterized in that: The method comprises: Making a zero layer including an overlay mark with a relative position zero deviation in the joint seam area; The zero layer is aligned with the splicing layer to measure the overlay deviation.

2. The method for detecting photolithography splicing deviation according to claim 1, characterized in that: The step of making a zero layer of an overlay mark including a relative position zero deviation in the splicing seam area specifically includes: By photolithography across the stitching seam, a zero layer is added before the stitching layer, the range of the zero layer includes the stitching position of two photolithography areas, and the zero layer includes the overlay mark and alignment mark of the stitching seam position.

3. The method for detecting photolithography splicing deviation according to claim 2, characterized in that: The overlay marks include at least two groups, which are respectively placed at the two ends of the joint seam, and each group includes two marks, which are respectively placed on the two sides of the joint seam.

4. The method for detecting photolithography splicing deviation according to claim 2, characterized in that: The method of aligning the zero layer with the splicing layer and measuring the overlay deviation specifically includes: Using the alignment mark to make a stitching layer lithography on the stitching layer; The size of the stitching deviation is characterized by the size of the overlay deviation of the stitching layer lithography to the zero layer, and the overlay deviation is calculated through the overlay mark.

5. A method for compensating photolithography splicing deviation, characterized in that: The method measures the photolithography stitching deviation by the method described in any one of claims 1 to 4, and the compensation method comprises: The overlay deviation is compensated to reduce the photolithography stitching deviation to within a preset deviation range threshold.

6. The method for compensating photolithography stitching deviation according to claim 5, characterized in that: The method further comprises: At least one group of overlay marks is added between the two groups of overlay marks on each splicing layer, and then deviation detection and compensation are performed.

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