Output driving circuit, interface chip and electronic equipment

Abstract

The invention discloses an output driving circuit, an interface chip and electronic equipment. The in-phase input end of an error amplifier in the output driving circuit is the input end of the output driving circuit, and the output end of the error amplifier is connected with the grid electrode of a first switching tube and the grid electrode of a second switching tube; the source electrode of the first switch tube is connected with the drain electrode of the third switch tube and the inverted input end of the error amplifier. The drain electrode of the first switch tube and the drain electrode of the second switch tube are connected with a first external voltage; the grid electrode of the third switch tube and the grid electrode of the fourth switch tube are connected with a second external voltage. The source electrode of the third switch tube and the source electrode of the fourth switch tube are both grounded; the source electrode of the second switch tube is connected with the drain electrode of the fourth switch tube. The invention provides an output driving circuit which is not influenced by capacitive load and / or load current change, can accurately track the change of input voltage, outputs stable voltage, and meets the requirements of large-range change of the input voltage, large load capacity and small output ripple.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an output drive circuit, an interface chip and an electronic device. Background Art

[0002] The LDO (Low Dropout Regulaor) circuit is used to generate and maintain an accurate and stable output voltage that does not change with the input voltage, load environment, and operating conditions. The traditional LDO circuit has a buffered reference inside, and uses an error amplifier to adjust the series device between the input and output so that the output voltage is a certain set value of the input voltage. The traditional LDO circuit is divided into two types: PMOS and NMOS according to the structure of the series device. Figure 1 A conventional PMOS type LDO circuit is shown. Figure 2 The figure shows a traditional NMOS type LDO circuit. VREF, error amplifier EA1 and switch tube M0 form a closed-loop control loop. The closed-loop control loop responds to the offset and offsets the influence of changes in load current, input voltage, temperature and process on the output to ensure that the feedback signal VFB can accurately track VREF. Among them, VREF is the input voltage of the LDO circuit, which can be generated by a reference voltage generator; the error amplifier EA1 is used to compare the input of the in-phase input terminal with the input of the inverting input terminal, and then amplify the comparison result to generate an error correction signal. However, since the output pole in the traditional LDO circuit is related to the load current, the output pole changes dramatically when the load current is extremely large or extremely small, so it cannot be guaranteed that the closed-loop control loop will still work stably when the load current of the LDO circuit changes dramatically and / or the capacitive load is large. Summary of the invention

[0003] The technical problem to be solved by the present invention is to overcome the defect that the closed-loop control circuit in the traditional LDO circuit in the prior art cannot work stably when the load current changes drastically and / or the capacitive load is large, and to provide an output drive circuit, an interface chip and an electronic device.

[0004] The present invention solves the above technical problems through the following technical solutions:

[0005] The present invention provides an output drive circuit, the output drive circuit comprising an error amplifier, a first switch tube, a second switch tube, a third switch tube and a fourth switch tube;

[0006] The non-inverting input terminal of the error amplifier is the input terminal of the output drive circuit;

[0007] The output end of the error amplifier is electrically connected to the gate of the first switch tube and the gate of the second switch tube respectively;

[0008] The source of the first switch tube is electrically connected to the drain of the third switch tube and the inverting input terminal of the error amplifier respectively;

[0009] The drain of the first switch tube and the drain of the second switch tube are both electrically connected to a first external voltage;

[0010] The gate of the third switch tube and the gate of the fourth switch tube are both electrically connected to a second external voltage;

[0011] The source of the third switch tube and the source of the fourth switch tube are both grounded;

[0012] The source of the second switch tube is electrically connected to the drain of the fourth switch tube, and serves as the output end of the output drive circuit.

[0013] Preferably, the first switch tube, the second switch tube, the third switch tube and the fourth switch tube are all NMOS tubes.

[0014] Preferably, the ratio of the channel width-to-length ratio of the first switch tube to the channel width-to-length ratio of the second switch tube is the same as the ratio of the channel width-to-length ratio of the third switch tube to the channel width-to-length ratio of the fourth switch tube.

[0015] Preferably, the non-inverting input terminal of the error amplifier is electrically connected to the output terminal of an external reference circuit, and the external reference circuit is used to output a reference voltage to the non-inverting input terminal of the error amplifier.

[0016] Preferably, the gate of the third switch tube and the gate of the fourth switch tube are both connected to the output end of a bias circuit, and the bias circuit is used to output the second external voltage.

[0017] Preferably, the error amplifier is an operational transconductance amplifier.

[0018] Preferably, the operational transconductance amplifier includes a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube, a ninth switch tube, a tenth switch tube, an eleventh switch tube, a twelfth switch tube and a thirteenth switch tube;

[0019] The source of the fifth switch tube and the source of the sixth switch tube are both electrically connected to the drain of the thirteenth switch tube;

[0020] The drain of the fifth switch tube is electrically connected to the drain of the seventh switch tube;

[0021] The gate of the seventh switch tube is electrically connected to the drain of the seventh switch tube and the gate of the ninth switch tube respectively;

[0022] The drain of the sixth switch tube is electrically connected to the drain of the eighth switch tube;

[0023] The gate of the eighth switch tube is electrically connected to the drain of the eighth switch tube and the gate of the tenth switch tube respectively;

[0024] The drain of the ninth switch tube is electrically connected to the drain of the eleventh switch tube;

[0025] The gate of the eleventh switch tube is electrically connected to the drain of the eleventh switch tube and the gate of the twelfth switch tube respectively;

[0026] The drain of the tenth switch tube is electrically connected to the drain of the twelfth switch tube;

[0027] Sources of the seventh switch tube, the eighth switch tube, the ninth switch tube and the tenth switch tube are all grounded;

[0028] Sources of the seventh switch tube, the eighth switch tube and the thirteenth switch tube are all electrically connected to a third external voltage;

[0029] The gate of the thirteenth switch tube is electrically connected to a fourth external voltage;

[0030] The gate of the fifth switch tube is the inverting input terminal of the operational transconductance amplifier;

[0031] The gate of the sixth switch tube is the non-inverting input terminal of the operational transconductance amplifier;

[0032] The gates of the tenth switch tube and the twelfth switch tube are output ends of the operational transconductance amplifier.

[0033] Preferably, the fifth switch tube, the sixth switch tube, the eleventh switch tube, the twelfth switch tube, and the thirteenth switch tube are all PMOS tubes, and the seventh switch tube, the eighth switch tube, the ninth switch tube, and the tenth switch tube are all NMOS tubes.

[0034] The present invention also provides an interface chip, which includes the above-mentioned output drive circuit.

[0035] The present invention also provides an electronic device, which includes the above-mentioned interface chip.

[0036] The positive progressive effect of the present invention is that the present invention provides an output drive circuit, which is not affected by capacitive load and / or load current changes, can accurately track changes in input voltage, output a stable voltage, and meet the requirements of a wide range of input voltage changes, large load capacity and small output ripple. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1Schematic diagram of a traditional PMOS type LDO circuit.

[0038] Figure 2 Schematic diagram of a traditional NMOS type LDO circuit.

[0039] Figure 3 This is a schematic diagram of an output drive circuit provided in Embodiment 1 of the present invention.

[0040] Figure 4 Schematic diagram of an operational transconductance amplifier provided in Embodiment 1 of the present invention. DETAILED DESCRIPTION

[0041] The present invention is further described below by way of examples, but the present invention is not limited to the scope of the examples.

[0042] Example 1

[0043] This embodiment provides an output drive circuit such as Figure 3 As shown, the output drive circuit includes an error amplifier OP1, a first switch tube M1, a second switch tube M2, a third switch tube M3 and a fourth switch tube M4. The non-inverting input terminal of the error amplifier OP1 is the input terminal of the output drive circuit; the output terminal of the error amplifier OP1 is electrically connected to the gate of the first switch tube M1 and the gate of the second switch tube M2 respectively; the source of the first switch tube M1 is electrically connected to the drain of the third switch tube M3 and the inverting input terminal of the error amplifier OP1 respectively; the drain of the first switch tube M1 and the drain of the second switch tube M2 are both electrically connected to the first external part; the gate of the third switch tube M3 and the gate of the fourth switch tube M4 are both electrically connected to the second external part; the source of the third switch tube M3 and the source of the fourth switch tube M4 are both grounded; the source of the second switch tube M2 is electrically connected to the drain of the fourth switch tube M4, which is the output terminal of the output drive circuit.

[0044] Specifically, the gate of the third switch tube M3 and the gate of the fourth switch tube M4 are both electrically connected to the second external voltage VB, and there are two mirror structures in the output drive circuit, the first mirror structure is the first switch tube M1 and the second switch tube M2, and the second mirror structure is the third switch tube M3 and the fourth switch tube M4. The input voltage Vref, the error amplifier OP1 and the first switch tube M1 form a closed-loop control loop to ensure that the feedback voltage Vfb can accurately track the input voltage Vref. The voltage at the gate of the first switch tube M1 and the second switch tube M2 is Vgate. If the channel width-to-length ratio of the first switch tube M1 and the second switch tube M2 adopts a ratio of 1:M, according to the characteristics of the MOS tube, ignoring the channel length modulation effect, when the first switch tube M1 and the second switch tube M2 are both in the saturation region, the actual current ratio flowing through the drain of the first switch tube M1 and the second switch tube M2 is also 1:M, so the output voltage Vout at the source of the second switch tube M2 can well track the change of the feedback voltage Vfb at the first switch tube M1. In summary, the feedback voltage Vfb tracks the change of the input voltage Vref, and the output voltage Vout tracks the change of the feedback voltage Vfb, so the output voltage Vout of the output drive circuit accurately tracks the input voltage Vref, and the output voltage Vout is equal to the input voltage Vref. It is precisely because of the use of this open-loop replica feedback structure (Replica Feedback) that the output voltage Vout of the output drive circuit can better adapt to various capacitive loads and load currents, thereby ensuring stability in practical applications.

[0045] This embodiment provides an output drive circuit that is not affected by capacitive loads and / or load current changes, can accurately track changes in input voltage, and output a stable voltage, meeting the requirements of a wide range of input voltage changes, large load capacity, and small output ripple.

[0046] In an optional implementation, the first switch tube, the second switch tube, the third switch tube and the fourth switch tube are all NMOS tubes.

[0047] In an optional implementation, the ratio of the channel width-to-length ratio of the first switch tube to the channel width-to-length ratio of the second switch tube is the same as the ratio of the channel width-to-length ratio of the third switch tube to the channel width-to-length ratio of the fourth switch tube.

[0048] Specifically, if the channel width-to-length ratio of the first switch tube and the second switch tube adopts a ratio of 1:M, in order to ensure that the output voltage Vout can accurately track the feedback voltage Vfb, the channel width-to-length ratio of the third switch tube and the fourth switch tube also adopts a ratio of 1:M. M is an arbitrary positive number, and the value of M can be determined according to actual conditions, and this embodiment does not limit this.

[0049] In an optional implementation, the non-inverting input terminal of the error amplifier is electrically connected to the output terminal of an external reference circuit, and the external reference circuit is used to output a reference voltage to the non-inverting input terminal of the error amplifier.

[0050] Specifically, the reference voltage generated by the reference circuit is used as the input voltage Vref of the output drive circuit in order to keep the input voltage Vref stable.

[0051] In an optional implementation, the gate of the third switch tube and the gate of the fourth switch tube are both connected to the output end of the bias circuit, and the bias circuit is used to output the second external

[0052] In an optional implementation, the error amplifier is a transconductance amplifier.

[0053] Specifically, an operational transconductance amplifier (OTA) is an amplifier that converts an input differential voltage into an output current, and thus is a voltage-controlled current source. In practical applications, the type of the error amplifier OP1 can be determined according to actual conditions, and this embodiment does not limit this. In addition to the transconductance amplifier, it can also be a voltage amplifier that absorbs voltage and generates a voltage at the output end, a current amplifier that receives a current input and generates a current output, or a transimpedance amplifier that converts a current input into a voltage output.

[0054] In an optional embodiment, if Figure 4As shown, the transconductance amplifier OP1 includes a fifth switch tube M5, a sixth switch tube M6, a seventh switch tube M7, an eighth switch tube M8, a ninth switch tube M9, a tenth switch tube M10, an eleventh switch tube M11, a twelfth switch tube M12 and a thirteenth switch tube M13. The source of the fifth switch tube M5 and the source of the sixth switch tube M6 are both electrically connected to the drain of the thirteenth switch tube M13. The drain of the fifth switch tube M5 is electrically connected to the drain of the seventh switch tube M7. The gate of the seventh switch tube M7 is electrically connected to the drain of the seventh switch tube M7 and the gate of the ninth switch tube M9, respectively. The drain of the sixth switch tube M6 is electrically connected to the drain of the eighth switch tube M8. The gate of the eighth switch tube M8 is electrically connected to the drain of the eighth switch tube M8 and the gate of the tenth switch tube M10, respectively. The drain of the ninth switch tube M9 is electrically connected to the drain of the eleventh switch tube M11. The gate of the eleventh switch tube M11 is electrically connected to the drain of the eleventh switch tube M11 and the gate of the twelfth switch tube M12, respectively. The drain of the tenth switch tube M10 is electrically connected to the drain of the twelfth switch tube M12. The sources of the seventh switch tube M7, the eighth switch tube M8, the ninth switch tube M9 and the tenth switch tube M10 are all grounded. The sources of the seventh switch tube M7, the eighth switch tube M8 and the thirteenth switch tube M13 are all electrically connected to the third external voltage. The gate of the thirteenth switch tube M13 is electrically connected to the fourth external voltage. The gate of the fifth switch tube M5 is the reverse input terminal of the transconductance amplifier. The gate of the sixth switch tube M6 is the non-inverting input terminal of the transconductance amplifier. The gates of the tenth switch tube M10 and the twelfth switch tube M12 are the output terminals of the transconductance amplifier.

[0055] Specifically, the gate of the thirteenth switch tube M13 is electrically connected to the fourth external voltage Vb, the gate of the fifth switch tube M5 takes the feedback voltage Vfb as input, the gate of the sixth switch tube M6 takes the input voltage Vref as input, the gates of the tenth switch tube M10 and the twelfth switch tube M12 take Vgate as output, the fifth switch tube M5 and the sixth switch tube M6 constitute the input stage of the transconductance amplifier OP1, the seventh switch tube M7 and the ninth switch tube M9 constitute the first mirror current load structure of the transconductance amplifier OP1, the eighth switch tube M8 and the tenth switch tube M10 constitute the second mirror current load structure of the transconductance amplifier OP1, the eleventh switch tube M11 and the twelfth switch tube M12 constitute the third mirror current load structure of the transconductance amplifier OP1, and the tenth switch tube M10 and the twelfth switch tube M12 constitute the output stage structure of the transconductance amplifier OP1. In practical applications, the structure of the transconductance amplifier OP1 can be determined according to actual conditions, and this embodiment does not limit this.

[0056] In an optional implementation, the fifth switch tube M5, the sixth switch tube M6, the eleventh switch tube M11, the twelfth switch tube M12, and the thirteenth switch tube M13 are all PMOS tubes, and the seventh switch tube M7, the eighth switch tube M8, the ninth switch tube M9, and the tenth switch tube M10 are all NMOS tubes.

[0057] Example 2

[0058] This embodiment provides an interface chip, which includes the output drive circuit as described in Embodiment 1.

[0059] Specifically, the input end of the interface chip can be electrically connected to the bus master, and the output end of the interface chip can be electrically connected to the bus slave. The type of bus can be determined according to actual conditions, and this embodiment does not limit this. Common bus types include IIC (Inter-Integrated Circuit) and SMBus (System Management Bus).

[0060] This embodiment provides an interface chip, in which the output drive circuit is not affected by capacitive load and / or load current changes, can accurately track changes in input voltage, and output a stable voltage, meeting the requirements of a wide range of input voltage changes, large load capacity, and small output ripple.

[0061] Example 3

[0062] This embodiment provides an electronic device, which includes the interface chip in Embodiment 2.

[0063] This embodiment provides an electronic device, in which the output drive circuit in the interface chip is not affected by the capacitive load and / or load current changes, can accurately track the changes in the input voltage, and output a stable voltage, meeting the requirements of a large range of input voltage changes, large load capacity and small output ripple.

[0064] Although the specific embodiments of the present invention are described above, it should be understood by those skilled in the art that this is only for illustration and the protection scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but these changes and modifications all fall within the protection scope of the present invention.

Claims

1. An output drive circuit, characterized in that: The output drive circuit includes an error amplifier, a first switch tube, a second switch tube, a third switch tube and a fourth switch tube; The non-inverting input terminal of the error amplifier is the input terminal of the output drive circuit; The output end of the error amplifier is electrically connected to the gate of the first switch tube and the gate of the second switch tube respectively; The source of the first switch tube is electrically connected to the drain of the third switch tube and the inverting input terminal of the error amplifier respectively; The drain of the first switch tube and the drain of the second switch tube are both electrically connected to a first external voltage; The gate of the third switch tube and the gate of the fourth switch tube are both electrically connected to a second external voltage; The source of the third switch tube and the source of the fourth switch tube are both grounded; The source of the second switch tube is electrically connected to the drain of the fourth switch tube, and serves as the output end of the output drive circuit.

2. The output drive circuit according to claim 1, characterized in that: The first switch tube, the second switch tube, the third switch tube and the fourth switch tube are all NMOS tubes.

3. The output drive circuit according to claim 1, characterized in that: The ratio of the channel width-to-length ratio of the first switch tube to the channel width-to-length ratio of the second switch tube is the same as the ratio of the channel width-to-length ratio of the third switch tube to the channel width-to-length ratio of the fourth switch tube.

4. The output drive circuit according to claim 1, characterized in that: The non-inverting input terminal of the error amplifier is electrically connected to the output terminal of an external reference circuit, and the external reference circuit is used to output a reference voltage to the non-inverting input terminal of the error amplifier.

5. The output drive circuit according to claim 1, wherein: The gate of the third switch tube and the gate of the fourth switch tube are both connected to the output end of the bias circuit, and the bias circuit is used to output the second external voltage.

6. The output drive circuit according to claim 1, characterized in that: The error amplifier is an operational transconductance amplifier.

7. The output drive circuit according to claim 6, characterized in that: The operational transconductance amplifier includes a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube, a ninth switch tube, a tenth switch tube, an eleventh switch tube, a twelfth switch tube and a thirteenth switch tube; The source of the fifth switch tube and the source of the sixth switch tube are both electrically connected to the drain of the thirteenth switch tube; The drain of the fifth switch tube is electrically connected to the drain of the seventh switch tube; The gate of the seventh switch tube is electrically connected to the drain of the seventh switch tube and the gate of the ninth switch tube respectively; The drain of the sixth switch tube is electrically connected to the drain of the eighth switch tube; The gate of the eighth switch tube is electrically connected to the drain of the eighth switch tube and the gate of the tenth switch tube respectively; The drain of the ninth switch tube is electrically connected to the drain of the eleventh switch tube; The gate of the eleventh switch tube is electrically connected to the drain of the eleventh switch tube and the gate of the twelfth switch tube respectively; The drain of the tenth switch tube is electrically connected to the drain of the twelfth switch tube; Sources of the seventh switch tube, the eighth switch tube, the ninth switch tube and the tenth switch tube are all grounded; Sources of the seventh switch tube, the eighth switch tube and the thirteenth switch tube are all electrically connected to a third external voltage; The gate of the thirteenth switch tube is electrically connected to a fourth external voltage; The gate of the fifth switch tube is the inverting input terminal of the operational transconductance amplifier; The gate of the sixth switch tube is the non-inverting input terminal of the operational transconductance amplifier; The gates of the tenth switch tube and the twelfth switch tube are output ends of the operational transconductance amplifier.

8. The output drive circuit according to claim 7, characterized in that: The fifth switch tube, the sixth switch tube, the eleventh switch tube, the twelfth switch tube, and the thirteenth switch tube are all PMOS tubes, and the seventh switch tube, the eighth switch tube, the ninth switch tube, and the tenth switch tube are all NMOS tubes.

9. An interface chip, characterized in that: The interface chip comprises the output driving circuit according to any one of claims 1-8.

10. An electronic device, characterized in that: The electronic device comprises the interface chip as claimed in claim 9.

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