Dual-core DSP chip online upgrading method, electronic equipment and product

Abstract

The invention belongs to the technical field of DSP chip online upgrading, and aims to provide a dual-core DSP chip online upgrading method, electronic equipment and a product. In the implementation process, after receiving the upgrading instruction, the first CPU executes the software forced restarting operation in the APP program, and enters the Bootloader area of the first CPU through a timing mechanism, so that the Bootloader program is executed, and the subsequent online upgrading process is completed. On the basis, stable operation of the dual-core DSP chip during program switching can be ensured, instability caused by program jumping is avoided, unsaved data or uncompleted operation possibly caused by direct jumping is prevented, meanwhile, the dual-core DSP chip is allowed to detect and trigger firmware upgrading during operation, physical restarting of equipment is not needed, and the reliability of the dual-core DSP chip is improved. The downtime of the system is reduced, and the maintenance efficiency of the system is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of DSP chip online upgrade, and in particular relates to a dual-core DSP chip online upgrade method, electronic equipment and product. Background Art

[0002] As the core device in the energy storage system, PCS (Power Conversion System) is an important bridge between the power grid and the energy storage medium. It has the functions of smoothing power fluctuations in the power grid, shaving peaks and filling valleys, and improving the quality of grid-connected waveforms. DSP (Digital Signal Processor) chips are used to control power electronic devices in PCS to achieve efficient energy conversion and management, ensuring efficient and stable operation of the energy storage system. Since the energy storage system has complex functions and requires unified management, in order to improve the management efficiency of the energy storage system, it is usually necessary to upgrade the DSP chip code online. This method can be achieved by directly burning the program on the host computer interface through the communication board, which is conducive to the unified management of the host computer and avoids the problem of low management efficiency caused by manual on-site burning operations.

[0003] For the 28379D dual-core DSP chip, it has two CPUs (Central Processing Units), and the two CPUs have independent FLASH (flash memory) areas. The dual-core DSP chip also runs a secondary Bootloader (a bootloader that transmits data through a communication board) program to facilitate receiving, transmitting and upgrading firmware. In the prior art, when it is necessary to upgrade the code of the dual-core DSP chip online, the firmware is usually received through the secondary Bootloader program, and according to the FLASH sectors pre-divided in the CMD file (a configuration file used to describe the management, allocation and use of the physical memory in the digital signal processing chip, and the user can manage and allocate the memory and address space in the system by writing the CMD file), according to the principle of upgrading one CPU first and then upgrading the other CPU, the firmware is first written into the FLASH area of ​​one CPU specified by the CMD file, and then written into the FLASH area of ​​another CPU specified by the CMD file, thereby completing the upgrade of the two CPUs on the dual-core DSP chip.

[0004] However, in the process of using the prior art, the inventors found that the prior art has at least the following problems: In the prior art, when the dual-core DSP chip jumps from the APP program to the Bootloader program, that is, when entering the upgrade process during the execution of the APP program, it usually jumps to the Bootloader area directly through the address of the Bootloader area preset in the CMD file. However, the APP program is relatively complex, and the forced address jump is likely to cause system initialization problems, which poses a serious hidden danger and is not conducive to the stable operation of the dual-core DSP chip. Summary of the invention

[0005] The present invention aims to solve the above technical problems at least to a certain extent. The present invention provides a dual-core DSP chip online upgrade method, electronic equipment and product.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions: In a first aspect, the present invention provides a dual-core DSP chip online upgrade method, comprising: Divide the two CPUs in the designated dual-core DSP chip into a first CPU and a second CPU, and use the first CPU as a main control core; Based on a preset CMD file, the FLASH area of ​​the dual-core DSP chip is divided into a first FLASH area corresponding to the first CPU and a second FLASH area corresponding to the second CPU, and the Bootloader area in the first FLASH area is used as the default startup address after the dual-core DSP chip is powered on; wherein the first FLASH area and the second FLASH area both include a Bootloader area for storing a Bootloader program and an APP area for storing an APP program; After the dual-core DSP chip is powered on, the dual-core DSP chip is initialized; The dual-core DSP chip enters the Bootloader area corresponding to the first CPU according to the configuration of the CMD file, so that the first CPU executes the Bootloader program stored in its Bootloader area; The first CPU performs a delay detection and determines whether an upgrade instruction is received within a specified time period. If yes, the first CPU cooperates with the second CPU to perform an online upgrade. If no, proceed to the next step. The first CPU and the second CPU jump to their respective APP areas respectively, so that the first CPU and the second CPU respectively execute the APP programs stored in their respective APP areas; The first CPU determines whether an upgrade instruction is received. If so, the first CPU executes a software forced restart action so that the first CPU enters its Bootloader area and cooperates with the second CPU to perform online upgrade.

[0007] In a possible design, the dual-core DSP chip is initialized, including: Checking a status of the second CPU, and starting the second CPU when the second CPU works normally; Initialize the clock module, GPIO interface and CAN communication interface in the dual-core DSP chip; Setting an ISR for the CAN communication interface; Configuring corresponding message objects in the dual-core DSP chip so that the CAN communication interface can correctly send and receive messages; And, the FLASH area in the dual-core DSP chip is initialized, and the permission for the first CPU to read and write FLASH is set.

[0008] In one possible design, the first CPU and / or the second CPU sends and receives data via a CAN communication interface, and the first CPU and the second CPU perform synchronous operations via an IPC mechanism.

[0009] In a possible design, the dual-core DSP chip is upgraded online in a state machine polling manner.

[0010] In a possible design, the first CPU cooperates with the second CPU to perform online upgrade, including: The first CPU determines whether a FLASH operation instruction is received. If yes, the first CPU parses the FLASH operation instruction, executes an action matching the FLASH operation instruction, and proceeds to the next step. If no, the first CPU directly proceeds to the next step. The first CPU performs a time counting detection to obtain a time counting value between the time when the first CPU receives the upgrade instruction and the current time; When the time count value is greater than a pre-designed value, there is executable code in the APP area of ​​the first CPU, and there is an upgrade flag in the Bootloader area of ​​the first CPU, the state of the dual-core DSP chip is a JUMP state, and the first CPU communicates with the second CPU in a coordinated manner so that the first CPU and the second CPU jump to their respective APP areas respectively, so that the first CPU and the second CPU respectively execute APP programs stored in their respective APP areas.

[0011] In a possible design, the FLASH operation instructions include erase instructions and program instructions; correspondingly, the message parsing function sCANProcess() is used to parse the FLASH operation instructions.

[0012] In a possible design, after the first CPU cooperates with the second CPU to complete the upgrade, the method further includes: The first CPU and the second CPU jump to their respective APP areas respectively, so that the first CPU and the second CPU respectively execute APP programs in their respective APP areas.

[0013] In a second aspect, the present invention provides an electronic device, comprising: a memory for storing computer program instructions; and, The processor is used to execute the computer program instructions to complete the operation of the dual-core DSP chip online upgrade method as described in any one of the above.

[0014] In a third aspect, the present invention provides a computer-readable storage product having instructions stored thereon. When the instructions are run on a computer, the online upgrade method for a dual-core DSP chip as described in any one of the above is executed.

[0015] In a fourth aspect, the present invention provides a computer program product, including a computer program or instructions, wherein the computer program or instructions, when executed by a computer, implements the online upgrade method for a dual-core DSP chip as described in any one of the above.

[0016] The beneficial effects of the present invention are: The present invention discloses a dual-core DSP chip online upgrade method, electronic device and product, which can improve the stability of the dual-core DSP chip online upgrade. It should be noted that in the present invention, the design of delay detection avoids accidentally staying in the Bootloader mode when there is no upgrade demand, thereby improving the stability and reliability of the system. At the same time, the present invention replaces the traditional address jump method by introducing a software forced restart method. Specifically, during the implementation of the present invention, after receiving the upgrade instruction, the first CPU will execute the software forced restart action in the APP program, and enter its Bootloader area through a timing mechanism to execute the Bootloader program and complete the subsequent online upgrade process. Based on this, the present invention can ensure the stable operation of the dual-core DSP chip when switching programs, avoid the instability caused by program jumps, and prevent unsaved data or uncompleted operations that may be caused by direct jumps. At the same time, the dual-core DSP chip is allowed to detect and trigger firmware upgrades during operation without physically restarting the device, reducing system downtime and improving system maintenance efficiency.

[0017] Other beneficial effects of the present invention will be further described in the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a flow chart of a dual-core DSP chip online upgrade method in an embodiment; Figure 2 It is a module block diagram of an electronic device in an embodiment. DETAILED DESCRIPTION

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below in combination with the drawings and the description of the embodiments or the prior art. Obviously, the following description of the structure of the drawings is only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention.

[0020] Embodiment 1: This embodiment discloses a dual-core DSP chip online upgrade method, which can be executed by, but is not limited to, a computer device or a virtual machine with certain computing resources, such as a personal computer, a smart phone, a personal digital assistant, or a wearable device, or by a virtual machine.

[0021] like Figure 1 As shown, a dual-core DSP chip online upgrade method may include but is not limited to the following steps: S1. The two CPUs in the designated dual-core DSP chip are divided into a first CPU and a second CPU, and the first CPU is used as the main control core; S2. Based on the preset CMD file, the FLASH area of ​​the dual-core DSP chip is divided into a first FLASH area corresponding to the first CPU and a second FLASH area corresponding to the second CPU, and the Bootloader area in the first FLASH area is used as the default startup address of the dual-core DSP chip after power-on; wherein, both the first FLASH area and the second FLASH area include a Bootloader area for storing the Bootloader program and an APP area for storing the APP (Application) program; it should be noted that step S2 is used to implement the memory allocation setting in the CMD file, and the CMD file can store setting information such as the FLASH area division rules of the first CPU and the second CPU to ensure that each area can be correctly loaded and executed during the firmware upgrade; specifically, the FLASH area division rules specify the location and size of the storage areas including the first FLASH area and the second FLASH area, and each FLASH area is further divided into a Bootloader area for storing the Bootloader program and an APP area for storing the APP program, wherein the Bootloader program is responsible for the upgrade boot process at startup, and is used to receive and update the firmware, and the APP program is used to be executed by the corresponding CPU after the upgrade is completed. In addition, in this embodiment, since the first CPU is the main control core, by using the Bootloader area in the first FLASH area as the default startup address after the dual-core DSP chip is powered on, the first CPU can be started first after the dual-core DSP chip is powered on, and the Bootloader area of ​​the first CPU can be entered, so that the first CPU can run the Bootloader program stored therein.

[0022] S3. After the dual-core DSP chip is powered on, the dual-core DSP chip is initialized; it should be noted that after the dual-core DSP chip is powered on, the dual-core DSP chip will automatically enter various hardware and software initialization processes. In this stage, the first CPU and the second CPU respectively perform self-initialization to ensure that the dual-core DSP chip can operate normally and prepare for subsequent firmware upgrade operations.

[0023] Specifically, in step S3, the dual-core DSP chip is initialized, including but not limited to: Checking the state of the second CPU, and when the second CPU is working normally, starting the second CPU to start executing a corresponding program; Initialize and set the clock module, GPIO (General Purpose Input / Output) interface and CAN (Controller Area Network) communication interface in the dual-core DSP chip to ensure that these modules can work normally during the operation of the dual-core DSP chip; An ISR (Interrupt Service Routine) is set for the CAN communication interface, so that when an interrupt occurs in the CAN communication interface, a timely response can be processed to prevent the dual-core DSP chip from falling into an infinite loop when an unexpected situation occurs; Configuring corresponding message objects in the dual-core DSP chip so that the CAN communication interface can correctly send and receive messages; And, the FLASH area in the dual-core DSP chip is initialized, and the permission for the first CPU to read and write FLASH is set.

[0024] In addition, in this embodiment, when the above initialization work is completed, the communication board and other peripherals can inform the first CPU and the second CPU that the initialization work is completed through the IPC (Inter-Process Communication) mechanism so that they can start normal operation.

[0025] S4. The dual-core DSP chip enters the Bootloader area corresponding to the first CPU according to the configuration of the CMD file, so that the first CPU executes the Bootloader program stored in its Bootloader area; at this time, the dual-core DSP chip will run the Bootloader program stored in the Bootloader area corresponding to the first CPU.

[0026] S5. The first CPU performs a delay detection and determines whether an upgrade instruction is received within a specified time period. If so, it indicates that the system needs to enter a firmware upgrade mode, and the first CPU cooperates with the second CPU to perform an online upgrade. If not, proceed to the next step. Specifically, in this embodiment, the specified time period is set to 3 seconds, that is, if the first CPU receives an upgrade instruction within 3 seconds, the first CPU cooperates with the second CPU to perform an online upgrade, otherwise the first CPU and the second CPU jump to their respective APP areas to execute the corresponding APP programs.

[0027] S6. The first CPU and the second CPU jump to their respective APP areas respectively, so that the first CPU and the second CPU respectively execute the APP programs stored in their respective APP areas; this step also means that the first CPU and the second CPU automatically jump to their respective APP areas after the delay ends, and the two CPUs continue to execute their respective APP programs.

[0028] S7. The first CPU determines whether an upgrade instruction is received. If so, it means that the system needs to enter the firmware upgrade mode. At this time, the first CPU executes a software forced restart action, for example, through a watchdog timer, so that the first CPU enters its Bootloader area and cooperates with the second CPU to perform online upgrade.

[0029] In steps S5 and S7, the first CPU cooperates with the second CPU to perform online upgrade, including: A1. The first CPU determines whether a FLASH operation instruction is received. If so, the FLASH operation instruction is parsed and an action matching the FLASH operation instruction is executed, and the next step is entered. If not, the next step is entered directly. Specifically, in step A1 of this embodiment, the FLASH operation instruction includes an erase instruction and a program instruction; correspondingly, in this embodiment, the message parsing function sCANProcess() is used to parse the FLASH operation instruction.

[0030] In this embodiment, the Bootloader program has only one entry and one exit to ensure the orderly operation of the Bootloader program. Specifically, the upgrade instruction code is 0xa1, so that the CPU can implement the handshake function of the Bootloader area entry and exit, and the upgrade completion instruction is 0xa5, so that the CPU can implement the Bootloader area exit function, which corresponds to writing or erasing the address data in the FLASH flag sector.

[0031] The erase instruction code is 0xa2. After the CPU receives the erase instruction, it will erase all the FLASH sectors corresponding to its APP program.

[0032] The programming instruction code is 0xa3 / 0xa4; 0xa3 is the information frame. In order to improve the programming efficiency, a packet of data is programmed as 64 frames, so the packet number and the CRC check code of the packet data are required; 0xa4 is the data frame. For programming failure and CRC (Cyclic Redundancy Check) check failure, the corresponding error identification code and the packet number of the packet will be replied to the communication board, indicating that the packet data needs to be retransmitted.

[0033] A2. The first CPU performs a time count detection to obtain a time count value between the time when the first CPU receives the upgrade instruction and the current time; A3. When the time count value is greater than the pre-designed value (such as set to 5000s), there is executable code in the APP area of ​​the first CPU, and there is an upgrade flag in the Bootloader area of ​​the first CPU, the state of the dual-core DSP chip is the JUMP state, and the first CPU and the second CPU communicate collaboratively so that the first CPU and the second CPU jump to their respective APP areas respectively, so that the first CPU and the second CPU respectively execute the APP programs stored in their respective APP areas. Otherwise, that is, when any one of the above three conditions is not met, return to step A1 and continue the online upgrade process. Among them, the upgrade flag is received and stored by the first CPU based on peripherals such as the communication board. The upgrade flag is used to prevent power failures and other situations during the upgrade process. This flag can be read when the power is turned on again to determine whether the previous upgrade operation is completed.

[0034] In addition, in this embodiment, when the second CPU performs certain system actions (such as erasing the APP area, updating the flag bit, etc.), it will send a signal to the first CPU through the IPC mechanism. These system actions usually require the cooperation of the first CPU to complete. For example, after completing the firmware upgrade, the second CPU may need the first CPU to jump to the respective APP area or clear the relevant flag bit together to ensure the normal operation of the dual-core DSP chip.

[0035] Based on the above steps A1 to A3, in this embodiment, the first CPU can decide whether to enter the APP program according to different conditions to ensure the integrity and security of the firmware upgrade. In this process, the first CPU acts as the main control core, is responsible for most operations, and coordinates the work of the second CP2, ultimately achieving stable operation of the dual-core DSP chip during the upgrade process.

[0036] In steps S5 and S7, after the first CPU cooperates with the second CPU to complete the upgrade, the method further includes: The first CPU and the second CPU jump to their respective APP areas respectively, so that the first CPU and the second CPU respectively execute APP programs in their respective APP areas.

[0037] At present, most energy storage systems are upgraded using SCI communication (a serial communication), which has the problems of poor anti-interference ability, low reliability of data transmission and high complexity of hardware implementation. To this end, this embodiment further makes the following improvements: the first CPU and / or the second CPU sends and receives data through the CAN communication interface, and the first CPU and the second CPU perform synchronous operation through the IPC mechanism.

[0038] It should be noted that CAN communication has the advantages of strong real-time performance, long transmission distance, strong anti-electromagnetic interference ability and low cost. The first CPU and / or the second CPU sends and receives data through the CAN communication interface, which can help ensure the stability of the online upgrade of the dual-core DSP chip. In the process of firmware upgrade based on this embodiment, the first CPU acts as the main control core. At this time, the first CPU mainly communicates with peripherals such as the communication board. Specifically, the communication board and other peripherals can interact with the first CPU through the CAN communication interface in the form of CAN communication, such as sending an upgrade instruction to the first CPU to instruct the first CPU to enter the upgrade mode, sending a data packet and status information to the first CPU, and receiving status information such as the upgrade completion instruction sent by the first CPU, which is not limited here.

[0039] In this embodiment, the right to use CAN communication can also be switched back and forth between the first CPU and the second CPU to increase the autonomy during the upgrade process. For example, the first CPU can be upgraded first and then the second CPU.

[0040] In addition, when the first CPU decides to jump to the Bootloader area, APP area (or execute other critical tasks), it can notify the second CPU through the IPC mechanism to ensure that both jump to the Bootloader area, APP area or execute a task at the same time. Based on this, through the IPC mechanism, the two CPUs in the dual-core DSP chip can achieve high synchronization without external interference, which ensures that in a multi-core environment, the two CPUs can enter the Bootloader area for upgrading or jump back to the APP area in a coordinated manner, thereby avoiding system instability caused by asynchrony between cores.

[0041] In this embodiment, the dual-core DSP chip is upgraded online in a state machine polling manner. It should be noted that during the implementation of this embodiment, the current state of the chip is continuously checked in a state machine polling manner, and the next operation is determined, that is, the firmware upgrade process is controlled in a state machine polling manner, so that the system can perform reasonable process control according to the current state and input conditions. The use of the state machine ensures the orderly progress of the upgrade process and simplifies the debugging and maintenance of the process, thereby ensuring that the first CPU and the second CPU of the dual-core DSP chip can efficiently coordinate to complete the upgrade task.

[0042] This embodiment can improve the stability of online upgrade of dual-core DSP chip. It should be noted that in this embodiment, the design of delay detection avoids accidentally staying in Bootloader mode when there is no upgrade demand, thereby improving the stability and reliability of the system. At the same time, this embodiment replaces the traditional address jump method by introducing software forced restart (such as watchdog restart). Specifically, during the implementation of this embodiment, after receiving the upgrade instruction, the first CPU will execute the software forced restart action in the APP program, and enter its Bootloader area through the timing mechanism to execute the Bootloader program and complete the subsequent online upgrade process. Based on this, this embodiment can ensure the stable operation of the dual-core DSP chip when switching programs, avoid instability caused by program jumps, and prevent unsaved data or uncompleted operations that may be caused by direct jumps. At the same time, it allows the dual-core DSP chip to detect and trigger firmware upgrades during operation without physically restarting the device, reducing system downtime and improving system maintenance efficiency.

[0043] Embodiment 2: Based on Embodiment 1 or 2, this embodiment discloses an electronic device, which may be a smart phone, a tablet computer, a laptop computer, or a desktop computer. The electronic device may be referred to as a user terminal, a portable terminal, a desktop terminal, etc. Figure 2 As shown, the electronic equipment includes: a memory for storing computer program instructions; and, The processor is used to execute the computer program instructions to complete the operation of the dual-core DSP chip online upgrade method as described in any one of Embodiment 1.

[0044] Specifically, the processor 301 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 301 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 301 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 301 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen.

[0045] The memory 302 may include one or more computer-readable storage media, which may be non-transitory. The memory 302 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 302 is used to store at least one instruction, which is used to be executed by the processor 301 to implement the dual-core DSP chip online upgrade method provided in Example 1 of the present application.

[0046] In some embodiments, the terminal may further optionally include: a communication interface 303 and at least one peripheral device. The processor 301, the memory 302 and the communication interface 303 may be connected via a bus or a signal line. Each peripheral device may be connected to the communication interface 303 via a bus, a signal line or a circuit board. Specifically, the peripheral device includes: at least one of a radio frequency circuit 304, a display screen 305 and a power supply 306.

[0047] The communication interface 303 may be used to connect at least one peripheral device related to I / O (Input / Output) to the processor 301 and the memory 302. In some embodiments, the processor 301, the memory 302, and the communication interface 303 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 301, the memory 302, and the communication interface 303 may be implemented on a separate chip or circuit board, which is not limited in this embodiment.

[0048] The radio frequency circuit 304 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The radio frequency circuit 304 communicates with a communication network and other communication devices through electromagnetic signals.

[0049] The display screen 305 is used to display a UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof.

[0050] The power supply 306 is used to supply power to various components in the electronic device.

[0051] Embodiment 3: Based on any one of Embodiments 1 to 2, this embodiment discloses a computer-readable storage product, on which instructions are stored, and when the instructions are run on a computer, the online upgrade method for a dual-core DSP chip as described in any one of Embodiments 1 is executed. The computer-readable storage product refers to a carrier for storing data, which may include but is not limited to computer-readable storage media such as floppy disks, optical disks, hard disks, flash memories, USB flash drives, and / or memory sticks, and the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.

[0052] Embodiment 4: Based on any one of Embodiments 1 to 2, this embodiment discloses a computer program product, including a computer program or instructions, which, when executed by a computer, implements the dual-core DSP chip online upgrade method as described in any one of Embodiments 1.

[0053] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the above embodiments, a person skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dual-core DSP chip online upgrade method, characterized in that: include: Divide the two CPUs in the designated dual-core DSP chip into a first CPU and a second CPU, and use the first CPU as a main control core; Based on a preset CMD file, the FLASH area of ​​the dual-core DSP chip is divided into a first FLASH area corresponding to the first CPU and a second FLASH area corresponding to the second CPU, and the Bootloader area in the first FLASH area is used as the default startup address after the dual-core DSP chip is powered on; wherein the first FLASH area and the second FLASH area both include a Bootloader area for storing a Bootloader program and an APP area for storing an APP program; After the dual-core DSP chip is powered on, the dual-core DSP chip is initialized; The dual-core DSP chip enters the Bootloader area corresponding to the first CPU according to the configuration of the CMD file, so that the first CPU executes the Bootloader program stored in its Bootloader area; The first CPU performs a delay detection and determines whether an upgrade instruction is received within a specified time period. If yes, the first CPU cooperates with the second CPU to perform an online upgrade. If no, proceed to the next step. The first CPU and the second CPU jump to their respective APP areas respectively, so that the first CPU and the second CPU respectively execute the APP programs stored in their respective APP areas; The first CPU determines whether an upgrade instruction is received. If so, the first CPU executes a software forced restart action so that the first CPU enters its Bootloader area and cooperates with the second CPU to perform online upgrade.

2. A dual-core DSP chip online upgrade method according to claim 1, characterized in that: The dual-core DSP chip is initialized, including: Checking a status of the second CPU, and starting the second CPU when the second CPU works normally; Initialize the clock module, GPIO interface and CAN communication interface in the dual-core DSP chip; Setting an ISR for the CAN communication interface; Configuring corresponding message objects in the dual-core DSP chip so that the CAN communication interface can correctly send and receive messages; And, the FLASH area in the dual-core DSP chip is initialized, and the permission for the first CPU to read and write FLASH is set.

3. The method for online upgrading of a dual-core DSP chip according to claim 1, characterized in that: The first CPU and / or the second CPU sends and receives data via a CAN communication interface, and the first CPU and the second CPU perform synchronous operations via an IPC mechanism.

4. The method for online upgrading of a dual-core DSP chip according to claim 1, characterized in that: The dual-core DSP chip is upgraded online in a state machine polling manner.

5. The method for online upgrading of a dual-core DSP chip according to claim 1, characterized in that: The first CPU cooperates with the second CPU to perform online upgrade, including: The first CPU determines whether a FLASH operation instruction is received. If yes, the first CPU parses the FLASH operation instruction, executes an action matching the FLASH operation instruction, and proceeds to the next step. If no, the first CPU directly proceeds to the next step. The first CPU performs a time counting detection to obtain a time counting value between the time when the first CPU receives the upgrade instruction and the current time; When the time count value is greater than a pre-designed value, there is executable code in the APP area of ​​the first CPU, and there is an upgrade flag in the Bootloader area of ​​the first CPU, the state of the dual-core DSP chip is a JUMP state, and the first CPU communicates with the second CPU in a coordinated manner so that the first CPU and the second CPU jump to their respective APP areas respectively, so that the first CPU and the second CPU respectively execute APP programs stored in their respective APP areas.

6. A dual-core DSP chip online upgrade method according to claim 5, characterized in that: The FLASH operation instructions include erase instructions and program instructions; correspondingly, the message parsing function sCANProcess() is used to parse the FLASH operation instructions.

7. The method for online upgrading of a dual-core DSP chip according to claim 1, characterized in that: After the first CPU cooperates with the second CPU to complete the upgrade, the method further includes: The first CPU and the second CPU jump to their respective APP areas respectively, so that the first CPU and the second CPU respectively execute APP programs in their respective APP areas.

8. An electronic device, characterized in that: include: a memory for storing computer program instructions; as well as, A processor is used to execute the computer program instructions to complete the operation of the dual-core DSP chip online upgrade method as described in any one of claims 1 to 7.

9. A computer readable storage product, characterized in that: The computer-readable storage product stores instructions, and when the instructions are executed on a computer, the online upgrade method for a dual-core DSP chip as claimed in any one of claims 1 to 7 is executed.

10. A computer program product comprising a computer program or instructions, characterized in that The computer program or the instruction, when executed by a computer, implements the dual-core DSP chip online upgrade method as claimed in any one of claims 1 to 7.

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