Single-channel multi-data-source transmission system and method based on SRIO

Abstract

The invention discloses a single-channel multi-data-source transmission system and method based on SRIO, and belongs to the technical field of data transmission. The FPGA subsystem comprises an FPGA preprocessing module, an SRIO sending module, an SRIO reset module and an SRIO receiving module. The DSP subsystem comprises a DSP receiving module, a DSP sending driving layer, a DSP sending interface layer, a DSP sending application layer and an EMIF setting module; and through an SRIO sending module, the SRIO packets packaged by the FPGA data preprocessing modules of the preceding-stage multiple channels are sequenced and sent. The SRIO carries out non-response transmission, and compared with processing of short packet data in the prior art, the transmission efficiency and the real-time performance are greatly improved; the chip cycle operation is added, compared with the previous single cache or ping-pong operation, the storage space is increased, the preceding stage transmission does not need to wait for the processing feedback time of the backward stage, large-scale continuous storage is directly carried out, and the problem of waiting delay is solved through the continuous storage.

Description

Technical Field

[0001] The present invention belongs to the technical field of data transmission, and in particular relates to a single-channel multi-data source transmission system and method based on SRIO. Background Art

[0002] Existing data processing systems are often developed using embedded platforms, with DSP+FPGA made into PCB. DSP processes total data messages and controls the flow, and FPGA expands the hardware interface. The DSP and FPGA internal communication core uses SRIO (Serial Rapid IP) and EMIF (External Memory Interface) external memory. SRIO is a high-speed serial communication interface protocol with a simple and flexible topology and few serial hardware buses. It is a high-reliability, high-performance, packet-switched high-speed interconnect technology for embedded systems. EMIF is a commonly used parallel communication connection method between DSP chips and FPGAs, with excellent performance, great convenience and flexibility.

[0003] In existing data transmission systems, EMIF is commonly used for data transmission on interfaces with uncertain time lengths, such as serial ports and SPI, and SRIO is used for large-scale continuous data transmission. This method has the problems of low EMIF rate and poor timeliness. Alternatively, SRIO is used to transmit stream mode data packets of less than or equal to 256 bytes. This method results in low SRIO bandwidth utilization, affecting the overall data transmission efficiency. Summary of the invention

[0004] The present invention aims to solve the above-mentioned data transmission using different interfaces and different formats, and uniformly use SRIO for fast and efficient data transmission; add a slice cyclic polling method to solve the problem of fast and continuous large-scale storage of short packets, and simultaneously shorten the delay waiting in the transmission process; provide a single-channel multi-data source transmission system and method based on SRIO.

[0005] In a first aspect, the present invention provides a single-channel multi-data source transmission system based on SRIO, comprising an FPGA subsystem and a DSP subsystem; The FPGA subsystem includes an interface channel module, an FPGA preprocessing module, an SRIO sending module, an EMIF status module, an SRIO reset module and an SRIO receiving module; The interface channel module is used to externally connect multiple interface hardware; the FPGA preprocessing module is used to preprocess data from the external interface; the SRIO sending module is used to send data packets and doorbell packets; the EMIF status module is used to store the latest status results of the current interface channel; the SRIO reset module is used to reset when the SRIO link is initialized or abnormal; the SRIO receiving module is used to receive SRIO data packets; The DSP subsystem includes a DSP receiving module, a DSP doorbell module, a DSP transmission driver layer, a DSP transmission interface layer, a DSP transmission application layer and an EMIF setting module; The DSP receiving module is used to receive and write data into the DSP memory; the DSP doorbell module is used to identify the interrupt source of the doorbell interrupt; the DSP sending application layer is used to process the data that needs to be sent by each interface; the DSP sending interface layer starts the DSP sending driver layer to send the SRIO packet according to the data volume in batches and time division; the EMIF setting module has storage performance, which is used to make SRIO protocol agreements, and set the SRIO chip cycle address, chip cycle size, chip cycle number, doorbell interrupt data length, and doorbell interrupt data packet number of each channel.

[0006] Furthermore, in the SRIO-based single-channel multi-data source transmission system of the present invention, the interface channel module receives or sends data according to the sampling clock of each interface; the number of receiving interfaces is at most 64, the number of sending interfaces is at most 2×32, and the sum of the interface bandwidths is less than or equal to the SRIO bandwidth.

[0007] Furthermore, in the SRIO-based single-channel multi-data source transmission system of the present invention, when the FPGA preprocessing module performs data preprocessing, data is packaged according to the SRIO protocol of the EMIF setting module and the internal slice loop; the packaged data includes adding a header, subpacketizing, and adding a doorbell packet; and the data packet after packaging is passed to the SRIO sending module.

[0008] Furthermore, in the SRIO-based single-channel multi-data source transmission system of the present invention, the SRIO reset module clears and resets the SRIO count, FIFO, and status word inside the FPGA when resetting; the FPGA subsystem detects the link status of the SRIO in real time, and notifies the DSP subsystem through the EMIF status module when the link link or port is abnormal, and performs reset and reconnection.

[0009] Furthermore, in the SRIO-based single-channel multi-data source transmission system of the present invention, the DSP doorbell module identifies the interrupt source of the doorbell interrupt and uses the DoorBell interrupt to notify the DSP subsystem; after the DSP subsystem enters the doorbell interrupt, it first searches for which interface channel the interrupt is based on the DoorBell doorbell interrupt, and then identifies the address area of ​​the chip cyclic polling and the valid byte length of each chip address area through the EMIF status module.

[0010] Furthermore, in the SRIO-based single-channel multi-data source transmission system of the present invention, after the FPGA preprocessing module completes data packaging and before the SRIO sending module sends the doorbell packet, the FPGA subsystem updates the latest status result of the current interface channel and stores it through the EMIF status module, so as to facilitate the DSP to query the status result after the doorbell interrupt, identify the chip cyclic polling result, and completely store and retrieve the data.

[0011] In a second aspect, the present invention provides a transmission method of the SRIO-based single-channel multi-data source transmission system according to the first aspect, including a data uplink process and a data downlink process; The data uplink process includes: the FPGA subsystem receives data from the hardware of multiple external interfaces, performs data preprocessing through the FPGA preprocessing module, processes and packages the data of each interface channel according to the preset doorbell interrupt protocol and chip cycle protocol, and then sends the data packet and the doorbell packet to the DSP subsystem through the SRIO sending module, sends the multi-channel data of the previous stage to the DSP through an SRIO channel, and the DSP's DDR3 performs data caching; directly caches the data in the DSP's memory, does not need to use the FPGA's redundant cache, and the FPGA only needs to process the packets in real time and actively upload them; the speed of the SRIO sending module is much faster than the packaging speed of the previous preprocessing module; when there is only one channel to be sent, the data of this channel is directly sent out; when there are two or more channels of data to be sent, the data packets are sent out in sequence according to the channel number; After receiving the data, the SRIO bottom layer of the DSP starts DMA to move the data, and stores the data in the corresponding memory area of ​​the DSP one by one according to the address and length of the SRIO packet header protocol; after receiving the doorbell interrupt, first verify the current interrupt source identification channel, then query the EMIF status module of the channel, query the first address of the current interrupt slice cycle and the first address of the previous slice cycle of the current channel, and the short packet complement interface will simultaneously identify the number of valid data bytes of each slice address, and then extract the valid data between the two interrupts for subsequent application layer processing; The data downlink process includes: the DSP subsystem sends data in batches and at different times; the FPGA subsystem encapsulates the data according to the agreed interface channel protocol; the FPGA subsystem identifies the header address information in the packet, determines which interface channel the data belongs to, extracts the data, and directly puts the data into the corresponding interface FIFO for external transmission in the order in which the packets are received.

[0012] Because the transmission speed of SRIO is much faster than the external interface speed, only the data transmission protocol needs to be agreed upon, and no priority processing is required. The timing of data downlink is actively controlled by the DSP. It is only necessary to consider not sending data too fast, which will exceed the number of FPGA FIFO buffers and thus lose data. At the same time, because FPGA is parallel, there is no need to send doorbell interrupts to FPGA, and there is no need to consider the problem of FPGA's real-time response. At the same time, there is no doorbell constraint, so the number of data channels sent by DSP to FPGA is much greater than 64, and can reach 2×16 channel data.

[0013] Furthermore, in the SRIO-based single-channel multi-data source transmission method of the present invention, the doorbell interrupt protocol stipulates the interrupt data volume of each channel; when the data volume of a channel sent by the FPGA reaches one packet, two packets, or more packets, it is necessary to send a doorbell interrupt notification to the DSP (the number of packets is set by the DSP to the FPGA according to the hardware interface characteristics), and the packet header address protocol in one doorbell is accumulated according to the chip cycle head address of this time, and the next doorbell needs a new chip cycle head address for accumulation.

[0014] Furthermore, in the single-channel multi-data source transmission method based on SRIO described in the present invention, the slice cycle protocol stipulates how many doorbell interrupts a channel continuously stores and the length of a single doorbell interrupt data; after sending a doorbell, the new data needs to offset the first address of the packet header according to the slice cycle protocol to ensure that the data area is continuous and can be arranged continuously according to the length of the doorbell; at the same time, after the DSP turns off the interrupt and turns it on again, the DSP queries the status register value of the FPGA slice cycle through the EMIF status module, detects the interval area between the two interrupts, and can completely identify the cached data in DDR3; the doorbell interrupt protocol and the slice cycle protocol are changed and constrained by the EMIF communication between the DSP and the FPGA. It is convenient for the DSP to still read the intermediate data after actively turning off the interrupt.

[0015] Furthermore, the SRIO-based single-channel multi-data source transmission method of the present invention, when processing short packet data according to the chip loop protocol polling, for discontinuous short packet type data, the FPGA needs to perform data packet break processing; the broken packet is judged according to time; for data with inconsistent lengths, the complement or packetization or doorbell interrupt is used for processing; for continuous data, wait for 256 bytes to be met and encapsulated into a SWRITE packet. The complement method is: when a single data packet is <= 256 bytes, the fixed data 0x80 is added to make it up to 256 bytes, and the specific number of bytes is updated through the EMIF status register; the packet sub-method is: when a single data packet is > 256 bytes, it is packetized according to 256 bytes. If the last packet is less than 256, it is still supplemented to 256 bytes; the doorbell adding method is: the doorbell is set according to the requirements of the hardware interface. For the short packet data interface, the doorbell interrupt is set according to one packet. After packet sub-method or complement, the short packet interface needs to add a doorbell interrupt; the doorbell interrupt of each interface is set separately; for large-volume continuous data interfaces, a doorbell is sent after multiple packets of data; for example, the serial port sets a doorbell for a single packet of data, so a doorbell packet needs to be added after the single packet of data; for large-volume or continuous data, one more doorbell can be packaged, such as video, one doorbell interrupt for one picture.

[0016] The SRIO-based single-channel multi-data source transmission system and method of the present invention can be used to sort and send out the SRIO packets encapsulated by the FPGA data preprocessing modules of the front-stage multiple channels through the SRIO sending module. SRIO performs non-response transmission, which greatly improves the transmission efficiency and real-time performance compared to the processing of short packet data in the prior art; adding slice loop operation increases the storage space compared to the previous single cache or ping-pong operation, and the front-stage transmission does not need to wait for the processing feedback time of the back-stage, and directly performs large-scale continuous storage. This continuous storage solves the waiting delay problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the framework of a single-channel multi-data source transmission system based on SRIO according to an embodiment of the present invention; Figure 2 It is a communication flow chart of a single-channel multi-data source transmission system based on SRIO according to an embodiment of the present invention; Figure 3 is a schematic diagram of the data uplink process according to an embodiment of the present invention; Figure 4 It is a schematic diagram of the data downlink process according to an embodiment of the present invention; Figure 5 It is a schematic diagram of the single-channel slice cycle plus doorbell transmission process according to an embodiment of the present invention; Figure 6It is a schematic diagram of the SRIO doorbell packet header protocol of the DSP according to an embodiment of the present invention; Figure 7 It is a partial protocol diagram of the SRIO doorbell packet header of the DSP described in an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The SRIO-based single-channel multi-data source transmission system and method of the present invention are described in detail below through the accompanying drawings and embodiments.

[0019] Embodiment 1 The present embodiment discloses a single-channel multi-data source transmission system based on SRIO, including an FPGA subsystem and a DSP subsystem; the FPGA subsystem includes an interface channel module, an FPGA preprocessing module, an SRIO sending module, an EMIF status module, an SRIO reset module and an SRIO receiving module; the DSP subsystem includes a DSP receiving module, a DSP doorbell module, a DSP sending driver layer, a DSP sending interface layer, a DSP sending application layer and an EMIF setting module.

[0020] In the disclosed embodiment, a 4x SRIO and an EMIF16 interface are connected between the FPGA subsystem and the DSP subsystem. An EMIF16 interface is used. Considering a storage feature of EMIF, the EMIF is used for the SRIO protocol agreement, and the slice cycle address, slice cycle number, and doorbell interrupt data length of each channel can be flexibly configured. The FPGA provides real-time status feedback through EMIF16 in real time. SRIO only transmits stream mode and doorbell interrupt. The actual use of SRIO bidirectional can reach a bandwidth speed of 1.1GB / s at the same time.

[0021] The interface channel module is a hardware that connects multiple external interfaces and is the input and output of system communication data. The interface channel module receives or sends data according to the sampling clock of each interface. The receiving interface can reach up to 64, and the sending interface can reach 2×32. The sum of the interface bandwidth is less than or equal to the SRIO bandwidth. When the amount of interface data reaches a certain value or reaches a certain time condition, the preprocessing module will start processing.

[0022] The FPGA pre-processing module is used to process data from the external interface and package the interface data according to the SRIO protocol of the EMIF setting module and the internal chip cycle count result. Packing data mainly includes adding headers, subpackets, and adding doorbell packets. After packaging, the data packets are passed to the SRIO sending module.

[0023] After the EMIF status module is packaged with the FPGA and the processing module, and before the FPGA's SRIO sending module sends the doorbell packet, the FPGA will update the latest status result of the current interface channel to facilitate the DSP to query the status result after the doorbell interrupt, identify the chip cycle result, and completely store and retrieve the data.

[0024] The SRIO reset module needs to be reset when the SRIO link is initialized or abnormal. The reset will clear and reset the FPGA's internal SRIO counts, FIFO, status words, etc. The FPGA will detect the SRIO link status in real time. When the link or port is abnormal, it will notify the DSP through EMIF16 to reset and reconnect.

[0025] DSP receiving module, DSP receiving is relatively simple, SRIO bottom layer will judge the protocol packet type according to the packet header, such as Figure 6 , Figure 7 As shown, the stream mode packet carrying the data word uses DMA to write the data into the DSP memory according to the DSP memory address agreed in the packet header and the data length of this packet.

[0026] The DSP doorbell module identifies the interrupt source of the doorbell interrupt. In order for the DSP to process data quickly and in real time, the DoorBell interrupt is used to notify the DSP. After entering the doorbell interrupt, the DSP first searches for the interface channel interrupt according to the DoorBell doorbell interrupt, and then identifies the address area of ​​the chip cyclic polling and the effective byte length of each chip address area through the EMIF16 status module.

[0027] The DSP transmission driver layer, DSP transmission interface layer, and DSP transmission application layer are three modules used for DSP to send data to FPGA. The DSP transmission application layer processes the data that needs to be sent by each interface. The DSP transmission interface layer starts the DSP transmission driver layer to send out SRIO packets according to the data volume in batches and time. The FPGA's SRIO receiving module receives the SRIO data packets and distributes them to each transmission interface module according to the packet header protocol. Each interface sends the data out in sequence.

[0028] Considering the storage performance of EMIF, the EMIF interface is used for SRIO protocol agreement. The EMIF setting module flexibly and conveniently sets the SRIO slice cycle address, slice cycle size, slice cycle number, doorbell interrupt data length, and doorbell interrupt data packet number of each channel.

[0029] In the disclosed embodiment, the DSP and FPGA internal communication core uses SRIO and EMIF external memory, and the SRIO protocol agreement between the DSP and the FPGA and the status result feedback of the slice cycle are very convenient through the EMIF interface. With the assistance of EMIF, the SRIO link only sends data packets in stream mode and doorbell packets without data, which greatly improves the transmission efficiency of SRIO.

[0030] SRIO transmission mainly includes two types of transmission: IO and Message. There are multiple protocol packet formats under these two transmission types. Based on the system usage requirements, this technical solution only uses two types of SWRITE packets (stream mode) and DOORBELL packets (doorbell interrupt packets). The stream mode is used for data transmission, and the doorbell is used to notify interrupts.

[0031] The SWRITE packet specifies that the protocol packet consists of a 64-bit header and a 1 to 256-byte data. The header carries the ID, packet mode, packet data length, and the destination address of the receiver. The receiver will parse the header and transfer the data of the corresponding length in the packet to the specified address. In this embodiment, the data length carried by SWRITE is 256 bytes, which makes the use efficiency of SRIO very high.

[0032] DOORBELL packet, 64-bit packet header will carry data protocol, of which 16-bit info segment will carry interrupt message, DSP can receive up to 64 DOORBELL doorbell interrupts. These 64 interrupts can be used to identify the interrupt source. After sending data in stream mode, FPGA sends a DOORBELL interrupt to DSP to notify DSP that data is completed, so that subsequent processing can be carried out in time.

[0033] This system is connected to data from multiple interfaces. FPGA is a parallel processor that receives and sends data from different clock domains, different data lengths, different data bits, and different time periods in real time. The data is continuously stored in the DSP's memory through a 4xSRIO interface. When a certain amount or time is reached, the DSP is notified through the SRIO doorbell interrupt, and the DSP processes the data.

[0034] Embodiment 2 Based on the SRIO-based single-channel multi-data source transmission system disclosed in the first embodiment, this embodiment discloses a SRIO-based single-channel multi-data source transmission method, such as Figure 1 , Figure 3 , Figure 4As shown in the figure, two bidirectional communication interfaces are connected between the two subsystems FPGA and DSP subsystem, a parallel EMIF16 interface and a high-speed serial 4x SRIO interface. The EMIF interface is constrained by the SRIO protocol. The DSP memory is expanded to a 2GB DDR3, which can cache data in large quantities.

[0035] There are two directions of data transmission, data downlink (sent from DSP to FPGA) and data uplink (sent from FPGA to DSP). Due to the differences between the two processors, there are slight differences in the schemes used for data uplink and data downlink. The specific data transmission process is as follows: Data uplink: Data comes in from the FPGA external hardware interface and reaches the dual-port RAM of the FPGA external interface. The FPGA preprocessing module performs data preprocessing and uses DSP for extended cache. Because the FPGA code is compiled once and takes effect once, the number of FIFOs for each channel of the FPGA is limited. The data of each channel is preprocessed and packaged according to the set doorbell interrupt protocol and chip cycle protocol, and then sent. The data enters the DSP's memory DDR3 and is cached by the DSP's DDR3 to achieve an extended cache function. The doorbell interrupt protocol stipulates the interrupt data volume of each channel. When the data volume of a channel sent by the FPGA reaches one packet, two packets, or more packets, it is necessary to send a doorbell interrupt notification to the DSP (the number of packets is set to the FPGA by the DSP according to the hardware interface characteristics). The packet header address protocol in a doorbell is accumulated according to the chip cycle head address of this time. The next doorbell needs a new chip cycle head address for accumulation.

[0036] The chip cycle protocol stipulates how many doorbell interrupts a channel can store continuously and the length of a single doorbell interrupt data. After sending a doorbell, the new data needs to offset the header address according to the chip cycle protocol to ensure that the data area is continuous and can be arranged continuously according to the length of the doorbell. At the same time, there is a need to turn off interrupts in DSP applications. After the DSP turns off the interrupt and turns it on again, the DSP queries the status register value of the FPGA chip cycle polling through the EMIF status module, detects the interval area between the two interrupts, and can fully identify the cached data in DDR3. The doorbell interrupt protocol and the chip cycle protocol are changed and constrained by the EMIF communication between the DSP and the FPGA. It is convenient for the DSP to read the intermediate data after actively turning off the interrupt.

[0037] The on-chip cyclic polling process of short packet data requires special processing. For discontinuous short packet types such as serial port and SPI data, FPGA has a data packet break function. The packet break is judged according to the time. After the baud rate and other proportional time, it is considered to be a packet of data. Due to the inconsistent length of serial port data, considering the real-time problem of the system, there will be operations such as complement, packetization, and doorbell interrupt. For continuous image, AD and other data, no complement is required, and only the 256-byte encapsulation process SWRITE packet needs to be met.

[0038] Among them, the complement processing method is: when the single data packet is <= 256 bytes, the fixed data 0x80 is added to make it 256 bytes, and the specific number of bytes will be updated through the EMIF status register. The packet processing method is: when the single packet data is > 256 bytes, it needs to be packetized according to 256 bytes. If the last packet is less than 256, it is still padded to 256 bytes. The doorbell interrupt processing method is: the doorbell is set according to the requirements of the hardware interface. For the short packet data interface, the doorbell interrupt will be set according to one packet. After packetization or complement, the short packet interface needs to add a doorbell interrupt. The doorbell interrupt of each interface is separate. For large-volume continuous data interfaces, a doorbell is sent after multiple packets of data. For example, the serial port sets a doorbell for a single packet of data, so a doorbell packet needs to be added after the single packet of data. For large-volume or continuous data, you can package more than one doorbell, such as video, one doorbell interrupt for one picture.

[0039] After being packaged by the slice loop protocol of the pre-processing module, it enters the FPGA sending module of the latter stage. This module mainly sends the multi-channel data of the previous stage to the DSP through an SRIO channel. The speed of this module is much faster than the packaging speed of the pre-processing module of the former stage. When there is only one channel to be sent, the data of this channel is sent directly; when there are two or more channels of data to be sent, the data packets are sent out in sequence according to the channel number. It is directly cached in the memory of the DSP, and there is no need to use the redundant cache of the FPGA. The FPGA only needs to process the packets in real time and upload them actively. The SRIO sending module sends the data packets and doorbell packets.

[0040] After receiving the data, the SRIO bottom layer of the DSP will start DMA to move the data, and store the data in the corresponding memory area of ​​the DSP one by one according to the address and length of the SRIO packet header protocol. After receiving the doorbell interrupt, first verify the current interrupt source identification channel, then query the EMIF status module of the channel, query the first address of the current interrupt slice cycle and the first address of the last slice cycle of the current channel, and the short packet complement interface will simultaneously identify the number of valid data bytes of each slice address, and then extract the valid data between the two interrupts for subsequent application layer processing.

[0041] Data downlink: Data downlink is relatively simple. FPGA decodes the packet header protocol of DSP's SRIO serial streaming mode data, distributes it to their respective channel FIFOs, and sends it to the hardware interface. Because the transmission speed of SRIO is much faster than the external interface speed, it is only necessary to agree on the data transmission protocol, and no priority processing is required. The timing of data downlink is actively controlled by DSP. It is only necessary to consider that the data should not be sent too fast, resulting in exceeding the number of FPGA FIFO buffers and thus losing data. At the same time, because FPGA is parallel, there is no need to send doorbell interrupts to FPGA, and there is no need to consider the problem of FPGA's real-time response. At the same time, there is no doorbell constraint, so the number of data channels sent by DSP to FPGA is much greater than 64. From a theoretical design, it can reach 2×16 channel data (the actual system only uses 39).

[0042] When DSP sends data, it is subject to time constraints. It cannot send data exceeding the FIFO buffer capacity to this interface within the limited time of the hardware interface. For this reason, the DSP interface layer sends data in batches and at different times. According to the agreed interface channel protocol packet, mainly the address information of the packet header, FPGA identifies the packet header address information, determines which interface channel the data belongs to, extracts the data, and directly puts it into the corresponding interface FIFO for external transmission according to the order in which the packets are received.

[0043] In the disclosed embodiment, an EMIF16 interface is used, combined with the SRIO module, to provide double protection for the communication of the system. The FPGA monitors the link and port link status of the SRIO link in real time, and notifies the DSP to reset and reconnect the SRIO when abnormal, so that the transmission of the system is more stable and reliable. During initialization, EMIF is used to constrain the SRIO protocol between the DSP and the FPGA. For example, the protocol stipulates that the starting address of the first picture of the SDI (1920*1080*2Byte) format video is 0x90000000, the number of doorbell interrupt packets of the SDI is 1920*1080*2 / 256 = 16200, and the number of slice cycle polling is 50. The actual effect is that the SDI video data is arranged continuously according to the data byte stream of the video frame. When a picture is transmitted, the FPGA will add a doorbell interrupt to notify the DSP that a picture has been completed and 50 video data are stored continuously. When 50 images are fully stored, it returns to the address 0x90000000 to continue storing. When 50 images are fully stored, it returns to the first address 0x90000000 to continue caching. The EMIF status update mainly updates the first address of the doorbell interrupt and notifies the DSP where the first address of the image is. If it is a short packet data such as a serial port, it will also notify the DSP of the number of valid bytes of this data, because the serial port short packet has a complement operation, and the DSP is notified of the number of valid bytes of this packet through EMIF.

[0044] Based on the communication example of SRIO multi-channel control between DSP and FPGA, the data is divided into blocks according to the maximum SRIO data packet, and the chip loop polling mode is added, plus the doorbell interrupt operation. The interface module's interrupt packet + doorbell + 256-byte SWRITE packet operation greatly improves the real-time performance of the system's transmission and processing of data. Considering that DSP cannot always process data, the communication needs can be processed in a timely and complete manner through the interrupt packet and doorbell operations. Figure 2 , Figure 5 As shown in the flow chart, through the slice loop polling mode, there is no DSP involved in the data control flow of the FPGA, which greatly simplifies the work of the FPGA. The FPGA does not need to consider the feedback problem when uplinking data. The FPGA only needs to consider the received data package to send, and the large batch cache data is executed by the DSP memory.

[0045] DSP reception is also independent of the DSP program flow, and is automatically executed by the SRIO module + DMA module, depending on the SRIO slice cycle protocol and channel protocol. The SRIO bottom layer uses DMA to move the data of the SWRITE packet to the memory area one by one according to the 32-bit address in the packet header and the 8-bit length information in the packet header. DMA is a high-speed access peripheral, and the DSP program flow control is not required to move data here. For a serial CPU such as DSP, it can be completed without taking up program time, saving a lot of time.

[0046] For the data sent by DSP to FPGA, the sending protocol is agreed upon when the SRIO protocol is initialized. FPGA extracts the address information corresponding to the packet header protocol, identifies which channel the data belongs to, extracts the data, and forwards it to the corresponding interface channel.

Claims

1. A single-channel multi-data source transmission system based on SRIO, characterized in that: Including FPGA subsystem and DSP subsystem; The FPGA subsystem includes an interface channel module, an FPGA preprocessing module, an SRIO sending module, an EMIF status module, an SRIO reset module and an SRIO receiving module; The interface channel module is used to externally connect multiple interface hardware; the FPGA preprocessing module is used to preprocess data from the external interface; the SRIO sending module is used to send data packets and doorbell packets; the EMIF status module is used to store the latest status results of the current interface channel; the SRIO reset module is used to reset when the SRIO link is initialized or abnormal; the SRIO receiving module is used to receive SRIO data packets; The DSP subsystem includes a DSP receiving module, a DSP doorbell module, a DSP transmission driver layer, a DSP transmission interface layer, a DSP transmission application layer and an EMIF setting module; The DSP receiving module is used to receive and write data into the DSP memory; the DSP doorbell module is used to identify the interrupt source of the doorbell interrupt; the DSP sending application layer is used to process the data that needs to be sent by each interface; the DSP sending interface layer starts the DSP sending driver layer to send the SRIO packet according to the data volume in batches and time division; the EMIF setting module has storage performance, which is used to make SRIO protocol agreements, and set the SRIO chip cycle address, chip cycle size, chip cycle number, doorbell interrupt data length, and doorbell interrupt data packet number of each channel.

2. The SRIO-based single-channel multi-data source transmission system according to claim 1, characterized in that: The interface channel module receives or sends data according to the sampling clock of each interface; the receiving interface is at most 64, the sending interface is at most 2×32, and the sum of the interface bandwidths is less than or equal to the SRIO bandwidth.

3. The SRIO-based single-channel multi-data source transmission system according to claim 1, characterized in that: When the FPGA preprocessing module performs data preprocessing, the data is packaged according to the SRIO protocol of the EMIF setting module and the internal chip loop protocol; the packaged data includes adding a header, subpacketing, and adding a doorbell packet; The packaged data packet is passed to the SRIO sending module.

4. The SRIO-based single-channel multi-data source transmission system according to claim 1, characterized in that: When the SRIO reset module is reset, the FPGA internal SRIO count, FIFO, and status word are cleared and reset; the FPGA subsystem detects the link status of the SRIO in real time, and notifies the DSP subsystem through the EMIF status module when the link or port is abnormal, and performs reset and reconnection.

5. The SRIO-based single-channel multi-data source transmission system according to claim 1, characterized in that: The DSP doorbell module identifies the interrupt source of the doorbell interrupt and uses the DoorBell interrupt to notify the DSP subsystem; after the DSP subsystem enters the doorbell interrupt, it first searches for the interface channel interrupt according to the DoorBell doorbell interrupt, and then identifies the address area of ​​the chip cyclic polling and the effective byte length of each chip address area through the EMIF status module.

6. The SRIO-based single-channel multi-data source transmission system according to claim 1, characterized in that: After the FPGA preprocessing module completes data packaging and before the SRIO sending module sends the doorbell packet, the FPGA subsystem updates the latest status result of the current interface channel and stores it through the EMIF status module.

7. A transmission method of a single-channel multi-data source transmission system based on SRIO according to any one of claims 1 to 6, comprising a data uplink process and a data downlink process; characterized in that: The data uplink process includes: the FPGA subsystem receives data from the hardware of multiple external interfaces, performs data preprocessing through the FPGA preprocessing module, processes and packages the data of each interface channel according to the preset doorbell interrupt protocol and chip cycle protocol, and then sends the data packet and the doorbell packet to the DSP subsystem through the SRIO sending module, sends the multi-channel data of the previous stage to the DSP through an SRIO channel, and the DSP performs data caching by the DDR3 of the DSP; the speed of the SRIO sending module is much faster than the packaging speed of the preprocessing module of the previous stage; when there is only one channel to be sent, the data of this channel is directly sent out; when there are two or more channels of data to be sent, the data packets are sent out in sequence according to the channel number; After receiving the data, the SRIO bottom layer of the DSP starts DMA to move the data, and stores the data in the corresponding memory area of ​​the DSP one by one according to the address and length of the SRIO packet header protocol; after receiving the doorbell interrupt, first verify the current interrupt source identification channel, then query the EMIF status module of the channel, query the first address of the current interrupt slice cycle and the first address of the previous slice cycle of the current channel, and the short packet complement interface will simultaneously identify the number of valid data bytes of each slice address, and then extract the valid data between the two interrupts for subsequent application layer processing; The data downlink process includes: the DSP subsystem sends data in batches and at different times; the FPGA subsystem encapsulates the data according to the agreed interface channel protocol; the FPGA subsystem identifies the header address information in the packet, determines which interface channel the data belongs to, extracts the data, and directly puts the data into the corresponding interface FIFO for external transmission in the order in which the packets are received.

8. The single-channel multi-data source transmission method based on SRIO according to claim 7, characterized in that: The doorbell interrupt protocol stipulates the amount of interrupt data for each channel; when the amount of data for a channel sent by the FPGA reaches one packet, two packets, or more packets, it is necessary to send a doorbell interrupt notification to the DSP. The packet header address protocol within a doorbell is accumulated according to the first address of this chip cycle, and the next doorbell requires a new chip cycle first address for accumulation.

9. The single-channel multi-data source transmission method based on SRIO according to claim 7, characterized in that: The chip cycle protocol stipulates how many doorbell interrupts a channel can store continuously and the length of a single doorbell interrupt data; after sending a doorbell, the new data needs to offset the first address of the packet header according to the chip cycle protocol to ensure that the data area is continuous and can be arranged continuously according to the length of the doorbell; at the same time, after the DSP turns off the interrupt and turns it on again, the DSP queries the status register value of the FPGA chip cycle through the EMIF status module, detects the interval area between the two interrupts, and can fully identify the cached data in DDR3.

10. The single-channel multi-data source transmission method based on SRIO according to claim 9, characterized in that: When processing short packet data according to the chip loop protocol polling, the FPGA needs to perform data packet break processing for discontinuous short packet type data; judge the broken packet according to time; use the complement or packetization or doorbell interrupt method to process the data with inconsistent length; wait for the continuous data to meet 256 bytes and encapsulate it into a SWRITE packet.

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